Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9419218 |
1 |
|
|
T32 |
9044 |
|
T1 |
60 |
|
T11 |
69 |
| auto[1] |
7407388 |
1 |
|
|
T32 |
5929 |
|
T1 |
6 |
|
T11 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13855948 |
1 |
|
|
T32 |
10335 |
|
T1 |
62 |
|
T11 |
88 |
| auto[1] |
2970658 |
1 |
|
|
T32 |
4638 |
|
T1 |
4 |
|
T11 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9443859 |
1 |
|
|
T32 |
8109 |
|
T1 |
56 |
|
T11 |
83 |
| auto[1] |
7382747 |
1 |
|
|
T32 |
6864 |
|
T1 |
10 |
|
T11 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2199167 |
1 |
|
|
T32 |
1202 |
|
T1 |
6 |
|
T11 |
5 |
| auto[1] |
auto[0] |
auto[1] |
1482673 |
1 |
|
|
T32 |
2392 |
|
T1 |
4 |
|
T11 |
11 |
| auto[1] |
auto[1] |
auto[0] |
2212922 |
1 |
|
|
T32 |
1024 |
|
T13 |
62739 |
|
T2 |
4477 |
| auto[1] |
auto[1] |
auto[1] |
1487985 |
1 |
|
|
T32 |
2246 |
|
T13 |
36593 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |