Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9416045 |
1 |
|
|
T32 |
9188 |
|
T1 |
60 |
|
T11 |
53 |
| auto[1] |
7410561 |
1 |
|
|
T32 |
5785 |
|
T1 |
6 |
|
T11 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13862074 |
1 |
|
|
T32 |
9792 |
|
T1 |
62 |
|
T11 |
96 |
| auto[1] |
2964532 |
1 |
|
|
T32 |
5181 |
|
T1 |
4 |
|
T11 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9446113 |
1 |
|
|
T32 |
7323 |
|
T1 |
50 |
|
T11 |
77 |
| auto[1] |
7380493 |
1 |
|
|
T32 |
7650 |
|
T1 |
16 |
|
T11 |
22 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2193554 |
1 |
|
|
T32 |
1669 |
|
T1 |
9 |
|
T11 |
4 |
| auto[1] |
auto[0] |
auto[1] |
1474606 |
1 |
|
|
T32 |
3690 |
|
T1 |
4 |
|
T13 |
37244 |
| auto[1] |
auto[1] |
auto[0] |
2222407 |
1 |
|
|
T32 |
800 |
|
T1 |
3 |
|
T11 |
15 |
| auto[1] |
auto[1] |
auto[1] |
1489926 |
1 |
|
|
T32 |
1491 |
|
T11 |
3 |
|
T13 |
35827 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |