Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9426266 |
1 |
|
|
T32 |
8132 |
|
T1 |
60 |
|
T11 |
53 |
| auto[1] |
7400340 |
1 |
|
|
T32 |
6841 |
|
T1 |
6 |
|
T11 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13853670 |
1 |
|
|
T32 |
10882 |
|
T1 |
58 |
|
T11 |
94 |
| auto[1] |
2972936 |
1 |
|
|
T32 |
4091 |
|
T1 |
8 |
|
T11 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9440079 |
1 |
|
|
T32 |
8928 |
|
T1 |
56 |
|
T11 |
83 |
| auto[1] |
7386527 |
1 |
|
|
T32 |
6045 |
|
T1 |
10 |
|
T11 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2212703 |
1 |
|
|
T32 |
837 |
|
T1 |
2 |
|
T11 |
6 |
| auto[1] |
auto[0] |
auto[1] |
1487563 |
1 |
|
|
T32 |
1823 |
|
T1 |
8 |
|
T11 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2200888 |
1 |
|
|
T32 |
1117 |
|
T11 |
5 |
|
T13 |
62197 |
| auto[1] |
auto[1] |
auto[1] |
1485373 |
1 |
|
|
T32 |
2268 |
|
T13 |
36436 |
|
T2 |
8089 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |