Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3219468 |
1 |
|
|
T32 |
2233 |
|
T1 |
12 |
|
T13 |
84051 |
| auto[1] |
auto[0] |
auto[1] |
466357 |
1 |
|
|
T32 |
187 |
|
T13 |
11545 |
|
T16 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3218526 |
1 |
|
|
T32 |
3722 |
|
T1 |
5 |
|
T11 |
10 |
| auto[1] |
auto[1] |
auto[1] |
467288 |
1 |
|
|
T32 |
478 |
|
T1 |
1 |
|
T13 |
12886 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |