Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9412279 |
1 |
|
|
T32 |
8032 |
|
T1 |
40 |
|
T11 |
88 |
| auto[1] |
7414327 |
1 |
|
|
T32 |
6941 |
|
T1 |
26 |
|
T11 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13874011 |
1 |
|
|
T32 |
10893 |
|
T1 |
65 |
|
T11 |
81 |
| auto[1] |
2952595 |
1 |
|
|
T32 |
4080 |
|
T1 |
1 |
|
T11 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9476190 |
1 |
|
|
T32 |
8809 |
|
T1 |
43 |
|
T11 |
76 |
| auto[1] |
7350416 |
1 |
|
|
T32 |
6164 |
|
T1 |
23 |
|
T11 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2196358 |
1 |
|
|
T32 |
940 |
|
T1 |
10 |
|
T11 |
5 |
| auto[1] |
auto[0] |
auto[1] |
1477238 |
1 |
|
|
T32 |
1839 |
|
T1 |
1 |
|
T11 |
15 |
| auto[1] |
auto[1] |
auto[0] |
2201463 |
1 |
|
|
T32 |
1144 |
|
T1 |
12 |
|
T13 |
66733 |
| auto[1] |
auto[1] |
auto[1] |
1475357 |
1 |
|
|
T32 |
2241 |
|
T11 |
3 |
|
T13 |
37848 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |