Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9417417 |
1 |
|
|
T32 |
7865 |
|
T1 |
40 |
|
T11 |
72 |
| auto[1] |
7409189 |
1 |
|
|
T32 |
7108 |
|
T1 |
26 |
|
T11 |
27 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13869781 |
1 |
|
|
T32 |
11165 |
|
T1 |
66 |
|
T11 |
94 |
| auto[1] |
2956825 |
1 |
|
|
T32 |
3808 |
|
T11 |
5 |
|
T13 |
71543 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9459076 |
1 |
|
|
T32 |
9145 |
|
T1 |
46 |
|
T11 |
80 |
| auto[1] |
7367530 |
1 |
|
|
T32 |
5828 |
|
T1 |
20 |
|
T11 |
19 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2209455 |
1 |
|
|
T32 |
848 |
|
T1 |
11 |
|
T11 |
9 |
| auto[1] |
auto[0] |
auto[1] |
1480700 |
1 |
|
|
T32 |
1640 |
|
T11 |
5 |
|
T13 |
35689 |
| auto[1] |
auto[1] |
auto[0] |
2201250 |
1 |
|
|
T32 |
1172 |
|
T1 |
9 |
|
T11 |
5 |
| auto[1] |
auto[1] |
auto[1] |
1476125 |
1 |
|
|
T32 |
2168 |
|
T13 |
35854 |
|
T16 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |