Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9432045 |
1 |
|
|
T32 |
7258 |
|
T1 |
40 |
|
T11 |
58 |
| auto[1] |
7394561 |
1 |
|
|
T32 |
7715 |
|
T1 |
26 |
|
T11 |
41 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13857753 |
1 |
|
|
T32 |
10280 |
|
T1 |
54 |
|
T11 |
92 |
| auto[1] |
2968853 |
1 |
|
|
T32 |
4693 |
|
T1 |
12 |
|
T11 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9442952 |
1 |
|
|
T32 |
8087 |
|
T1 |
50 |
|
T11 |
85 |
| auto[1] |
7383654 |
1 |
|
|
T32 |
6886 |
|
T1 |
16 |
|
T11 |
14 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2199407 |
1 |
|
|
T32 |
916 |
|
T1 |
1 |
|
T11 |
4 |
| auto[1] |
auto[0] |
auto[1] |
1483254 |
1 |
|
|
T32 |
1737 |
|
T1 |
3 |
|
T11 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2215394 |
1 |
|
|
T32 |
1277 |
|
T1 |
3 |
|
T11 |
3 |
| auto[1] |
auto[1] |
auto[1] |
1485599 |
1 |
|
|
T32 |
2956 |
|
T1 |
9 |
|
T11 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |