Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9443226 |
1 |
|
|
T32 |
8161 |
|
T1 |
49 |
|
T11 |
65 |
| auto[1] |
7383380 |
1 |
|
|
T32 |
6812 |
|
T1 |
17 |
|
T11 |
34 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13840776 |
1 |
|
|
T32 |
10682 |
|
T1 |
60 |
|
T11 |
88 |
| auto[1] |
2985830 |
1 |
|
|
T32 |
4291 |
|
T1 |
6 |
|
T11 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9406433 |
1 |
|
|
T32 |
8623 |
|
T1 |
60 |
|
T11 |
86 |
| auto[1] |
7420173 |
1 |
|
|
T32 |
6350 |
|
T1 |
6 |
|
T11 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2225316 |
1 |
|
|
T32 |
1019 |
|
T11 |
2 |
|
T13 |
64470 |
| auto[1] |
auto[0] |
auto[1] |
1501239 |
1 |
|
|
T32 |
2197 |
|
T1 |
3 |
|
T11 |
11 |
| auto[1] |
auto[1] |
auto[0] |
2209027 |
1 |
|
|
T32 |
1040 |
|
T13 |
66636 |
|
T2 |
4309 |
| auto[1] |
auto[1] |
auto[1] |
1484591 |
1 |
|
|
T32 |
2094 |
|
T1 |
3 |
|
T13 |
38547 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |