Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9453491 |
1 |
|
|
T32 |
8869 |
|
T1 |
40 |
|
T11 |
52 |
| auto[1] |
7373115 |
1 |
|
|
T32 |
6104 |
|
T1 |
26 |
|
T11 |
47 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13871529 |
1 |
|
|
T32 |
9987 |
|
T1 |
63 |
|
T11 |
95 |
| auto[1] |
2955077 |
1 |
|
|
T32 |
4986 |
|
T1 |
3 |
|
T11 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9475971 |
1 |
|
|
T32 |
7682 |
|
T1 |
60 |
|
T11 |
75 |
| auto[1] |
7350635 |
1 |
|
|
T32 |
7291 |
|
T1 |
6 |
|
T11 |
24 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2226705 |
1 |
|
|
T32 |
1398 |
|
T1 |
3 |
|
T11 |
12 |
| auto[1] |
auto[0] |
auto[1] |
1490200 |
1 |
|
|
T32 |
3098 |
|
T1 |
3 |
|
T11 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2168853 |
1 |
|
|
T32 |
907 |
|
T11 |
8 |
|
T13 |
60599 |
| auto[1] |
auto[1] |
auto[1] |
1464877 |
1 |
|
|
T32 |
1888 |
|
T11 |
3 |
|
T13 |
36377 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |