Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9429746 |
1 |
|
|
T32 |
7710 |
|
T1 |
51 |
|
T11 |
58 |
| auto[1] |
7396860 |
1 |
|
|
T32 |
7263 |
|
T1 |
15 |
|
T11 |
41 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13856468 |
1 |
|
|
T32 |
10708 |
|
T1 |
66 |
|
T11 |
83 |
| auto[1] |
2970138 |
1 |
|
|
T32 |
4265 |
|
T11 |
16 |
|
T13 |
74220 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9437659 |
1 |
|
|
T32 |
8575 |
|
T1 |
56 |
|
T11 |
83 |
| auto[1] |
7388947 |
1 |
|
|
T32 |
6398 |
|
T1 |
10 |
|
T11 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2196610 |
1 |
|
|
T32 |
1049 |
|
T1 |
1 |
|
T13 |
60570 |
| auto[1] |
auto[0] |
auto[1] |
1483129 |
1 |
|
|
T32 |
2285 |
|
T11 |
6 |
|
T13 |
36020 |
| auto[1] |
auto[1] |
auto[0] |
2222199 |
1 |
|
|
T32 |
1084 |
|
T1 |
9 |
|
T13 |
66826 |
| auto[1] |
auto[1] |
auto[1] |
1487009 |
1 |
|
|
T32 |
1980 |
|
T11 |
10 |
|
T13 |
38200 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |