Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9445066 |
1 |
|
|
T32 |
7638 |
|
T1 |
60 |
|
T11 |
58 |
| auto[1] |
7381540 |
1 |
|
|
T32 |
7335 |
|
T1 |
6 |
|
T11 |
41 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13855604 |
1 |
|
|
T32 |
10542 |
|
T1 |
60 |
|
T11 |
90 |
| auto[1] |
2971002 |
1 |
|
|
T32 |
4431 |
|
T1 |
6 |
|
T11 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9423019 |
1 |
|
|
T32 |
8416 |
|
T1 |
50 |
|
T11 |
69 |
| auto[1] |
7403587 |
1 |
|
|
T32 |
6557 |
|
T1 |
16 |
|
T11 |
30 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2225049 |
1 |
|
|
T32 |
952 |
|
T1 |
7 |
|
T11 |
7 |
| auto[1] |
auto[0] |
auto[1] |
1494863 |
1 |
|
|
T32 |
2056 |
|
T1 |
6 |
|
T11 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2207536 |
1 |
|
|
T32 |
1174 |
|
T1 |
3 |
|
T11 |
14 |
| auto[1] |
auto[1] |
auto[1] |
1476139 |
1 |
|
|
T32 |
2375 |
|
T11 |
4 |
|
T13 |
36396 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |