Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9402221 |
1 |
|
|
T32 |
7837 |
|
T1 |
46 |
|
T11 |
77 |
| auto[1] |
7424385 |
1 |
|
|
T32 |
7136 |
|
T1 |
20 |
|
T11 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13865457 |
1 |
|
|
T32 |
11017 |
|
T1 |
51 |
|
T11 |
93 |
| auto[1] |
2961149 |
1 |
|
|
T32 |
3956 |
|
T1 |
15 |
|
T11 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9449765 |
1 |
|
|
T32 |
9079 |
|
T1 |
46 |
|
T11 |
67 |
| auto[1] |
7376841 |
1 |
|
|
T32 |
5894 |
|
T1 |
20 |
|
T11 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2207215 |
1 |
|
|
T32 |
964 |
|
T1 |
3 |
|
T11 |
19 |
| auto[1] |
auto[0] |
auto[1] |
1479825 |
1 |
|
|
T32 |
2147 |
|
T1 |
8 |
|
T11 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2208477 |
1 |
|
|
T32 |
974 |
|
T1 |
2 |
|
T11 |
7 |
| auto[1] |
auto[1] |
auto[1] |
1481324 |
1 |
|
|
T32 |
1809 |
|
T1 |
7 |
|
T11 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |