Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9404564 |
1 |
|
|
T32 |
8182 |
|
T1 |
66 |
|
T11 |
62 |
| auto[1] |
7422042 |
1 |
|
|
T32 |
6791 |
|
T11 |
37 |
|
T13 |
201195 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13852658 |
1 |
|
|
T32 |
10383 |
|
T1 |
60 |
|
T11 |
91 |
| auto[1] |
2973948 |
1 |
|
|
T32 |
4590 |
|
T1 |
6 |
|
T11 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9432826 |
1 |
|
|
T32 |
8183 |
|
T1 |
56 |
|
T11 |
75 |
| auto[1] |
7393780 |
1 |
|
|
T32 |
6790 |
|
T1 |
10 |
|
T11 |
24 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2209912 |
1 |
|
|
T32 |
1086 |
|
T1 |
4 |
|
T11 |
9 |
| auto[1] |
auto[0] |
auto[1] |
1485126 |
1 |
|
|
T32 |
2240 |
|
T1 |
6 |
|
T11 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2209920 |
1 |
|
|
T32 |
1114 |
|
T11 |
7 |
|
T13 |
63567 |
| auto[1] |
auto[1] |
auto[1] |
1488822 |
1 |
|
|
T32 |
2350 |
|
T11 |
3 |
|
T13 |
37202 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |