Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9457233 |
1 |
|
|
T32 |
6842 |
|
T1 |
49 |
|
T11 |
77 |
| auto[1] |
7369373 |
1 |
|
|
T32 |
8131 |
|
T1 |
17 |
|
T11 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15885440 |
1 |
|
|
T32 |
14400 |
|
T1 |
65 |
|
T11 |
99 |
| auto[1] |
941166 |
1 |
|
|
T32 |
573 |
|
T1 |
1 |
|
T13 |
25957 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9401835 |
1 |
|
|
T32 |
8743 |
|
T1 |
51 |
|
T11 |
84 |
| auto[1] |
7424771 |
1 |
|
|
T32 |
6230 |
|
T1 |
15 |
|
T11 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3253350 |
1 |
|
|
T32 |
2771 |
|
T1 |
10 |
|
T11 |
11 |
| auto[1] |
auto[0] |
auto[1] |
473147 |
1 |
|
|
T32 |
277 |
|
T1 |
1 |
|
T13 |
12620 |
| auto[1] |
auto[1] |
auto[0] |
3230255 |
1 |
|
|
T32 |
2886 |
|
T1 |
4 |
|
T11 |
4 |
| auto[1] |
auto[1] |
auto[1] |
468019 |
1 |
|
|
T32 |
296 |
|
T13 |
13337 |
|
T2 |
1459 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |