Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9430577 |
1 |
|
|
T32 |
7617 |
|
T1 |
49 |
|
T11 |
78 |
| auto[1] |
7396029 |
1 |
|
|
T32 |
7356 |
|
T1 |
17 |
|
T11 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13852303 |
1 |
|
|
T32 |
10126 |
|
T1 |
59 |
|
T11 |
93 |
| auto[1] |
2974303 |
1 |
|
|
T32 |
4847 |
|
T1 |
7 |
|
T11 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9431222 |
1 |
|
|
T32 |
7745 |
|
T1 |
59 |
|
T11 |
80 |
| auto[1] |
7395384 |
1 |
|
|
T32 |
7228 |
|
T1 |
7 |
|
T11 |
19 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2201300 |
1 |
|
|
T32 |
881 |
|
T11 |
13 |
|
T13 |
61114 |
| auto[1] |
auto[0] |
auto[1] |
1483946 |
1 |
|
|
T32 |
1845 |
|
T1 |
7 |
|
T11 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2219781 |
1 |
|
|
T32 |
1500 |
|
T13 |
65118 |
|
T2 |
4173 |
| auto[1] |
auto[1] |
auto[1] |
1490357 |
1 |
|
|
T32 |
3002 |
|
T11 |
2 |
|
T13 |
37757 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |