Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9452869 |
1 |
|
|
T32 |
9260 |
|
T1 |
46 |
|
T11 |
73 |
| auto[1] |
7373737 |
1 |
|
|
T32 |
5713 |
|
T1 |
20 |
|
T11 |
26 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13860436 |
1 |
|
|
T32 |
10142 |
|
T1 |
58 |
|
T11 |
87 |
| auto[1] |
2966170 |
1 |
|
|
T32 |
4831 |
|
T1 |
8 |
|
T11 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9443247 |
1 |
|
|
T32 |
7886 |
|
T1 |
50 |
|
T11 |
78 |
| auto[1] |
7383359 |
1 |
|
|
T32 |
7087 |
|
T1 |
16 |
|
T11 |
21 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2219922 |
1 |
|
|
T32 |
1449 |
|
T1 |
3 |
|
T11 |
9 |
| auto[1] |
auto[0] |
auto[1] |
1483986 |
1 |
|
|
T32 |
3102 |
|
T1 |
4 |
|
T11 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2197267 |
1 |
|
|
T32 |
807 |
|
T1 |
5 |
|
T13 |
61040 |
| auto[1] |
auto[1] |
auto[1] |
1482184 |
1 |
|
|
T32 |
1729 |
|
T1 |
4 |
|
T13 |
35642 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |