Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9398819 |
1 |
|
|
T32 |
8621 |
|
T1 |
46 |
|
T11 |
78 |
| auto[1] |
7427787 |
1 |
|
|
T32 |
6352 |
|
T1 |
20 |
|
T11 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15888616 |
1 |
|
|
T32 |
14234 |
|
T1 |
65 |
|
T11 |
99 |
| auto[1] |
937990 |
1 |
|
|
T32 |
739 |
|
T1 |
1 |
|
T13 |
24821 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9422062 |
1 |
|
|
T32 |
7142 |
|
T1 |
38 |
|
T11 |
83 |
| auto[1] |
7404544 |
1 |
|
|
T32 |
7831 |
|
T1 |
28 |
|
T11 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3227720 |
1 |
|
|
T32 |
3847 |
|
T1 |
9 |
|
T11 |
11 |
| auto[1] |
auto[0] |
auto[1] |
468037 |
1 |
|
|
T32 |
402 |
|
T13 |
12304 |
|
T2 |
1321 |
| auto[1] |
auto[1] |
auto[0] |
3238834 |
1 |
|
|
T32 |
3245 |
|
T1 |
18 |
|
T11 |
5 |
| auto[1] |
auto[1] |
auto[1] |
469953 |
1 |
|
|
T32 |
337 |
|
T1 |
1 |
|
T13 |
12517 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |