Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9434248 |
1 |
|
|
T32 |
9605 |
|
T1 |
40 |
|
T11 |
54 |
| auto[1] |
7392358 |
1 |
|
|
T32 |
5368 |
|
T1 |
26 |
|
T11 |
45 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15893254 |
1 |
|
|
T32 |
14261 |
|
T1 |
66 |
|
T11 |
99 |
| auto[1] |
933352 |
1 |
|
|
T32 |
712 |
|
T13 |
23853 |
|
T2 |
2724 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9441646 |
1 |
|
|
T32 |
7722 |
|
T1 |
59 |
|
T11 |
81 |
| auto[1] |
7384960 |
1 |
|
|
T32 |
7251 |
|
T1 |
7 |
|
T11 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3218887 |
1 |
|
|
T32 |
3874 |
|
T1 |
3 |
|
T11 |
8 |
| auto[1] |
auto[0] |
auto[1] |
464704 |
1 |
|
|
T32 |
489 |
|
T13 |
12358 |
|
T2 |
1423 |
| auto[1] |
auto[1] |
auto[0] |
3232721 |
1 |
|
|
T32 |
2665 |
|
T1 |
4 |
|
T11 |
10 |
| auto[1] |
auto[1] |
auto[1] |
468648 |
1 |
|
|
T32 |
223 |
|
T13 |
11495 |
|
T2 |
1301 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |