Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9409085 |
1 |
|
|
T32 |
7211 |
|
T1 |
66 |
|
T11 |
82 |
| auto[1] |
7417521 |
1 |
|
|
T32 |
7762 |
|
T11 |
17 |
|
T13 |
203619 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15886115 |
1 |
|
|
T32 |
14121 |
|
T1 |
66 |
|
T11 |
99 |
| auto[1] |
940491 |
1 |
|
|
T32 |
852 |
|
T13 |
25166 |
|
T2 |
2655 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9409712 |
1 |
|
|
T32 |
7023 |
|
T1 |
58 |
|
T11 |
81 |
| auto[1] |
7416894 |
1 |
|
|
T32 |
7950 |
|
T1 |
8 |
|
T11 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3226876 |
1 |
|
|
T32 |
2595 |
|
T1 |
8 |
|
T11 |
9 |
| auto[1] |
auto[0] |
auto[1] |
468521 |
1 |
|
|
T32 |
229 |
|
T13 |
11832 |
|
T2 |
1379 |
| auto[1] |
auto[1] |
auto[0] |
3249527 |
1 |
|
|
T32 |
4503 |
|
T11 |
9 |
|
T13 |
92120 |
| auto[1] |
auto[1] |
auto[1] |
471970 |
1 |
|
|
T32 |
623 |
|
T13 |
13334 |
|
T2 |
1276 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |