Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9408817 |
1 |
|
|
T32 |
6749 |
|
T1 |
40 |
|
T11 |
89 |
| auto[1] |
7417789 |
1 |
|
|
T32 |
8224 |
|
T1 |
26 |
|
T11 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15893632 |
1 |
|
|
T32 |
14350 |
|
T1 |
66 |
|
T11 |
98 |
| auto[1] |
932974 |
1 |
|
|
T32 |
623 |
|
T11 |
1 |
|
T13 |
24963 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9453487 |
1 |
|
|
T32 |
8247 |
|
T1 |
49 |
|
T11 |
76 |
| auto[1] |
7373119 |
1 |
|
|
T32 |
6726 |
|
T1 |
17 |
|
T11 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3220831 |
1 |
|
|
T32 |
2651 |
|
T1 |
7 |
|
T11 |
17 |
| auto[1] |
auto[0] |
auto[1] |
467161 |
1 |
|
|
T32 |
212 |
|
T11 |
1 |
|
T13 |
12010 |
| auto[1] |
auto[1] |
auto[0] |
3219314 |
1 |
|
|
T32 |
3452 |
|
T1 |
10 |
|
T11 |
5 |
| auto[1] |
auto[1] |
auto[1] |
465813 |
1 |
|
|
T32 |
411 |
|
T13 |
12953 |
|
T2 |
1333 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |