Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9454544 |
1 |
|
|
T32 |
7528 |
|
T1 |
60 |
|
T11 |
69 |
| auto[1] |
7372062 |
1 |
|
|
T32 |
7445 |
|
T1 |
6 |
|
T11 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15888700 |
1 |
|
|
T32 |
14293 |
|
T1 |
66 |
|
T11 |
99 |
| auto[1] |
937906 |
1 |
|
|
T32 |
680 |
|
T13 |
25189 |
|
T16 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9422363 |
1 |
|
|
T32 |
8176 |
|
T1 |
44 |
|
T11 |
79 |
| auto[1] |
7404243 |
1 |
|
|
T32 |
6797 |
|
T1 |
22 |
|
T11 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3235734 |
1 |
|
|
T32 |
2020 |
|
T1 |
22 |
|
T11 |
10 |
| auto[1] |
auto[0] |
auto[1] |
468084 |
1 |
|
|
T32 |
163 |
|
T13 |
12556 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3230603 |
1 |
|
|
T32 |
4097 |
|
T11 |
10 |
|
T13 |
87080 |
| auto[1] |
auto[1] |
auto[1] |
469822 |
1 |
|
|
T32 |
517 |
|
T13 |
12633 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |