Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 949
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T765 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1803927879 Aug 07 05:11:43 PM PDT 24 Aug 07 05:11:45 PM PDT 24 853626406 ps
T766 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.412990730 Aug 07 05:12:25 PM PDT 24 Aug 07 05:12:28 PM PDT 24 481559376 ps
T767 /workspace/coverage/cover_reg_top/20.gpio_intr_test.1811610187 Aug 07 05:12:31 PM PDT 24 Aug 07 05:12:32 PM PDT 24 35192498 ps
T768 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3726420068 Aug 07 05:12:06 PM PDT 24 Aug 07 05:12:07 PM PDT 24 130773455 ps
T769 /workspace/coverage/cover_reg_top/27.gpio_intr_test.2441649473 Aug 07 05:12:40 PM PDT 24 Aug 07 05:12:41 PM PDT 24 13825774 ps
T770 /workspace/coverage/cover_reg_top/47.gpio_intr_test.2888755916 Aug 07 05:12:43 PM PDT 24 Aug 07 05:12:43 PM PDT 24 18267894 ps
T771 /workspace/coverage/cover_reg_top/45.gpio_intr_test.2937610742 Aug 07 05:12:50 PM PDT 24 Aug 07 05:12:51 PM PDT 24 15611518 ps
T87 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.4092280315 Aug 07 05:12:25 PM PDT 24 Aug 07 05:12:26 PM PDT 24 20359416 ps
T772 /workspace/coverage/cover_reg_top/19.gpio_intr_test.3848275675 Aug 07 05:12:45 PM PDT 24 Aug 07 05:12:45 PM PDT 24 10905469 ps
T773 /workspace/coverage/cover_reg_top/31.gpio_intr_test.2850535868 Aug 07 05:12:49 PM PDT 24 Aug 07 05:12:49 PM PDT 24 13987527 ps
T774 /workspace/coverage/cover_reg_top/1.gpio_intr_test.2394323234 Aug 07 05:11:36 PM PDT 24 Aug 07 05:11:37 PM PDT 24 49219454 ps
T775 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1740974462 Aug 07 05:11:31 PM PDT 24 Aug 07 05:11:32 PM PDT 24 64671217 ps
T776 /workspace/coverage/cover_reg_top/29.gpio_intr_test.3614654020 Aug 07 05:12:43 PM PDT 24 Aug 07 05:12:43 PM PDT 24 12155462 ps
T88 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1978110286 Aug 07 05:12:33 PM PDT 24 Aug 07 05:12:34 PM PDT 24 103140485 ps
T777 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3653685849 Aug 07 05:12:16 PM PDT 24 Aug 07 05:12:17 PM PDT 24 49209866 ps
T89 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.883985782 Aug 07 05:12:26 PM PDT 24 Aug 07 05:12:27 PM PDT 24 38926816 ps
T73 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1128102211 Aug 07 05:11:39 PM PDT 24 Aug 07 05:11:40 PM PDT 24 17847653 ps
T778 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2923486144 Aug 07 05:11:47 PM PDT 24 Aug 07 05:11:47 PM PDT 24 47810402 ps
T779 /workspace/coverage/cover_reg_top/37.gpio_intr_test.3667407656 Aug 07 05:12:42 PM PDT 24 Aug 07 05:12:43 PM PDT 24 19928185 ps
T90 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1714099102 Aug 07 05:12:26 PM PDT 24 Aug 07 05:12:27 PM PDT 24 33966831 ps
T780 /workspace/coverage/cover_reg_top/23.gpio_intr_test.3478364633 Aug 07 05:12:38 PM PDT 24 Aug 07 05:12:39 PM PDT 24 16389858 ps
T96 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2926104689 Aug 07 05:12:10 PM PDT 24 Aug 07 05:12:11 PM PDT 24 134500385 ps
T74 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2739313883 Aug 07 05:11:55 PM PDT 24 Aug 07 05:11:56 PM PDT 24 17272900 ps
T781 /workspace/coverage/cover_reg_top/42.gpio_intr_test.1984423494 Aug 07 05:12:45 PM PDT 24 Aug 07 05:12:46 PM PDT 24 14364955 ps
T782 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3296172970 Aug 07 05:12:16 PM PDT 24 Aug 07 05:12:17 PM PDT 24 51255834 ps
T783 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3364976596 Aug 07 05:12:46 PM PDT 24 Aug 07 05:12:47 PM PDT 24 43694531 ps
T784 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3241454206 Aug 07 05:12:23 PM PDT 24 Aug 07 05:12:24 PM PDT 24 86494831 ps
T785 /workspace/coverage/cover_reg_top/12.gpio_intr_test.3106737569 Aug 07 05:12:21 PM PDT 24 Aug 07 05:12:22 PM PDT 24 12482090 ps
T75 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2270204220 Aug 07 05:12:17 PM PDT 24 Aug 07 05:12:17 PM PDT 24 61449964 ps
T786 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1245272411 Aug 07 05:12:04 PM PDT 24 Aug 07 05:12:05 PM PDT 24 85589175 ps
T787 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.4095469673 Aug 07 05:11:29 PM PDT 24 Aug 07 05:11:29 PM PDT 24 45981994 ps
T788 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2654086347 Aug 07 05:12:26 PM PDT 24 Aug 07 05:12:27 PM PDT 24 64660880 ps
T789 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.4213672804 Aug 07 05:12:07 PM PDT 24 Aug 07 05:12:08 PM PDT 24 25774308 ps
T790 /workspace/coverage/cover_reg_top/22.gpio_intr_test.3619374864 Aug 07 05:12:46 PM PDT 24 Aug 07 05:12:46 PM PDT 24 16362169 ps
T791 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2486882404 Aug 07 05:11:57 PM PDT 24 Aug 07 05:11:58 PM PDT 24 138110814 ps
T792 /workspace/coverage/cover_reg_top/48.gpio_intr_test.1841341783 Aug 07 05:12:51 PM PDT 24 Aug 07 05:12:52 PM PDT 24 14698453 ps
T793 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.947099503 Aug 07 05:11:53 PM PDT 24 Aug 07 05:11:55 PM PDT 24 115059435 ps
T794 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.117764314 Aug 07 05:12:23 PM PDT 24 Aug 07 05:12:24 PM PDT 24 135687802 ps
T795 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2507939760 Aug 07 05:11:59 PM PDT 24 Aug 07 05:12:00 PM PDT 24 78371314 ps
T76 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3352608190 Aug 07 05:11:32 PM PDT 24 Aug 07 05:11:33 PM PDT 24 42519716 ps
T796 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3330578678 Aug 07 05:12:23 PM PDT 24 Aug 07 05:12:24 PM PDT 24 23933741 ps
T797 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3163574312 Aug 07 05:11:40 PM PDT 24 Aug 07 05:11:40 PM PDT 24 24260270 ps
T798 /workspace/coverage/cover_reg_top/21.gpio_intr_test.1904251086 Aug 07 05:12:46 PM PDT 24 Aug 07 05:12:47 PM PDT 24 12025372 ps
T799 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.4096188486 Aug 07 05:12:37 PM PDT 24 Aug 07 05:12:39 PM PDT 24 38583218 ps
T800 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.145022110 Aug 07 05:12:35 PM PDT 24 Aug 07 05:12:36 PM PDT 24 73911225 ps
T801 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1769027600 Aug 07 05:12:05 PM PDT 24 Aug 07 05:12:06 PM PDT 24 111521764 ps
T802 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3386799963 Aug 07 05:11:48 PM PDT 24 Aug 07 05:11:49 PM PDT 24 53707729 ps
T803 /workspace/coverage/cover_reg_top/32.gpio_intr_test.4288834287 Aug 07 05:12:50 PM PDT 24 Aug 07 05:12:50 PM PDT 24 39043350 ps
T804 /workspace/coverage/cover_reg_top/11.gpio_intr_test.2120685418 Aug 07 05:12:18 PM PDT 24 Aug 07 05:12:19 PM PDT 24 13370905 ps
T805 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.965711011 Aug 07 05:11:27 PM PDT 24 Aug 07 05:11:28 PM PDT 24 34487466 ps
T806 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3540247008 Aug 07 05:12:04 PM PDT 24 Aug 07 05:12:06 PM PDT 24 44902063 ps
T77 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1353898282 Aug 07 05:11:53 PM PDT 24 Aug 07 05:11:55 PM PDT 24 94070713 ps
T78 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.311813346 Aug 07 05:11:49 PM PDT 24 Aug 07 05:11:49 PM PDT 24 37853993 ps
T807 /workspace/coverage/cover_reg_top/38.gpio_intr_test.3529301713 Aug 07 05:12:45 PM PDT 24 Aug 07 05:12:46 PM PDT 24 15835015 ps
T808 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3795617969 Aug 07 05:11:48 PM PDT 24 Aug 07 05:11:49 PM PDT 24 33227444 ps
T809 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.133260248 Aug 07 05:12:19 PM PDT 24 Aug 07 05:12:20 PM PDT 24 79476558 ps
T810 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3474422727 Aug 07 05:12:27 PM PDT 24 Aug 07 05:12:28 PM PDT 24 104558205 ps
T811 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3234178000 Aug 07 05:11:36 PM PDT 24 Aug 07 05:11:38 PM PDT 24 107977645 ps
T812 /workspace/coverage/cover_reg_top/39.gpio_intr_test.1857687178 Aug 07 05:12:43 PM PDT 24 Aug 07 05:12:44 PM PDT 24 18965600 ps
T813 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3956497119 Aug 07 05:12:16 PM PDT 24 Aug 07 05:12:17 PM PDT 24 29367303 ps
T814 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3161402172 Aug 07 05:12:34 PM PDT 24 Aug 07 05:12:35 PM PDT 24 11310638 ps
T79 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2628859465 Aug 07 05:11:31 PM PDT 24 Aug 07 05:11:32 PM PDT 24 62333889 ps
T815 /workspace/coverage/cover_reg_top/30.gpio_intr_test.1173242531 Aug 07 05:12:44 PM PDT 24 Aug 07 05:12:44 PM PDT 24 54249123 ps
T816 /workspace/coverage/cover_reg_top/46.gpio_intr_test.4265216449 Aug 07 05:12:47 PM PDT 24 Aug 07 05:12:47 PM PDT 24 21628040 ps
T817 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.636471277 Aug 07 05:11:29 PM PDT 24 Aug 07 05:11:32 PM PDT 24 122736179 ps
T818 /workspace/coverage/cover_reg_top/33.gpio_intr_test.2554183402 Aug 07 05:12:42 PM PDT 24 Aug 07 05:12:43 PM PDT 24 49653882 ps
T819 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1318590227 Aug 07 05:12:10 PM PDT 24 Aug 07 05:12:11 PM PDT 24 231944708 ps
T820 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3307604076 Aug 07 05:11:47 PM PDT 24 Aug 07 05:11:48 PM PDT 24 25585242 ps
T821 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.4251504913 Aug 07 05:12:17 PM PDT 24 Aug 07 05:12:18 PM PDT 24 132015785 ps
T822 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.813518066 Aug 07 05:11:48 PM PDT 24 Aug 07 05:11:49 PM PDT 24 27961040 ps
T823 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3613642224 Aug 07 05:12:10 PM PDT 24 Aug 07 05:12:11 PM PDT 24 14186099 ps
T824 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2872682842 Aug 07 05:11:53 PM PDT 24 Aug 07 05:11:54 PM PDT 24 91032847 ps
T825 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1983191404 Aug 07 05:11:42 PM PDT 24 Aug 07 05:11:43 PM PDT 24 39725102 ps
T826 /workspace/coverage/cover_reg_top/7.gpio_intr_test.312482849 Aug 07 05:12:04 PM PDT 24 Aug 07 05:12:05 PM PDT 24 17339922 ps
T827 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2562491575 Aug 07 05:12:33 PM PDT 24 Aug 07 05:12:34 PM PDT 24 46351887 ps
T828 /workspace/coverage/cover_reg_top/40.gpio_intr_test.2612510364 Aug 07 05:12:47 PM PDT 24 Aug 07 05:12:47 PM PDT 24 22193363 ps
T81 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3339758498 Aug 07 05:11:40 PM PDT 24 Aug 07 05:11:41 PM PDT 24 26206825 ps
T829 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2587055905 Aug 07 05:11:47 PM PDT 24 Aug 07 05:11:49 PM PDT 24 559632151 ps
T830 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.388427545 Aug 07 05:12:32 PM PDT 24 Aug 07 05:12:35 PM PDT 24 225942903 ps
T831 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3151630762 Aug 07 05:12:15 PM PDT 24 Aug 07 05:12:16 PM PDT 24 53431522 ps
T832 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1407288322 Aug 07 05:12:15 PM PDT 24 Aug 07 05:12:17 PM PDT 24 124911742 ps
T833 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.868659367 Aug 07 05:12:29 PM PDT 24 Aug 07 05:12:30 PM PDT 24 55042308 ps
T834 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3042706175 Aug 07 05:11:48 PM PDT 24 Aug 07 05:11:49 PM PDT 24 27520844 ps
T835 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2585527181 Aug 07 05:12:32 PM PDT 24 Aug 07 05:12:33 PM PDT 24 45367417 ps
T836 /workspace/coverage/cover_reg_top/34.gpio_intr_test.145718344 Aug 07 05:12:44 PM PDT 24 Aug 07 05:12:44 PM PDT 24 16006085 ps
T837 /workspace/coverage/cover_reg_top/5.gpio_intr_test.1105625410 Aug 07 05:11:52 PM PDT 24 Aug 07 05:11:53 PM PDT 24 22800859 ps
T838 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.307265667 Aug 07 05:12:17 PM PDT 24 Aug 07 05:12:18 PM PDT 24 39011576 ps
T839 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2046184497 Aug 07 05:11:32 PM PDT 24 Aug 07 05:11:32 PM PDT 24 46360091 ps
T80 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.490401445 Aug 07 05:12:03 PM PDT 24 Aug 07 05:12:03 PM PDT 24 16450479 ps
T840 /workspace/coverage/cover_reg_top/25.gpio_intr_test.3204892103 Aug 07 05:12:39 PM PDT 24 Aug 07 05:12:40 PM PDT 24 25513058 ps
T841 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1602918178 Aug 07 05:11:27 PM PDT 24 Aug 07 05:11:27 PM PDT 24 19865725 ps
T842 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3675196329 Aug 07 05:12:33 PM PDT 24 Aug 07 05:12:34 PM PDT 24 22604323 ps
T843 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.675535822 Aug 07 05:11:59 PM PDT 24 Aug 07 05:12:00 PM PDT 24 49695721 ps
T844 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.731646106 Aug 07 05:12:28 PM PDT 24 Aug 07 05:12:29 PM PDT 24 18702462 ps
T845 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.841583596 Aug 07 05:11:58 PM PDT 24 Aug 07 05:11:59 PM PDT 24 300359740 ps
T846 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.394227629 Aug 07 05:11:54 PM PDT 24 Aug 07 05:11:55 PM PDT 24 16027086 ps
T847 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.760154207 Aug 07 05:11:54 PM PDT 24 Aug 07 05:11:55 PM PDT 24 80434908 ps
T848 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3366901475 Aug 07 05:11:48 PM PDT 24 Aug 07 05:11:50 PM PDT 24 45229897 ps
T849 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3266465736 Aug 07 05:11:37 PM PDT 24 Aug 07 05:11:40 PM PDT 24 73604947 ps
T850 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4287436341 Aug 07 05:26:19 PM PDT 24 Aug 07 05:26:20 PM PDT 24 125017589 ps
T851 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2292775584 Aug 07 05:26:09 PM PDT 24 Aug 07 05:26:11 PM PDT 24 53267198 ps
T852 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3850107917 Aug 07 05:25:46 PM PDT 24 Aug 07 05:25:48 PM PDT 24 48316496 ps
T853 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1459934140 Aug 07 05:26:28 PM PDT 24 Aug 07 05:26:29 PM PDT 24 41667577 ps
T854 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.53791646 Aug 07 05:26:01 PM PDT 24 Aug 07 05:26:01 PM PDT 24 79255735 ps
T855 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3406374634 Aug 07 05:25:35 PM PDT 24 Aug 07 05:25:37 PM PDT 24 77795374 ps
T856 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3404492834 Aug 07 05:25:26 PM PDT 24 Aug 07 05:25:28 PM PDT 24 62093808 ps
T857 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2172286417 Aug 07 05:25:28 PM PDT 24 Aug 07 05:25:29 PM PDT 24 127888522 ps
T858 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3734009453 Aug 07 05:26:09 PM PDT 24 Aug 07 05:26:10 PM PDT 24 144348981 ps
T859 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2410864480 Aug 07 05:25:06 PM PDT 24 Aug 07 05:25:08 PM PDT 24 133679264 ps
T860 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2460627853 Aug 07 05:26:17 PM PDT 24 Aug 07 05:26:19 PM PDT 24 192597163 ps
T861 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1399439085 Aug 07 05:26:20 PM PDT 24 Aug 07 05:26:21 PM PDT 24 218594858 ps
T862 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3551098621 Aug 07 05:25:08 PM PDT 24 Aug 07 05:25:09 PM PDT 24 119664105 ps
T863 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3359736140 Aug 07 05:26:17 PM PDT 24 Aug 07 05:26:18 PM PDT 24 117013852 ps
T864 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.264561338 Aug 07 05:26:09 PM PDT 24 Aug 07 05:26:11 PM PDT 24 371976452 ps
T865 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.509239906 Aug 07 05:26:25 PM PDT 24 Aug 07 05:26:26 PM PDT 24 89029639 ps
T866 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2363705562 Aug 07 05:26:00 PM PDT 24 Aug 07 05:26:01 PM PDT 24 47448038 ps
T867 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.362123268 Aug 07 05:25:53 PM PDT 24 Aug 07 05:25:54 PM PDT 24 161813526 ps
T868 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3946237278 Aug 07 05:25:29 PM PDT 24 Aug 07 05:25:30 PM PDT 24 48432023 ps
T869 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.509745073 Aug 07 05:25:53 PM PDT 24 Aug 07 05:25:54 PM PDT 24 117116786 ps
T870 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1226590293 Aug 07 05:26:09 PM PDT 24 Aug 07 05:26:11 PM PDT 24 66824405 ps
T871 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1693704513 Aug 07 05:26:09 PM PDT 24 Aug 07 05:26:10 PM PDT 24 38065429 ps
T872 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.22662994 Aug 07 05:26:20 PM PDT 24 Aug 07 05:26:21 PM PDT 24 178559283 ps
T873 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.407562044 Aug 07 05:26:23 PM PDT 24 Aug 07 05:26:24 PM PDT 24 39963656 ps
T874 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3790610939 Aug 07 05:26:04 PM PDT 24 Aug 07 05:26:05 PM PDT 24 49124107 ps
T875 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1870907656 Aug 07 05:25:49 PM PDT 24 Aug 07 05:25:50 PM PDT 24 128223526 ps
T876 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3979650394 Aug 07 05:25:56 PM PDT 24 Aug 07 05:25:58 PM PDT 24 88715054 ps
T877 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1208078845 Aug 07 05:26:16 PM PDT 24 Aug 07 05:26:17 PM PDT 24 800563027 ps
T878 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.620115386 Aug 07 05:26:22 PM PDT 24 Aug 07 05:26:23 PM PDT 24 207333423 ps
T879 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3274585507 Aug 07 05:25:47 PM PDT 24 Aug 07 05:25:48 PM PDT 24 45560003 ps
T880 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1944292832 Aug 07 05:26:20 PM PDT 24 Aug 07 05:26:21 PM PDT 24 106278703 ps
T881 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1604500469 Aug 07 05:26:02 PM PDT 24 Aug 07 05:26:03 PM PDT 24 28252979 ps
T882 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3624092642 Aug 07 05:25:45 PM PDT 24 Aug 07 05:25:46 PM PDT 24 224270479 ps
T883 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.598598543 Aug 07 05:25:52 PM PDT 24 Aug 07 05:25:54 PM PDT 24 326980207 ps
T884 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3072080760 Aug 07 05:25:11 PM PDT 24 Aug 07 05:25:12 PM PDT 24 206629674 ps
T885 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3826365697 Aug 07 05:26:26 PM PDT 24 Aug 07 05:26:27 PM PDT 24 206331046 ps
T886 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3858795050 Aug 07 05:25:47 PM PDT 24 Aug 07 05:25:48 PM PDT 24 28837779 ps
T887 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2045673368 Aug 07 05:25:29 PM PDT 24 Aug 07 05:25:31 PM PDT 24 87837754 ps
T888 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.402969157 Aug 07 05:25:41 PM PDT 24 Aug 07 05:25:42 PM PDT 24 174562648 ps
T889 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.878024632 Aug 07 05:26:09 PM PDT 24 Aug 07 05:26:10 PM PDT 24 227754168 ps
T890 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3388059662 Aug 07 05:25:40 PM PDT 24 Aug 07 05:25:41 PM PDT 24 195882567 ps
T891 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3595817425 Aug 07 05:25:44 PM PDT 24 Aug 07 05:25:45 PM PDT 24 351731102 ps
T892 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2906401711 Aug 07 05:25:54 PM PDT 24 Aug 07 05:25:55 PM PDT 24 54967606 ps
T893 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1969803572 Aug 07 05:26:10 PM PDT 24 Aug 07 05:26:11 PM PDT 24 35927476 ps
T894 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1791111775 Aug 07 05:26:14 PM PDT 24 Aug 07 05:26:15 PM PDT 24 159460017 ps
T895 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2221908616 Aug 07 05:26:11 PM PDT 24 Aug 07 05:26:13 PM PDT 24 46177016 ps
T896 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2436450062 Aug 07 05:26:17 PM PDT 24 Aug 07 05:26:19 PM PDT 24 70542028 ps
T897 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2060290769 Aug 07 05:25:21 PM PDT 24 Aug 07 05:25:22 PM PDT 24 34046794 ps
T898 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1154109307 Aug 07 05:25:29 PM PDT 24 Aug 07 05:25:30 PM PDT 24 109941515 ps
T899 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.485570076 Aug 07 05:25:29 PM PDT 24 Aug 07 05:25:30 PM PDT 24 65110681 ps
T900 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3980939269 Aug 07 05:25:10 PM PDT 24 Aug 07 05:25:11 PM PDT 24 223068878 ps
T901 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2927499237 Aug 07 05:26:26 PM PDT 24 Aug 07 05:26:27 PM PDT 24 114906137 ps
T902 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3940183432 Aug 07 05:26:28 PM PDT 24 Aug 07 05:26:29 PM PDT 24 61499830 ps
T903 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.664497625 Aug 07 05:25:41 PM PDT 24 Aug 07 05:25:42 PM PDT 24 44585416 ps
T904 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3775058590 Aug 07 05:26:09 PM PDT 24 Aug 07 05:26:11 PM PDT 24 242798103 ps
T905 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3527630754 Aug 07 05:25:50 PM PDT 24 Aug 07 05:25:51 PM PDT 24 125180259 ps
T906 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1867406099 Aug 07 05:26:21 PM PDT 24 Aug 07 05:26:22 PM PDT 24 55679210 ps
T907 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3276554412 Aug 07 05:26:20 PM PDT 24 Aug 07 05:26:21 PM PDT 24 70377099 ps
T908 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1324766549 Aug 07 05:25:42 PM PDT 24 Aug 07 05:25:43 PM PDT 24 38822159 ps
T909 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2127581687 Aug 07 05:26:02 PM PDT 24 Aug 07 05:26:03 PM PDT 24 45288404 ps
T910 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.606092204 Aug 07 05:25:04 PM PDT 24 Aug 07 05:25:05 PM PDT 24 90224094 ps
T911 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1628503131 Aug 07 05:26:19 PM PDT 24 Aug 07 05:26:21 PM PDT 24 90073187 ps
T912 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2807594789 Aug 07 05:25:09 PM PDT 24 Aug 07 05:25:10 PM PDT 24 38615768 ps
T913 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.524721197 Aug 07 05:26:16 PM PDT 24 Aug 07 05:26:18 PM PDT 24 475989689 ps
T914 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2041011708 Aug 07 05:25:40 PM PDT 24 Aug 07 05:25:41 PM PDT 24 287050398 ps
T915 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2124085219 Aug 07 05:25:44 PM PDT 24 Aug 07 05:25:45 PM PDT 24 163294253 ps
T916 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.75962578 Aug 07 05:25:29 PM PDT 24 Aug 07 05:25:30 PM PDT 24 79274524 ps
T917 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3380523861 Aug 07 05:25:28 PM PDT 24 Aug 07 05:25:29 PM PDT 24 59414208 ps
T918 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1423023236 Aug 07 05:26:23 PM PDT 24 Aug 07 05:26:25 PM PDT 24 83678307 ps
T919 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1925866464 Aug 07 05:25:09 PM PDT 24 Aug 07 05:25:10 PM PDT 24 132986606 ps
T920 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1836333702 Aug 07 05:26:18 PM PDT 24 Aug 07 05:26:19 PM PDT 24 84998329 ps
T921 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3264253529 Aug 07 05:26:03 PM PDT 24 Aug 07 05:26:04 PM PDT 24 73305696 ps
T922 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3033267484 Aug 07 05:26:16 PM PDT 24 Aug 07 05:26:17 PM PDT 24 112410646 ps
T923 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3127517273 Aug 07 05:25:51 PM PDT 24 Aug 07 05:25:53 PM PDT 24 204640693 ps
T924 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.151503234 Aug 07 05:25:35 PM PDT 24 Aug 07 05:25:36 PM PDT 24 110764153 ps
T925 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3026153004 Aug 07 05:25:47 PM PDT 24 Aug 07 05:25:48 PM PDT 24 199500309 ps
T926 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1361412896 Aug 07 05:25:54 PM PDT 24 Aug 07 05:25:55 PM PDT 24 753467351 ps
T927 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4070965589 Aug 07 05:25:48 PM PDT 24 Aug 07 05:25:49 PM PDT 24 36050509 ps
T928 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.265091157 Aug 07 05:26:02 PM PDT 24 Aug 07 05:26:03 PM PDT 24 210444136 ps
T929 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1587210773 Aug 07 05:25:24 PM PDT 24 Aug 07 05:25:26 PM PDT 24 495350798 ps
T930 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3237579300 Aug 07 05:25:07 PM PDT 24 Aug 07 05:25:08 PM PDT 24 40953541 ps
T931 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.232037302 Aug 07 05:26:11 PM PDT 24 Aug 07 05:26:13 PM PDT 24 298956100 ps
T932 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.152310500 Aug 07 05:26:17 PM PDT 24 Aug 07 05:26:18 PM PDT 24 67374127 ps
T933 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3315309425 Aug 07 05:25:56 PM PDT 24 Aug 07 05:25:57 PM PDT 24 35700960 ps
T934 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2292265608 Aug 07 05:26:24 PM PDT 24 Aug 07 05:26:25 PM PDT 24 41342325 ps
T935 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1856251227 Aug 07 05:25:30 PM PDT 24 Aug 07 05:25:32 PM PDT 24 140048335 ps
T936 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4196103465 Aug 07 05:25:58 PM PDT 24 Aug 07 05:25:59 PM PDT 24 100553765 ps
T937 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3029313092 Aug 07 05:26:18 PM PDT 24 Aug 07 05:26:19 PM PDT 24 30082797 ps
T938 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2070501409 Aug 07 05:26:15 PM PDT 24 Aug 07 05:26:16 PM PDT 24 91257199 ps
T939 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2138387130 Aug 07 05:25:21 PM PDT 24 Aug 07 05:25:23 PM PDT 24 244295328 ps
T940 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2155239560 Aug 07 05:25:58 PM PDT 24 Aug 07 05:25:59 PM PDT 24 32029714 ps
T941 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.916085327 Aug 07 05:25:21 PM PDT 24 Aug 07 05:25:22 PM PDT 24 267202392 ps
T942 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.851035218 Aug 07 05:25:55 PM PDT 24 Aug 07 05:25:57 PM PDT 24 174076782 ps
T943 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1876362035 Aug 07 05:25:58 PM PDT 24 Aug 07 05:25:59 PM PDT 24 168596714 ps
T944 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2674251667 Aug 07 05:25:26 PM PDT 24 Aug 07 05:25:27 PM PDT 24 198271345 ps
T945 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1956846068 Aug 07 05:25:53 PM PDT 24 Aug 07 05:25:54 PM PDT 24 78037751 ps
T946 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.908045050 Aug 07 05:25:57 PM PDT 24 Aug 07 05:25:58 PM PDT 24 30633207 ps
T947 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2597614925 Aug 07 05:26:24 PM PDT 24 Aug 07 05:26:25 PM PDT 24 134968863 ps
T948 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.679905073 Aug 07 05:25:29 PM PDT 24 Aug 07 05:25:30 PM PDT 24 196440645 ps
T949 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2761770610 Aug 07 05:25:29 PM PDT 24 Aug 07 05:25:31 PM PDT 24 381429341 ps

Test location /workspace/coverage/default/4.gpio_full_random.2381705254
Short name T11
Test name
Test status
Simulation time 276388281 ps
CPU time 0.92 seconds
Started Aug 07 05:26:58 PM PDT 24
Finished Aug 07 05:26:59 PM PDT 24
Peak memory 198240 kb
Host smart-4e3f6f96-2572-47e8-a3e2-039c91d807ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381705254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2381705254
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2355645115
Short name T28
Test name
Test status
Simulation time 77192257 ps
CPU time 3.04 seconds
Started Aug 07 05:28:19 PM PDT 24
Finished Aug 07 05:28:22 PM PDT 24
Peak memory 198620 kb
Host smart-a198234c-1263-4f36-ad6c-a49baf516450
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355645115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2355645115
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.1415242283
Short name T13
Test name
Test status
Simulation time 125236807908 ps
CPU time 1252.49 seconds
Started Aug 07 05:28:48 PM PDT 24
Finished Aug 07 05:49:40 PM PDT 24
Peak memory 198904 kb
Host smart-7af455e0-ef13-43a9-a40b-19adc156cfa0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1415242283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.1415242283
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2843367715
Short name T38
Test name
Test status
Simulation time 126593697 ps
CPU time 0.8 seconds
Started Aug 07 05:26:31 PM PDT 24
Finished Aug 07 05:26:32 PM PDT 24
Peak memory 214324 kb
Host smart-d1ea9e8f-dbf7-4769-bea9-b8cae8a0037f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843367715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2843367715
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3800124085
Short name T69
Test name
Test status
Simulation time 62354711 ps
CPU time 0.62 seconds
Started Aug 07 05:12:37 PM PDT 24
Finished Aug 07 05:12:37 PM PDT 24
Peak memory 195848 kb
Host smart-f79f5242-0655-43ba-b92d-d780bc03cc08
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800124085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3800124085
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/default/10.gpio_stress_all.768161758
Short name T2
Test name
Test status
Simulation time 30964369776 ps
CPU time 86.61 seconds
Started Aug 07 05:27:37 PM PDT 24
Finished Aug 07 05:29:03 PM PDT 24
Peak memory 198692 kb
Host smart-fe48e29f-70f6-4a28-a0be-f4eb4033b332
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768161758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.768161758
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1707127139
Short name T41
Test name
Test status
Simulation time 246119031 ps
CPU time 1.17 seconds
Started Aug 07 05:12:33 PM PDT 24
Finished Aug 07 05:12:35 PM PDT 24
Peak memory 198696 kb
Host smart-325306a5-a25b-4cd1-aae3-3f2c000ef772
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707127139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1707127139
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/20.gpio_alert_test.3417830247
Short name T170
Test name
Test status
Simulation time 26331742 ps
CPU time 0.58 seconds
Started Aug 07 05:28:17 PM PDT 24
Finished Aug 07 05:28:17 PM PDT 24
Peak memory 194588 kb
Host smart-5abdbb27-011c-4c8d-9ef5-f10d64550c67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417830247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.3417830247
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1602976854
Short name T82
Test name
Test status
Simulation time 18883730 ps
CPU time 0.69 seconds
Started Aug 07 05:12:17 PM PDT 24
Finished Aug 07 05:12:18 PM PDT 24
Peak memory 196524 kb
Host smart-7c4b7ee2-0e8e-46bd-8054-85b8844764aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602976854 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1602976854
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2926104689
Short name T96
Test name
Test status
Simulation time 134500385 ps
CPU time 1.38 seconds
Started Aug 07 05:12:10 PM PDT 24
Finished Aug 07 05:12:11 PM PDT 24
Peak memory 198628 kb
Host smart-a0c4880f-f0d7-48f0-8faf-88dbb3f40a97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926104689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2926104689
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.4095469673
Short name T787
Test name
Test status
Simulation time 45981994 ps
CPU time 0.64 seconds
Started Aug 07 05:11:29 PM PDT 24
Finished Aug 07 05:11:29 PM PDT 24
Peak memory 195700 kb
Host smart-f2280859-a765-4d40-a0b1-7f570210e4c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095469673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.4095469673
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1740974462
Short name T775
Test name
Test status
Simulation time 64671217 ps
CPU time 1.36 seconds
Started Aug 07 05:11:31 PM PDT 24
Finished Aug 07 05:11:32 PM PDT 24
Peak memory 197344 kb
Host smart-60bfa29a-c7cb-4281-a2f3-ca8e9878f50b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740974462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1740974462
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2628859465
Short name T79
Test name
Test status
Simulation time 62333889 ps
CPU time 0.67 seconds
Started Aug 07 05:11:31 PM PDT 24
Finished Aug 07 05:11:32 PM PDT 24
Peak memory 195728 kb
Host smart-53300999-4364-41ae-9130-14d3db35ba45
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628859465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2628859465
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.965711011
Short name T805
Test name
Test status
Simulation time 34487466 ps
CPU time 0.88 seconds
Started Aug 07 05:11:27 PM PDT 24
Finished Aug 07 05:11:28 PM PDT 24
Peak memory 198656 kb
Host smart-759fc1ef-7b14-4d5c-9c2e-b0ad3b0011a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965711011 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.965711011
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1602918178
Short name T841
Test name
Test status
Simulation time 19865725 ps
CPU time 0.57 seconds
Started Aug 07 05:11:27 PM PDT 24
Finished Aug 07 05:11:27 PM PDT 24
Peak memory 194036 kb
Host smart-81e8961d-b063-46fe-91f0-002007af6640
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602918178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1602918178
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.985553894
Short name T726
Test name
Test status
Simulation time 33225025 ps
CPU time 0.6 seconds
Started Aug 07 05:11:27 PM PDT 24
Finished Aug 07 05:11:28 PM PDT 24
Peak memory 195028 kb
Host smart-efe91335-88ce-4cf9-8971-d653a3fd0352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985553894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.985553894
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.37240403
Short name T85
Test name
Test status
Simulation time 20721320 ps
CPU time 0.68 seconds
Started Aug 07 05:11:26 PM PDT 24
Finished Aug 07 05:11:27 PM PDT 24
Peak memory 195560 kb
Host smart-486194f7-833b-48f0-9c16-a0909e527af0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37240403 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.gpio_same_csr_outstanding.37240403
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.636471277
Short name T817
Test name
Test status
Simulation time 122736179 ps
CPU time 2.75 seconds
Started Aug 07 05:11:29 PM PDT 24
Finished Aug 07 05:11:32 PM PDT 24
Peak memory 198788 kb
Host smart-17a687ee-f82c-4c40-95ab-fa328049bb8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636471277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.636471277
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1561409352
Short name T95
Test name
Test status
Simulation time 119516048 ps
CPU time 1.15 seconds
Started Aug 07 05:11:29 PM PDT 24
Finished Aug 07 05:11:31 PM PDT 24
Peak memory 198744 kb
Host smart-6276ef5c-4bfc-4109-914e-eadee83aa0e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561409352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1561409352
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3339758498
Short name T81
Test name
Test status
Simulation time 26206825 ps
CPU time 0.76 seconds
Started Aug 07 05:11:40 PM PDT 24
Finished Aug 07 05:11:41 PM PDT 24
Peak memory 196924 kb
Host smart-b9e0a7ba-332b-43c1-a6a0-80f7569942cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339758498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3339758498
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3266465736
Short name T849
Test name
Test status
Simulation time 73604947 ps
CPU time 2.23 seconds
Started Aug 07 05:11:37 PM PDT 24
Finished Aug 07 05:11:40 PM PDT 24
Peak memory 197948 kb
Host smart-06ce2940-1aca-4ea7-a5f5-22c1e6fcbb27
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266465736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.3266465736
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2819437737
Short name T66
Test name
Test status
Simulation time 15598224 ps
CPU time 0.6 seconds
Started Aug 07 05:11:36 PM PDT 24
Finished Aug 07 05:11:37 PM PDT 24
Peak memory 195132 kb
Host smart-40b36e24-5b19-46df-99e0-2e5476653131
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819437737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2819437737
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3163574312
Short name T797
Test name
Test status
Simulation time 24260270 ps
CPU time 0.8 seconds
Started Aug 07 05:11:40 PM PDT 24
Finished Aug 07 05:11:40 PM PDT 24
Peak memory 198636 kb
Host smart-4b99bbcf-87fc-4d63-bcba-898240a46fd9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163574312 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3163574312
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3352608190
Short name T76
Test name
Test status
Simulation time 42519716 ps
CPU time 0.61 seconds
Started Aug 07 05:11:32 PM PDT 24
Finished Aug 07 05:11:33 PM PDT 24
Peak memory 195556 kb
Host smart-bd4241bb-ec03-4512-a891-d44f0f1c7ad3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352608190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3352608190
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2394323234
Short name T774
Test name
Test status
Simulation time 49219454 ps
CPU time 0.58 seconds
Started Aug 07 05:11:36 PM PDT 24
Finished Aug 07 05:11:37 PM PDT 24
Peak memory 194532 kb
Host smart-c7f4a398-7ea7-4ab2-b16a-2e799aed3eba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394323234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2394323234
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2046184497
Short name T839
Test name
Test status
Simulation time 46360091 ps
CPU time 0.61 seconds
Started Aug 07 05:11:32 PM PDT 24
Finished Aug 07 05:11:32 PM PDT 24
Peak memory 195264 kb
Host smart-57671a7e-cd10-4c72-b7e6-1e27868dc9e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046184497 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2046184497
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3234178000
Short name T811
Test name
Test status
Simulation time 107977645 ps
CPU time 1.52 seconds
Started Aug 07 05:11:36 PM PDT 24
Finished Aug 07 05:11:38 PM PDT 24
Peak memory 198816 kb
Host smart-12c7a803-436a-478b-a3a9-af91cdf351be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234178000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3234178000
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3739719627
Short name T35
Test name
Test status
Simulation time 102018232 ps
CPU time 1.41 seconds
Started Aug 07 05:11:36 PM PDT 24
Finished Aug 07 05:11:38 PM PDT 24
Peak memory 198732 kb
Host smart-99e648ef-e891-4ec9-9677-eb167b3ef0a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739719627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3739719627
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3961325386
Short name T748
Test name
Test status
Simulation time 32235645 ps
CPU time 0.85 seconds
Started Aug 07 05:12:16 PM PDT 24
Finished Aug 07 05:12:18 PM PDT 24
Peak memory 198620 kb
Host smart-70fe3567-b094-4b58-a029-37cc8acccc29
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961325386 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3961325386
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3613642224
Short name T823
Test name
Test status
Simulation time 14186099 ps
CPU time 0.6 seconds
Started Aug 07 05:12:10 PM PDT 24
Finished Aug 07 05:12:11 PM PDT 24
Peak memory 195892 kb
Host smart-3f46e86a-335d-46b1-8cf2-b75343ad96ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613642224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3613642224
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.90683755
Short name T738
Test name
Test status
Simulation time 49924859 ps
CPU time 0.6 seconds
Started Aug 07 05:12:16 PM PDT 24
Finished Aug 07 05:12:17 PM PDT 24
Peak memory 194516 kb
Host smart-6a91b51b-d601-4476-bc2f-ab9fedb61383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90683755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.90683755
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1407288322
Short name T832
Test name
Test status
Simulation time 124911742 ps
CPU time 1.55 seconds
Started Aug 07 05:12:15 PM PDT 24
Finished Aug 07 05:12:17 PM PDT 24
Peak memory 198796 kb
Host smart-1d73e460-cccd-4a66-bd7f-f61ced66cca6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407288322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1407288322
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.133260248
Short name T809
Test name
Test status
Simulation time 79476558 ps
CPU time 0.87 seconds
Started Aug 07 05:12:19 PM PDT 24
Finished Aug 07 05:12:20 PM PDT 24
Peak memory 197920 kb
Host smart-54b94141-c877-4228-a669-a727a84cdfab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133260248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.133260248
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3653685849
Short name T777
Test name
Test status
Simulation time 49209866 ps
CPU time 0.8 seconds
Started Aug 07 05:12:16 PM PDT 24
Finished Aug 07 05:12:17 PM PDT 24
Peak memory 198600 kb
Host smart-5c29a8ba-7e5a-4b01-bef8-482cf1f25d67
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653685849 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3653685849
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.307265667
Short name T838
Test name
Test status
Simulation time 39011576 ps
CPU time 0.63 seconds
Started Aug 07 05:12:17 PM PDT 24
Finished Aug 07 05:12:18 PM PDT 24
Peak memory 195696 kb
Host smart-25bcd6ce-cb79-45b5-bc01-30fdaf8f3b98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307265667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.307265667
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2120685418
Short name T804
Test name
Test status
Simulation time 13370905 ps
CPU time 0.63 seconds
Started Aug 07 05:12:18 PM PDT 24
Finished Aug 07 05:12:19 PM PDT 24
Peak memory 195196 kb
Host smart-f3818a4a-9cf5-4257-a13d-edb0921c4c60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120685418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2120685418
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3956497119
Short name T813
Test name
Test status
Simulation time 29367303 ps
CPU time 0.71 seconds
Started Aug 07 05:12:16 PM PDT 24
Finished Aug 07 05:12:17 PM PDT 24
Peak memory 195752 kb
Host smart-6955ed48-610c-49e5-aa77-9bff203376d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956497119 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3956497119
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3857482311
Short name T747
Test name
Test status
Simulation time 449467885 ps
CPU time 2.36 seconds
Started Aug 07 05:12:15 PM PDT 24
Finished Aug 07 05:12:18 PM PDT 24
Peak memory 198692 kb
Host smart-1561a182-1646-4fab-b26c-a8bbf4f7ea94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857482311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3857482311
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.4251504913
Short name T821
Test name
Test status
Simulation time 132015785 ps
CPU time 0.97 seconds
Started Aug 07 05:12:17 PM PDT 24
Finished Aug 07 05:12:18 PM PDT 24
Peak memory 197852 kb
Host smart-d670b376-5999-423a-9bb3-8ae10eb45e49
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251504913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.4251504913
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3151630762
Short name T831
Test name
Test status
Simulation time 53431522 ps
CPU time 0.77 seconds
Started Aug 07 05:12:15 PM PDT 24
Finished Aug 07 05:12:16 PM PDT 24
Peak memory 198672 kb
Host smart-74fbea6c-5a82-4fd1-8b60-54bf2350c89f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151630762 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3151630762
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2270204220
Short name T75
Test name
Test status
Simulation time 61449964 ps
CPU time 0.6 seconds
Started Aug 07 05:12:17 PM PDT 24
Finished Aug 07 05:12:17 PM PDT 24
Peak memory 195180 kb
Host smart-8dbf9bfe-95ff-411a-9130-a976183214b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270204220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2270204220
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3106737569
Short name T785
Test name
Test status
Simulation time 12482090 ps
CPU time 0.64 seconds
Started Aug 07 05:12:21 PM PDT 24
Finished Aug 07 05:12:22 PM PDT 24
Peak memory 194504 kb
Host smart-d89994c1-de7a-48f4-a3d7-69cbfef3aea4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106737569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3106737569
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3296172970
Short name T782
Test name
Test status
Simulation time 51255834 ps
CPU time 0.74 seconds
Started Aug 07 05:12:16 PM PDT 24
Finished Aug 07 05:12:17 PM PDT 24
Peak memory 197104 kb
Host smart-9c7c2cee-8d72-41cf-abd9-c0a3b32ca5be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296172970 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3296172970
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3905389257
Short name T739
Test name
Test status
Simulation time 48820932 ps
CPU time 1.46 seconds
Started Aug 07 05:12:22 PM PDT 24
Finished Aug 07 05:12:23 PM PDT 24
Peak memory 198772 kb
Host smart-e4955acc-7b98-4ea1-aed9-d10a165a2708
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905389257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3905389257
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3213099244
Short name T42
Test name
Test status
Simulation time 244262687 ps
CPU time 1.39 seconds
Started Aug 07 05:12:21 PM PDT 24
Finished Aug 07 05:12:22 PM PDT 24
Peak memory 198716 kb
Host smart-06036ba1-ac02-4121-9f05-273eb9815a23
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213099244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3213099244
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.895727301
Short name T744
Test name
Test status
Simulation time 69335602 ps
CPU time 1.21 seconds
Started Aug 07 05:12:29 PM PDT 24
Finished Aug 07 05:12:31 PM PDT 24
Peak memory 198704 kb
Host smart-21f67f1d-7509-40bd-9444-c1f2f4c7d8a6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895727301 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.895727301
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3330578678
Short name T796
Test name
Test status
Simulation time 23933741 ps
CPU time 0.63 seconds
Started Aug 07 05:12:23 PM PDT 24
Finished Aug 07 05:12:24 PM PDT 24
Peak memory 196100 kb
Host smart-7e9ba5b9-da43-4f1c-821b-0e4e15fb62ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330578678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3330578678
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1306242533
Short name T763
Test name
Test status
Simulation time 13710923 ps
CPU time 0.58 seconds
Started Aug 07 05:12:24 PM PDT 24
Finished Aug 07 05:12:24 PM PDT 24
Peak memory 194504 kb
Host smart-3fd039e8-40c1-436f-9896-f8968247dc4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306242533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1306242533
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.868659367
Short name T833
Test name
Test status
Simulation time 55042308 ps
CPU time 0.72 seconds
Started Aug 07 05:12:29 PM PDT 24
Finished Aug 07 05:12:30 PM PDT 24
Peak memory 196664 kb
Host smart-8e3aa217-1e79-4c71-8e64-7e47a45c909f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868659367 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.868659367
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.412990730
Short name T766
Test name
Test status
Simulation time 481559376 ps
CPU time 2.61 seconds
Started Aug 07 05:12:25 PM PDT 24
Finished Aug 07 05:12:28 PM PDT 24
Peak memory 198736 kb
Host smart-61dc4770-8484-4272-9bd7-f50cb8cd3efa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412990730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.412990730
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.117764314
Short name T794
Test name
Test status
Simulation time 135687802 ps
CPU time 1.01 seconds
Started Aug 07 05:12:23 PM PDT 24
Finished Aug 07 05:12:24 PM PDT 24
Peak memory 198588 kb
Host smart-12873e07-45a9-4141-84a9-2f47c9018ac5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117764314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.117764314
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3664167896
Short name T745
Test name
Test status
Simulation time 107521250 ps
CPU time 0.79 seconds
Started Aug 07 05:12:23 PM PDT 24
Finished Aug 07 05:12:24 PM PDT 24
Peak memory 198632 kb
Host smart-48d5bd46-cec0-4994-8f8d-379deaf0fa6c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664167896 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3664167896
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2044088116
Short name T751
Test name
Test status
Simulation time 25401546 ps
CPU time 0.61 seconds
Started Aug 07 05:12:27 PM PDT 24
Finished Aug 07 05:12:28 PM PDT 24
Peak memory 195256 kb
Host smart-4bbb501a-ab4e-4b71-a1ad-b05a9818f45c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044088116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2044088116
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1220119057
Short name T730
Test name
Test status
Simulation time 14369880 ps
CPU time 0.61 seconds
Started Aug 07 05:12:28 PM PDT 24
Finished Aug 07 05:12:29 PM PDT 24
Peak memory 194364 kb
Host smart-c899acc2-8620-47a5-b327-d9178bad01a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220119057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1220119057
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.4092280315
Short name T87
Test name
Test status
Simulation time 20359416 ps
CPU time 0.61 seconds
Started Aug 07 05:12:25 PM PDT 24
Finished Aug 07 05:12:26 PM PDT 24
Peak memory 195712 kb
Host smart-de96e3e0-a857-40a1-a35b-9f83c4f93f4b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092280315 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.4092280315
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3241454206
Short name T784
Test name
Test status
Simulation time 86494831 ps
CPU time 1.57 seconds
Started Aug 07 05:12:23 PM PDT 24
Finished Aug 07 05:12:24 PM PDT 24
Peak memory 198812 kb
Host smart-66ce773f-f34b-473d-b6fe-762268d02ae5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241454206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3241454206
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1984439240
Short name T97
Test name
Test status
Simulation time 127907596 ps
CPU time 0.86 seconds
Started Aug 07 05:12:21 PM PDT 24
Finished Aug 07 05:12:22 PM PDT 24
Peak memory 197584 kb
Host smart-f9e686b2-12d0-475a-90cc-db800f1cc04e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984439240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1984439240
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3554493608
Short name T735
Test name
Test status
Simulation time 19587762 ps
CPU time 0.7 seconds
Started Aug 07 05:12:27 PM PDT 24
Finished Aug 07 05:12:28 PM PDT 24
Peak memory 197852 kb
Host smart-f194b2f8-678c-4638-bb16-af00ea789f72
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554493608 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3554493608
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2608118793
Short name T753
Test name
Test status
Simulation time 17100398 ps
CPU time 0.66 seconds
Started Aug 07 05:12:37 PM PDT 24
Finished Aug 07 05:12:37 PM PDT 24
Peak memory 195608 kb
Host smart-257c9b0d-ad21-47ed-99df-b1a20b8daa41
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608118793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2608118793
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.1004424517
Short name T736
Test name
Test status
Simulation time 20259294 ps
CPU time 0.6 seconds
Started Aug 07 05:12:28 PM PDT 24
Finished Aug 07 05:12:29 PM PDT 24
Peak memory 194484 kb
Host smart-f231f13f-a9ec-4565-87a3-e60249743b95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004424517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1004424517
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.883985782
Short name T89
Test name
Test status
Simulation time 38926816 ps
CPU time 0.87 seconds
Started Aug 07 05:12:26 PM PDT 24
Finished Aug 07 05:12:27 PM PDT 24
Peak memory 197996 kb
Host smart-65c464cc-ddfb-4537-ae74-506c91342bd4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883985782 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.883985782
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.145022110
Short name T800
Test name
Test status
Simulation time 73911225 ps
CPU time 1.07 seconds
Started Aug 07 05:12:35 PM PDT 24
Finished Aug 07 05:12:36 PM PDT 24
Peak memory 198800 kb
Host smart-62479e13-4343-4178-9bf6-465a05824687
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145022110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.145022110
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3364976596
Short name T783
Test name
Test status
Simulation time 43694531 ps
CPU time 0.84 seconds
Started Aug 07 05:12:46 PM PDT 24
Finished Aug 07 05:12:47 PM PDT 24
Peak memory 197864 kb
Host smart-603bb9fa-85b4-41cd-904c-b5aae1107f3a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364976596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3364976596
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1164410763
Short name T734
Test name
Test status
Simulation time 28053280 ps
CPU time 0.87 seconds
Started Aug 07 05:12:29 PM PDT 24
Finished Aug 07 05:12:30 PM PDT 24
Peak memory 198640 kb
Host smart-254c672b-1a29-42d3-a997-1615f90eda1a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164410763 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1164410763
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.538536355
Short name T94
Test name
Test status
Simulation time 14881580 ps
CPU time 0.58 seconds
Started Aug 07 05:12:46 PM PDT 24
Finished Aug 07 05:12:46 PM PDT 24
Peak memory 195256 kb
Host smart-1e7687a1-8b44-42df-b1cf-519f165190f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538536355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.538536355
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3161402172
Short name T814
Test name
Test status
Simulation time 11310638 ps
CPU time 0.57 seconds
Started Aug 07 05:12:34 PM PDT 24
Finished Aug 07 05:12:35 PM PDT 24
Peak memory 195128 kb
Host smart-1a045e58-27d3-4af6-bda2-0b8f43608f5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161402172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3161402172
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1714099102
Short name T90
Test name
Test status
Simulation time 33966831 ps
CPU time 0.66 seconds
Started Aug 07 05:12:26 PM PDT 24
Finished Aug 07 05:12:27 PM PDT 24
Peak memory 195928 kb
Host smart-74ea9e8a-ee0e-441a-9a40-13e539d22ba2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714099102 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1714099102
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1868784034
Short name T752
Test name
Test status
Simulation time 133342321 ps
CPU time 2.39 seconds
Started Aug 07 05:12:37 PM PDT 24
Finished Aug 07 05:12:39 PM PDT 24
Peak memory 198800 kb
Host smart-86a2d361-4791-46f3-9fe9-2df9073a490b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868784034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1868784034
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2944438071
Short name T36
Test name
Test status
Simulation time 232729695 ps
CPU time 1.48 seconds
Started Aug 07 05:12:28 PM PDT 24
Finished Aug 07 05:12:29 PM PDT 24
Peak memory 198760 kb
Host smart-1dc5ff94-4cc1-4eb0-8b68-5fb880aaff1f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944438071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2944438071
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3474422727
Short name T810
Test name
Test status
Simulation time 104558205 ps
CPU time 0.98 seconds
Started Aug 07 05:12:27 PM PDT 24
Finished Aug 07 05:12:28 PM PDT 24
Peak memory 198596 kb
Host smart-76ae7961-26a7-4281-b496-b8cc417f9911
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474422727 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3474422727
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1772312280
Short name T749
Test name
Test status
Simulation time 25100527 ps
CPU time 0.61 seconds
Started Aug 07 05:12:28 PM PDT 24
Finished Aug 07 05:12:28 PM PDT 24
Peak memory 194544 kb
Host smart-f4b0dcb7-d8d3-481c-9a87-419ee31ce43b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772312280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1772312280
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.731646106
Short name T844
Test name
Test status
Simulation time 18702462 ps
CPU time 0.76 seconds
Started Aug 07 05:12:28 PM PDT 24
Finished Aug 07 05:12:29 PM PDT 24
Peak memory 196740 kb
Host smart-bcd1e92a-7376-47a6-9cf0-da70ca5f2506
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731646106 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.731646106
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.373828006
Short name T732
Test name
Test status
Simulation time 89066640 ps
CPU time 1.15 seconds
Started Aug 07 05:12:26 PM PDT 24
Finished Aug 07 05:12:27 PM PDT 24
Peak memory 198848 kb
Host smart-86bcde15-6b1b-44e4-8a94-fb8aa9d9bf40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373828006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.373828006
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1120184457
Short name T44
Test name
Test status
Simulation time 419860540 ps
CPU time 1.5 seconds
Started Aug 07 05:12:26 PM PDT 24
Finished Aug 07 05:12:28 PM PDT 24
Peak memory 198668 kb
Host smart-eea0b7f9-56ce-43af-8ee4-7779080d9667
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120184457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1120184457
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.424481242
Short name T764
Test name
Test status
Simulation time 137909367 ps
CPU time 0.93 seconds
Started Aug 07 05:12:32 PM PDT 24
Finished Aug 07 05:12:33 PM PDT 24
Peak memory 198604 kb
Host smart-8f751d5d-ccf8-486e-948c-d5dad1ff3033
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424481242 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.424481242
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2728235867
Short name T757
Test name
Test status
Simulation time 36126977 ps
CPU time 0.62 seconds
Started Aug 07 05:12:47 PM PDT 24
Finished Aug 07 05:12:47 PM PDT 24
Peak memory 195608 kb
Host smart-6c6ee172-d45e-4710-acc1-411b2db15dbe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728235867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2728235867
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2585527181
Short name T835
Test name
Test status
Simulation time 45367417 ps
CPU time 0.57 seconds
Started Aug 07 05:12:32 PM PDT 24
Finished Aug 07 05:12:33 PM PDT 24
Peak memory 195088 kb
Host smart-58df7e3f-ad1d-4884-8558-1347801fd3b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585527181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2585527181
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2654086347
Short name T788
Test name
Test status
Simulation time 64660880 ps
CPU time 0.73 seconds
Started Aug 07 05:12:26 PM PDT 24
Finished Aug 07 05:12:27 PM PDT 24
Peak memory 196588 kb
Host smart-0cd20bd1-f16a-4b3d-a550-9ffe56ea9bac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654086347 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2654086347
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.4096188486
Short name T799
Test name
Test status
Simulation time 38583218 ps
CPU time 1.77 seconds
Started Aug 07 05:12:37 PM PDT 24
Finished Aug 07 05:12:39 PM PDT 24
Peak memory 198800 kb
Host smart-00fbd7a3-542e-4a19-97c9-ec8ef0df3085
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096188486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.4096188486
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3675196329
Short name T842
Test name
Test status
Simulation time 22604323 ps
CPU time 0.83 seconds
Started Aug 07 05:12:33 PM PDT 24
Finished Aug 07 05:12:34 PM PDT 24
Peak memory 198632 kb
Host smart-3a7d9131-1768-4137-9e04-7cdd5885cdc0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675196329 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3675196329
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4003122817
Short name T64
Test name
Test status
Simulation time 64322298 ps
CPU time 0.6 seconds
Started Aug 07 05:12:34 PM PDT 24
Finished Aug 07 05:12:34 PM PDT 24
Peak memory 195512 kb
Host smart-e60a5c37-0fc0-48bf-b1b3-af08c2ed447c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003122817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.4003122817
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3848275675
Short name T772
Test name
Test status
Simulation time 10905469 ps
CPU time 0.6 seconds
Started Aug 07 05:12:45 PM PDT 24
Finished Aug 07 05:12:45 PM PDT 24
Peak memory 194536 kb
Host smart-06cdf9ed-5972-4475-9c7c-d2c44aeb0e90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848275675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3848275675
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1978110286
Short name T88
Test name
Test status
Simulation time 103140485 ps
CPU time 0.75 seconds
Started Aug 07 05:12:33 PM PDT 24
Finished Aug 07 05:12:34 PM PDT 24
Peak memory 197404 kb
Host smart-901c145b-aca6-44f2-8e73-2415bfa66129
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978110286 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1978110286
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.388427545
Short name T830
Test name
Test status
Simulation time 225942903 ps
CPU time 2.05 seconds
Started Aug 07 05:12:32 PM PDT 24
Finished Aug 07 05:12:35 PM PDT 24
Peak memory 198828 kb
Host smart-cf09012b-3577-4109-a2bc-3f86a4f5dc5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388427545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.388427545
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2562491575
Short name T827
Test name
Test status
Simulation time 46351887 ps
CPU time 0.87 seconds
Started Aug 07 05:12:33 PM PDT 24
Finished Aug 07 05:12:34 PM PDT 24
Peak memory 197836 kb
Host smart-e5ba45c9-cd25-449f-a8ac-fa95e3467159
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562491575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2562491575
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1591255522
Short name T72
Test name
Test status
Simulation time 52696178 ps
CPU time 0.66 seconds
Started Aug 07 05:11:41 PM PDT 24
Finished Aug 07 05:11:42 PM PDT 24
Peak memory 195976 kb
Host smart-790c8f1e-b0cb-4511-8439-9e7976c12830
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591255522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1591255522
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2292623356
Short name T71
Test name
Test status
Simulation time 318258700 ps
CPU time 3.15 seconds
Started Aug 07 05:11:48 PM PDT 24
Finished Aug 07 05:11:52 PM PDT 24
Peak memory 198764 kb
Host smart-8d0c1e16-2de3-4e89-bc23-e51958fa1246
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292623356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2292623356
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.231420418
Short name T67
Test name
Test status
Simulation time 74019748 ps
CPU time 0.67 seconds
Started Aug 07 05:11:42 PM PDT 24
Finished Aug 07 05:11:43 PM PDT 24
Peak memory 196228 kb
Host smart-0dcb9aeb-c08c-42ac-995e-2b22982063e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231420418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.231420418
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1983191404
Short name T825
Test name
Test status
Simulation time 39725102 ps
CPU time 0.96 seconds
Started Aug 07 05:11:42 PM PDT 24
Finished Aug 07 05:11:43 PM PDT 24
Peak memory 198616 kb
Host smart-af7773b9-877e-4b3f-8d66-f53767317c95
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983191404 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1983191404
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1128102211
Short name T73
Test name
Test status
Simulation time 17847653 ps
CPU time 0.59 seconds
Started Aug 07 05:11:39 PM PDT 24
Finished Aug 07 05:11:40 PM PDT 24
Peak memory 195780 kb
Host smart-bd195d5b-6ea6-4d75-8c2c-b2ce19639d80
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128102211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1128102211
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.83099569
Short name T741
Test name
Test status
Simulation time 14757197 ps
CPU time 0.59 seconds
Started Aug 07 05:11:44 PM PDT 24
Finished Aug 07 05:11:44 PM PDT 24
Peak memory 194524 kb
Host smart-d0c7b658-46d4-442c-b463-b6e5152bcb21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83099569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.83099569
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1978778500
Short name T86
Test name
Test status
Simulation time 26839728 ps
CPU time 0.75 seconds
Started Aug 07 05:11:42 PM PDT 24
Finished Aug 07 05:11:43 PM PDT 24
Peak memory 197520 kb
Host smart-1f01e1f4-eb0e-4a9c-b865-a502f6d64f79
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978778500 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1978778500
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.417167319
Short name T740
Test name
Test status
Simulation time 38743083 ps
CPU time 1.87 seconds
Started Aug 07 05:11:42 PM PDT 24
Finished Aug 07 05:11:44 PM PDT 24
Peak memory 198772 kb
Host smart-d88dce05-a721-4e62-b902-1845065597e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417167319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.417167319
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1803927879
Short name T765
Test name
Test status
Simulation time 853626406 ps
CPU time 1.31 seconds
Started Aug 07 05:11:43 PM PDT 24
Finished Aug 07 05:11:45 PM PDT 24
Peak memory 198760 kb
Host smart-2d575c3c-a473-4410-98d4-13cacdef9436
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803927879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1803927879
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1811610187
Short name T767
Test name
Test status
Simulation time 35192498 ps
CPU time 0.58 seconds
Started Aug 07 05:12:31 PM PDT 24
Finished Aug 07 05:12:32 PM PDT 24
Peak memory 194484 kb
Host smart-f64f5e0d-43d8-4616-aa23-7295ad8222a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811610187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1811610187
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.1904251086
Short name T798
Test name
Test status
Simulation time 12025372 ps
CPU time 0.59 seconds
Started Aug 07 05:12:46 PM PDT 24
Finished Aug 07 05:12:47 PM PDT 24
Peak memory 194464 kb
Host smart-e8a1219e-1108-4ea9-bfa1-e64f23bc13be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904251086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.1904251086
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3619374864
Short name T790
Test name
Test status
Simulation time 16362169 ps
CPU time 0.61 seconds
Started Aug 07 05:12:46 PM PDT 24
Finished Aug 07 05:12:46 PM PDT 24
Peak memory 194512 kb
Host smart-9db1d29c-ad67-413d-87a6-bf2c3ff1e928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619374864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3619374864
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3478364633
Short name T780
Test name
Test status
Simulation time 16389858 ps
CPU time 0.6 seconds
Started Aug 07 05:12:38 PM PDT 24
Finished Aug 07 05:12:39 PM PDT 24
Peak memory 194524 kb
Host smart-71a97287-04ba-4988-874b-4cc02c088721
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478364633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3478364633
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1103123851
Short name T762
Test name
Test status
Simulation time 20890355 ps
CPU time 0.59 seconds
Started Aug 07 05:12:41 PM PDT 24
Finished Aug 07 05:12:41 PM PDT 24
Peak memory 194368 kb
Host smart-d941c9e1-81db-471d-aeae-2340282e6102
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103123851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1103123851
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3204892103
Short name T840
Test name
Test status
Simulation time 25513058 ps
CPU time 0.59 seconds
Started Aug 07 05:12:39 PM PDT 24
Finished Aug 07 05:12:40 PM PDT 24
Peak memory 194360 kb
Host smart-a9cdb1a3-390f-4d2f-aa0d-ccdf035fa3ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204892103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3204892103
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.918753579
Short name T760
Test name
Test status
Simulation time 80045904 ps
CPU time 0.66 seconds
Started Aug 07 05:12:40 PM PDT 24
Finished Aug 07 05:12:40 PM PDT 24
Peak memory 194576 kb
Host smart-0f4de2b0-2fec-47f1-aafd-db282d985a2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918753579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.918753579
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.2441649473
Short name T769
Test name
Test status
Simulation time 13825774 ps
CPU time 0.58 seconds
Started Aug 07 05:12:40 PM PDT 24
Finished Aug 07 05:12:41 PM PDT 24
Peak memory 194508 kb
Host smart-fa302cf4-dd32-44be-9e83-397c36d1b095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441649473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.2441649473
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2939469783
Short name T756
Test name
Test status
Simulation time 49680410 ps
CPU time 0.58 seconds
Started Aug 07 05:12:38 PM PDT 24
Finished Aug 07 05:12:39 PM PDT 24
Peak memory 194460 kb
Host smart-1c6bf012-136f-45cb-b29d-529a734466b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939469783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2939469783
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3614654020
Short name T776
Test name
Test status
Simulation time 12155462 ps
CPU time 0.62 seconds
Started Aug 07 05:12:43 PM PDT 24
Finished Aug 07 05:12:43 PM PDT 24
Peak memory 194620 kb
Host smart-45410d07-3703-46a0-b44d-d20b7e9313a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614654020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3614654020
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.311813346
Short name T78
Test name
Test status
Simulation time 37853993 ps
CPU time 0.65 seconds
Started Aug 07 05:11:49 PM PDT 24
Finished Aug 07 05:11:49 PM PDT 24
Peak memory 195316 kb
Host smart-cedd91b8-46be-400a-b124-d6baeb1b49f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311813346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.311813346
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.748453286
Short name T733
Test name
Test status
Simulation time 132855906 ps
CPU time 1.51 seconds
Started Aug 07 05:11:47 PM PDT 24
Finished Aug 07 05:11:49 PM PDT 24
Peak memory 197020 kb
Host smart-fbe6cc62-a837-4374-be47-d7bdf0851edd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748453286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.748453286
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3795617969
Short name T808
Test name
Test status
Simulation time 33227444 ps
CPU time 0.59 seconds
Started Aug 07 05:11:48 PM PDT 24
Finished Aug 07 05:11:49 PM PDT 24
Peak memory 195052 kb
Host smart-0d4d4ec5-ac00-4d24-a9eb-66fe29847425
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795617969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3795617969
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2010897383
Short name T728
Test name
Test status
Simulation time 35624815 ps
CPU time 0.83 seconds
Started Aug 07 05:11:48 PM PDT 24
Finished Aug 07 05:11:49 PM PDT 24
Peak memory 198524 kb
Host smart-98211c47-edf1-45ea-99fe-df67b044b537
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010897383 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2010897383
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1746732504
Short name T65
Test name
Test status
Simulation time 37340345 ps
CPU time 0.62 seconds
Started Aug 07 05:11:49 PM PDT 24
Finished Aug 07 05:11:49 PM PDT 24
Peak memory 196372 kb
Host smart-af303ed4-0687-466e-a350-3a464a2a9c6b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746732504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1746732504
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3307604076
Short name T820
Test name
Test status
Simulation time 25585242 ps
CPU time 0.62 seconds
Started Aug 07 05:11:47 PM PDT 24
Finished Aug 07 05:11:48 PM PDT 24
Peak memory 195272 kb
Host smart-02e67bab-87b6-47e9-98ca-dd24e8d41cb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307604076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3307604076
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.813518066
Short name T822
Test name
Test status
Simulation time 27961040 ps
CPU time 0.73 seconds
Started Aug 07 05:11:48 PM PDT 24
Finished Aug 07 05:11:49 PM PDT 24
Peak memory 196860 kb
Host smart-bdff1174-14d1-429e-8f0b-a65467113032
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813518066 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.813518066
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3042706175
Short name T834
Test name
Test status
Simulation time 27520844 ps
CPU time 1.39 seconds
Started Aug 07 05:11:48 PM PDT 24
Finished Aug 07 05:11:49 PM PDT 24
Peak memory 198760 kb
Host smart-bbb15e6a-54d9-47c5-9d6d-b1985626c7fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042706175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3042706175
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2587055905
Short name T829
Test name
Test status
Simulation time 559632151 ps
CPU time 1.36 seconds
Started Aug 07 05:11:47 PM PDT 24
Finished Aug 07 05:11:49 PM PDT 24
Peak memory 198644 kb
Host smart-00762ad7-cea6-4577-b5fd-1fa81eb5d4c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587055905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2587055905
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1173242531
Short name T815
Test name
Test status
Simulation time 54249123 ps
CPU time 0.6 seconds
Started Aug 07 05:12:44 PM PDT 24
Finished Aug 07 05:12:44 PM PDT 24
Peak memory 194512 kb
Host smart-a288a374-e083-4f5a-a7e7-1b5df313f9e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173242531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1173242531
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2850535868
Short name T773
Test name
Test status
Simulation time 13987527 ps
CPU time 0.58 seconds
Started Aug 07 05:12:49 PM PDT 24
Finished Aug 07 05:12:49 PM PDT 24
Peak memory 194472 kb
Host smart-74b73ec9-0871-494e-98d5-b6e81be89422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850535868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2850535868
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.4288834287
Short name T803
Test name
Test status
Simulation time 39043350 ps
CPU time 0.59 seconds
Started Aug 07 05:12:50 PM PDT 24
Finished Aug 07 05:12:50 PM PDT 24
Peak memory 195100 kb
Host smart-d592be65-95ef-41f4-8b8e-549590e16b2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288834287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.4288834287
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2554183402
Short name T818
Test name
Test status
Simulation time 49653882 ps
CPU time 0.6 seconds
Started Aug 07 05:12:42 PM PDT 24
Finished Aug 07 05:12:43 PM PDT 24
Peak memory 195120 kb
Host smart-4073b7fb-5438-4837-845b-a920b3780af2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554183402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2554183402
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.145718344
Short name T836
Test name
Test status
Simulation time 16006085 ps
CPU time 0.64 seconds
Started Aug 07 05:12:44 PM PDT 24
Finished Aug 07 05:12:44 PM PDT 24
Peak memory 194580 kb
Host smart-04aeebb1-ff2f-402b-96ea-e497e52f0bfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145718344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.145718344
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1315750951
Short name T737
Test name
Test status
Simulation time 148928769 ps
CPU time 0.6 seconds
Started Aug 07 05:12:43 PM PDT 24
Finished Aug 07 05:12:44 PM PDT 24
Peak memory 195020 kb
Host smart-90d30f8b-8552-4fc6-8f71-e54543815d0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315750951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1315750951
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.384840691
Short name T725
Test name
Test status
Simulation time 158430019 ps
CPU time 0.59 seconds
Started Aug 07 05:12:44 PM PDT 24
Finished Aug 07 05:12:45 PM PDT 24
Peak memory 195124 kb
Host smart-9d3e3ea5-a542-466c-8a49-1c87ea9a07f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384840691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.384840691
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3667407656
Short name T779
Test name
Test status
Simulation time 19928185 ps
CPU time 0.59 seconds
Started Aug 07 05:12:42 PM PDT 24
Finished Aug 07 05:12:43 PM PDT 24
Peak memory 194588 kb
Host smart-0a1dfa8b-f3d3-4781-844a-807b4b1a4ea0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667407656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3667407656
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3529301713
Short name T807
Test name
Test status
Simulation time 15835015 ps
CPU time 0.61 seconds
Started Aug 07 05:12:45 PM PDT 24
Finished Aug 07 05:12:46 PM PDT 24
Peak memory 194512 kb
Host smart-a3ed0d3d-c6d9-4f60-9ce1-20e3df6c943f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529301713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3529301713
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1857687178
Short name T812
Test name
Test status
Simulation time 18965600 ps
CPU time 0.62 seconds
Started Aug 07 05:12:43 PM PDT 24
Finished Aug 07 05:12:44 PM PDT 24
Peak memory 195140 kb
Host smart-a8de99e7-123e-48a9-9c15-9894791242cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857687178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1857687178
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2923486144
Short name T778
Test name
Test status
Simulation time 47810402 ps
CPU time 0.65 seconds
Started Aug 07 05:11:47 PM PDT 24
Finished Aug 07 05:11:47 PM PDT 24
Peak memory 195128 kb
Host smart-e5f32f1e-e3ea-48d6-8681-96982e4cafff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923486144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2923486144
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1353898282
Short name T77
Test name
Test status
Simulation time 94070713 ps
CPU time 1.5 seconds
Started Aug 07 05:11:53 PM PDT 24
Finished Aug 07 05:11:55 PM PDT 24
Peak memory 197532 kb
Host smart-2a090a77-bb39-491e-9367-725350c7f071
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353898282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1353898282
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2739313883
Short name T74
Test name
Test status
Simulation time 17272900 ps
CPU time 0.66 seconds
Started Aug 07 05:11:55 PM PDT 24
Finished Aug 07 05:11:56 PM PDT 24
Peak memory 195404 kb
Host smart-6afa30ce-51cc-459d-a24d-d34f199d3e47
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739313883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2739313883
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.229270237
Short name T746
Test name
Test status
Simulation time 80265039 ps
CPU time 1.25 seconds
Started Aug 07 05:11:48 PM PDT 24
Finished Aug 07 05:11:49 PM PDT 24
Peak memory 198796 kb
Host smart-943bbd5b-5271-4141-ba41-f28712b7a38e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229270237 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.229270237
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3386799963
Short name T802
Test name
Test status
Simulation time 53707729 ps
CPU time 0.63 seconds
Started Aug 07 05:11:48 PM PDT 24
Finished Aug 07 05:11:49 PM PDT 24
Peak memory 195572 kb
Host smart-02514f1b-4cdf-4905-ae2e-786dc1e453cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386799963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.3386799963
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.3059606734
Short name T724
Test name
Test status
Simulation time 52129512 ps
CPU time 0.59 seconds
Started Aug 07 05:11:53 PM PDT 24
Finished Aug 07 05:11:53 PM PDT 24
Peak memory 194432 kb
Host smart-29298a34-1d20-415f-8be7-12fb5b7c3d24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059606734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3059606734
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1870850770
Short name T70
Test name
Test status
Simulation time 19885099 ps
CPU time 0.64 seconds
Started Aug 07 05:11:47 PM PDT 24
Finished Aug 07 05:11:48 PM PDT 24
Peak memory 195612 kb
Host smart-7f0a1d4e-1333-4b59-be0b-09a41a64ca97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870850770 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1870850770
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3366901475
Short name T848
Test name
Test status
Simulation time 45229897 ps
CPU time 2.26 seconds
Started Aug 07 05:11:48 PM PDT 24
Finished Aug 07 05:11:50 PM PDT 24
Peak memory 198796 kb
Host smart-e2ef7eb7-ff77-4f2d-b7db-c91221875eaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366901475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3366901475
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.355136686
Short name T743
Test name
Test status
Simulation time 85374063 ps
CPU time 1.17 seconds
Started Aug 07 05:11:50 PM PDT 24
Finished Aug 07 05:11:52 PM PDT 24
Peak memory 198228 kb
Host smart-b7bd0556-2d67-44bb-b7b7-aca1122e1aa9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355136686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.355136686
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2612510364
Short name T828
Test name
Test status
Simulation time 22193363 ps
CPU time 0.58 seconds
Started Aug 07 05:12:47 PM PDT 24
Finished Aug 07 05:12:47 PM PDT 24
Peak memory 194516 kb
Host smart-3b167d76-7159-4212-992b-a6b8aefd7c7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612510364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2612510364
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1721066325
Short name T731
Test name
Test status
Simulation time 32111085 ps
CPU time 0.59 seconds
Started Aug 07 05:12:43 PM PDT 24
Finished Aug 07 05:12:44 PM PDT 24
Peak memory 194528 kb
Host smart-d9fd4612-868b-4956-905e-b0b5ef1a9188
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721066325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1721066325
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1984423494
Short name T781
Test name
Test status
Simulation time 14364955 ps
CPU time 0.59 seconds
Started Aug 07 05:12:45 PM PDT 24
Finished Aug 07 05:12:46 PM PDT 24
Peak memory 195112 kb
Host smart-51fb15a9-e494-4787-8535-9244ee04355c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984423494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1984423494
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.4047538705
Short name T727
Test name
Test status
Simulation time 16826844 ps
CPU time 0.59 seconds
Started Aug 07 05:12:43 PM PDT 24
Finished Aug 07 05:12:44 PM PDT 24
Peak memory 194568 kb
Host smart-fdf634f7-842b-428f-b015-905ce096be3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047538705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.4047538705
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.999585793
Short name T723
Test name
Test status
Simulation time 58070943 ps
CPU time 0.59 seconds
Started Aug 07 05:12:44 PM PDT 24
Finished Aug 07 05:12:44 PM PDT 24
Peak memory 194484 kb
Host smart-308fa48b-4365-4990-bfb6-9b530819f3fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999585793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.999585793
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2937610742
Short name T771
Test name
Test status
Simulation time 15611518 ps
CPU time 0.6 seconds
Started Aug 07 05:12:50 PM PDT 24
Finished Aug 07 05:12:51 PM PDT 24
Peak memory 194460 kb
Host smart-b4f75db1-d415-4afd-8e89-29d2cd3aec39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937610742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2937610742
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.4265216449
Short name T816
Test name
Test status
Simulation time 21628040 ps
CPU time 0.58 seconds
Started Aug 07 05:12:47 PM PDT 24
Finished Aug 07 05:12:47 PM PDT 24
Peak memory 194464 kb
Host smart-3a90214d-12e5-4b62-af7d-0ea0f5bd6926
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265216449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.4265216449
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2888755916
Short name T770
Test name
Test status
Simulation time 18267894 ps
CPU time 0.66 seconds
Started Aug 07 05:12:43 PM PDT 24
Finished Aug 07 05:12:43 PM PDT 24
Peak memory 194440 kb
Host smart-f5b339bd-ea47-48f7-bbc3-e7ea618dc3ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888755916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2888755916
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1841341783
Short name T792
Test name
Test status
Simulation time 14698453 ps
CPU time 0.6 seconds
Started Aug 07 05:12:51 PM PDT 24
Finished Aug 07 05:12:52 PM PDT 24
Peak memory 194344 kb
Host smart-967ea862-2373-4f06-b98f-47c151c83fa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841341783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1841341783
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3739029324
Short name T750
Test name
Test status
Simulation time 20202488 ps
CPU time 0.62 seconds
Started Aug 07 05:12:51 PM PDT 24
Finished Aug 07 05:12:52 PM PDT 24
Peak memory 194536 kb
Host smart-6568a8af-4980-4a20-bddd-bd87d56b33be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739029324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3739029324
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2872682842
Short name T824
Test name
Test status
Simulation time 91032847 ps
CPU time 0.71 seconds
Started Aug 07 05:11:53 PM PDT 24
Finished Aug 07 05:11:54 PM PDT 24
Peak memory 198568 kb
Host smart-e0c65c42-b1ed-4906-9d74-570adcb65cfe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872682842 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2872682842
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2437443905
Short name T68
Test name
Test status
Simulation time 14713958 ps
CPU time 0.59 seconds
Started Aug 07 05:11:54 PM PDT 24
Finished Aug 07 05:11:55 PM PDT 24
Peak memory 195232 kb
Host smart-173d0a1d-caee-41f5-b36d-8d17948c4719
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437443905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.2437443905
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.1105625410
Short name T837
Test name
Test status
Simulation time 22800859 ps
CPU time 0.59 seconds
Started Aug 07 05:11:52 PM PDT 24
Finished Aug 07 05:11:53 PM PDT 24
Peak memory 194512 kb
Host smart-335081e8-9642-4513-8fc4-f7938ac9b645
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105625410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.1105625410
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.394227629
Short name T846
Test name
Test status
Simulation time 16027086 ps
CPU time 0.63 seconds
Started Aug 07 05:11:54 PM PDT 24
Finished Aug 07 05:11:55 PM PDT 24
Peak memory 195420 kb
Host smart-3544e160-fce2-41ab-98c9-e5aefa5a40e9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394227629 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.394227629
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.760154207
Short name T847
Test name
Test status
Simulation time 80434908 ps
CPU time 1.12 seconds
Started Aug 07 05:11:54 PM PDT 24
Finished Aug 07 05:11:55 PM PDT 24
Peak memory 198828 kb
Host smart-4fb07018-e1a1-484e-9e18-f6ef73fbb6f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760154207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.760154207
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.947099503
Short name T793
Test name
Test status
Simulation time 115059435 ps
CPU time 1.46 seconds
Started Aug 07 05:11:53 PM PDT 24
Finished Aug 07 05:11:55 PM PDT 24
Peak memory 198644 kb
Host smart-bd11f967-218a-4f50-b855-6f877eaf3feb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947099503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.947099503
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2486882404
Short name T791
Test name
Test status
Simulation time 138110814 ps
CPU time 0.94 seconds
Started Aug 07 05:11:57 PM PDT 24
Finished Aug 07 05:11:58 PM PDT 24
Peak memory 198596 kb
Host smart-17976700-fce1-4d8c-afc4-a5e73af37d57
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486882404 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2486882404
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2507939760
Short name T795
Test name
Test status
Simulation time 78371314 ps
CPU time 0.6 seconds
Started Aug 07 05:11:59 PM PDT 24
Finished Aug 07 05:12:00 PM PDT 24
Peak memory 194096 kb
Host smart-75273fea-b02f-4b59-879b-c03133aff772
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507939760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2507939760
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3823198629
Short name T755
Test name
Test status
Simulation time 14210095 ps
CPU time 0.62 seconds
Started Aug 07 05:11:57 PM PDT 24
Finished Aug 07 05:11:58 PM PDT 24
Peak memory 194592 kb
Host smart-b48ad3d6-d2cd-4457-a1a4-246ec6a0aa38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823198629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3823198629
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.4089571052
Short name T84
Test name
Test status
Simulation time 54518744 ps
CPU time 0.69 seconds
Started Aug 07 05:11:59 PM PDT 24
Finished Aug 07 05:12:00 PM PDT 24
Peak memory 195620 kb
Host smart-1d9f5a5f-d0f8-4905-8b5f-36cd23ae2d98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089571052 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.4089571052
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.841583596
Short name T845
Test name
Test status
Simulation time 300359740 ps
CPU time 1.55 seconds
Started Aug 07 05:11:58 PM PDT 24
Finished Aug 07 05:11:59 PM PDT 24
Peak memory 198784 kb
Host smart-cea77ec6-ec62-4ef3-ab24-73a04b0cb115
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841583596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.841583596
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.675535822
Short name T843
Test name
Test status
Simulation time 49695721 ps
CPU time 0.91 seconds
Started Aug 07 05:11:59 PM PDT 24
Finished Aug 07 05:12:00 PM PDT 24
Peak memory 197748 kb
Host smart-b6687f56-e1ab-449f-b032-461d7c4b99fb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675535822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.675535822
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1769027600
Short name T801
Test name
Test status
Simulation time 111521764 ps
CPU time 0.87 seconds
Started Aug 07 05:12:05 PM PDT 24
Finished Aug 07 05:12:06 PM PDT 24
Peak memory 198612 kb
Host smart-51dc013f-a256-460c-89ab-f42aa53e6cd3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769027600 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1769027600
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1471120415
Short name T761
Test name
Test status
Simulation time 84098048 ps
CPU time 0.6 seconds
Started Aug 07 05:12:07 PM PDT 24
Finished Aug 07 05:12:08 PM PDT 24
Peak memory 196100 kb
Host smart-0eea97ca-02a9-48f8-acfd-d4cd9b1b033d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471120415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1471120415
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.312482849
Short name T826
Test name
Test status
Simulation time 17339922 ps
CPU time 0.61 seconds
Started Aug 07 05:12:04 PM PDT 24
Finished Aug 07 05:12:05 PM PDT 24
Peak memory 194508 kb
Host smart-9271c450-18af-47ca-8243-47df0cfcaedb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312482849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.312482849
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.4213672804
Short name T789
Test name
Test status
Simulation time 25774308 ps
CPU time 0.74 seconds
Started Aug 07 05:12:07 PM PDT 24
Finished Aug 07 05:12:08 PM PDT 24
Peak memory 196616 kb
Host smart-40cfc520-869d-4f89-a5a8-431a9840d34d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213672804 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.4213672804
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.401042952
Short name T754
Test name
Test status
Simulation time 198984894 ps
CPU time 1.05 seconds
Started Aug 07 05:12:03 PM PDT 24
Finished Aug 07 05:12:05 PM PDT 24
Peak memory 198632 kb
Host smart-7e76afb4-fd81-42f7-a428-bb7f4dbab11b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401042952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.401042952
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.4153147548
Short name T37
Test name
Test status
Simulation time 126845939 ps
CPU time 1.42 seconds
Started Aug 07 05:12:04 PM PDT 24
Finished Aug 07 05:12:05 PM PDT 24
Peak memory 198668 kb
Host smart-3d8195ed-b207-4550-870a-8b3aab217ae5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153147548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.4153147548
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3726420068
Short name T768
Test name
Test status
Simulation time 130773455 ps
CPU time 0.85 seconds
Started Aug 07 05:12:06 PM PDT 24
Finished Aug 07 05:12:07 PM PDT 24
Peak memory 198632 kb
Host smart-7e585b96-bd3d-4265-8eed-93e1e03be671
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726420068 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3726420068
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.490401445
Short name T80
Test name
Test status
Simulation time 16450479 ps
CPU time 0.62 seconds
Started Aug 07 05:12:03 PM PDT 24
Finished Aug 07 05:12:03 PM PDT 24
Peak memory 195508 kb
Host smart-4d53c6f3-ba84-455a-89b6-2896110a9f63
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490401445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.490401445
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.735651405
Short name T758
Test name
Test status
Simulation time 37184091 ps
CPU time 0.58 seconds
Started Aug 07 05:12:07 PM PDT 24
Finished Aug 07 05:12:07 PM PDT 24
Peak memory 194512 kb
Host smart-0105a8f8-22d7-45ea-80a4-e3b0fb07c286
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735651405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.735651405
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1245272411
Short name T786
Test name
Test status
Simulation time 85589175 ps
CPU time 0.81 seconds
Started Aug 07 05:12:04 PM PDT 24
Finished Aug 07 05:12:05 PM PDT 24
Peak memory 196900 kb
Host smart-e6f9060d-bd70-4b83-b71e-26884864faa7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245272411 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1245272411
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3540247008
Short name T806
Test name
Test status
Simulation time 44902063 ps
CPU time 2.31 seconds
Started Aug 07 05:12:04 PM PDT 24
Finished Aug 07 05:12:06 PM PDT 24
Peak memory 198872 kb
Host smart-722a3b41-fb69-4d7a-a83d-a8b6ca4b119c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540247008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.3540247008
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2267640748
Short name T43
Test name
Test status
Simulation time 428217661 ps
CPU time 1.43 seconds
Started Aug 07 05:12:07 PM PDT 24
Finished Aug 07 05:12:09 PM PDT 24
Peak memory 198792 kb
Host smart-0f569e00-9cd9-433b-b14e-7c3895afdec2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267640748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2267640748
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1318590227
Short name T819
Test name
Test status
Simulation time 231944708 ps
CPU time 0.7 seconds
Started Aug 07 05:12:10 PM PDT 24
Finished Aug 07 05:12:11 PM PDT 24
Peak memory 198548 kb
Host smart-f8e70d02-5f3e-4d7f-a6dc-b6618535d83c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318590227 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1318590227
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3659535883
Short name T729
Test name
Test status
Simulation time 47700806 ps
CPU time 0.59 seconds
Started Aug 07 05:12:12 PM PDT 24
Finished Aug 07 05:12:13 PM PDT 24
Peak memory 195308 kb
Host smart-d8a79772-6e4d-40e7-8475-ee4a6caf39cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659535883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3659535883
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2313388719
Short name T742
Test name
Test status
Simulation time 46350989 ps
CPU time 0.6 seconds
Started Aug 07 05:12:11 PM PDT 24
Finished Aug 07 05:12:11 PM PDT 24
Peak memory 194460 kb
Host smart-d7568304-9a63-4fb9-a1ad-a7170f3dadb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313388719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2313388719
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2615057812
Short name T83
Test name
Test status
Simulation time 19833527 ps
CPU time 0.67 seconds
Started Aug 07 05:12:10 PM PDT 24
Finished Aug 07 05:12:11 PM PDT 24
Peak memory 196060 kb
Host smart-57eab26f-cb94-46c4-a4f3-e9db6bc95bda
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615057812 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2615057812
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.798516988
Short name T759
Test name
Test status
Simulation time 93593561 ps
CPU time 2.06 seconds
Started Aug 07 05:12:11 PM PDT 24
Finished Aug 07 05:12:14 PM PDT 24
Peak memory 199028 kb
Host smart-eaaa7b91-1540-4fe4-80bd-9fa804b87f26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798516988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.798516988
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1500137427
Short name T643
Test name
Test status
Simulation time 45455037 ps
CPU time 0.56 seconds
Started Aug 07 05:26:29 PM PDT 24
Finished Aug 07 05:26:29 PM PDT 24
Peak memory 194532 kb
Host smart-fbe72aa9-7059-480f-9674-74ec1049d32e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500137427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1500137427
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3998461620
Short name T398
Test name
Test status
Simulation time 20505147 ps
CPU time 0.73 seconds
Started Aug 07 05:26:31 PM PDT 24
Finished Aug 07 05:26:32 PM PDT 24
Peak memory 195828 kb
Host smart-b22a9c1f-b1dd-4687-b34c-91b1788ce398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998461620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3998461620
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.1879844742
Short name T687
Test name
Test status
Simulation time 1141965859 ps
CPU time 14.52 seconds
Started Aug 07 05:26:32 PM PDT 24
Finished Aug 07 05:26:47 PM PDT 24
Peak memory 198540 kb
Host smart-09056626-4319-40a4-8674-bc6b9503ed7b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879844742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1879844742
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.708797252
Short name T276
Test name
Test status
Simulation time 306036109 ps
CPU time 0.91 seconds
Started Aug 07 05:26:29 PM PDT 24
Finished Aug 07 05:26:30 PM PDT 24
Peak memory 197668 kb
Host smart-176c268f-8368-4d05-ac5d-eb34836a92ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708797252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.708797252
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1423108192
Short name T330
Test name
Test status
Simulation time 378170928 ps
CPU time 1.26 seconds
Started Aug 07 05:26:31 PM PDT 24
Finished Aug 07 05:26:32 PM PDT 24
Peak memory 196356 kb
Host smart-c9973f07-67bf-4214-b7bb-b9341e316ca5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423108192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1423108192
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3791889866
Short name T391
Test name
Test status
Simulation time 265311921 ps
CPU time 3.67 seconds
Started Aug 07 05:26:30 PM PDT 24
Finished Aug 07 05:26:33 PM PDT 24
Peak memory 198612 kb
Host smart-df7ba104-78e7-4945-a92a-b18ad20937e3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791889866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3791889866
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3761062021
Short name T149
Test name
Test status
Simulation time 309683860 ps
CPU time 2.72 seconds
Started Aug 07 05:26:32 PM PDT 24
Finished Aug 07 05:26:35 PM PDT 24
Peak memory 197712 kb
Host smart-71daa030-51a0-4e62-9d89-0e78b0a485eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761062021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3761062021
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3925013161
Short name T472
Test name
Test status
Simulation time 192345064 ps
CPU time 1.17 seconds
Started Aug 07 05:26:24 PM PDT 24
Finished Aug 07 05:26:25 PM PDT 24
Peak memory 197400 kb
Host smart-c4f0237b-1917-43a7-b727-a26684a08bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925013161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3925013161
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.2968937208
Short name T656
Test name
Test status
Simulation time 27915951 ps
CPU time 1.01 seconds
Started Aug 07 05:26:27 PM PDT 24
Finished Aug 07 05:26:28 PM PDT 24
Peak memory 196480 kb
Host smart-f5ea43a1-5138-428e-b657-4e9f86b83d24
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968937208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.2968937208
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.4103443949
Short name T350
Test name
Test status
Simulation time 1074040694 ps
CPU time 4.82 seconds
Started Aug 07 05:26:35 PM PDT 24
Finished Aug 07 05:26:40 PM PDT 24
Peak memory 198540 kb
Host smart-ee5eebf9-7065-4621-b6d1-b37afddd571c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103443949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.4103443949
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.1567219451
Short name T457
Test name
Test status
Simulation time 54955269 ps
CPU time 1.08 seconds
Started Aug 07 05:26:24 PM PDT 24
Finished Aug 07 05:26:25 PM PDT 24
Peak memory 196776 kb
Host smart-8e67e6f6-1445-4456-8e23-e0085c2a6e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567219451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1567219451
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1443073533
Short name T173
Test name
Test status
Simulation time 184315970 ps
CPU time 1.24 seconds
Started Aug 07 05:26:26 PM PDT 24
Finished Aug 07 05:26:27 PM PDT 24
Peak memory 198412 kb
Host smart-a85de182-0568-4620-a6be-df501bd945f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443073533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1443073533
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1660549997
Short name T680
Test name
Test status
Simulation time 14936711159 ps
CPU time 102.26 seconds
Started Aug 07 05:26:29 PM PDT 24
Finished Aug 07 05:28:12 PM PDT 24
Peak memory 198704 kb
Host smart-7ee6e68b-23c3-4905-b694-2243d49617a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660549997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1660549997
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.462633024
Short name T390
Test name
Test status
Simulation time 523313878218 ps
CPU time 1674.93 seconds
Started Aug 07 05:26:29 PM PDT 24
Finished Aug 07 05:54:24 PM PDT 24
Peak memory 198816 kb
Host smart-3fdfe2e6-bbd4-485e-80fb-a37e1aa66e14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=462633024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.462633024
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2668019251
Short name T418
Test name
Test status
Simulation time 33733787 ps
CPU time 0.54 seconds
Started Aug 07 05:26:37 PM PDT 24
Finished Aug 07 05:26:37 PM PDT 24
Peak memory 194476 kb
Host smart-a3821456-5a36-4e79-8cbe-263afc9d0d81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668019251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2668019251
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3168714240
Short name T377
Test name
Test status
Simulation time 146633153 ps
CPU time 0.67 seconds
Started Aug 07 05:26:35 PM PDT 24
Finished Aug 07 05:26:36 PM PDT 24
Peak memory 194700 kb
Host smart-a0b65b18-2bbd-4547-9ff6-99442fa4f162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168714240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3168714240
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3022873733
Short name T105
Test name
Test status
Simulation time 5864853613 ps
CPU time 16.38 seconds
Started Aug 07 05:26:31 PM PDT 24
Finished Aug 07 05:26:48 PM PDT 24
Peak memory 197136 kb
Host smart-5d0ede46-9cc1-4078-8f68-b31dedc404ca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022873733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3022873733
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.793336150
Short name T447
Test name
Test status
Simulation time 56769205 ps
CPU time 0.73 seconds
Started Aug 07 05:26:39 PM PDT 24
Finished Aug 07 05:26:39 PM PDT 24
Peak memory 196188 kb
Host smart-a9cc103c-f27e-4bce-973c-9de36aabf54e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793336150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.793336150
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2748180066
Short name T444
Test name
Test status
Simulation time 23960591 ps
CPU time 0.77 seconds
Started Aug 07 05:26:31 PM PDT 24
Finished Aug 07 05:26:32 PM PDT 24
Peak memory 196640 kb
Host smart-82fcd3ce-655e-42f6-aeb3-d10b94264cbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748180066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2748180066
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3511652898
Short name T267
Test name
Test status
Simulation time 140921174 ps
CPU time 2.91 seconds
Started Aug 07 05:26:31 PM PDT 24
Finished Aug 07 05:26:34 PM PDT 24
Peak memory 198576 kb
Host smart-76f8ff90-4784-45ba-98ce-c17050796c60
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511652898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3511652898
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.894635244
Short name T504
Test name
Test status
Simulation time 83364665 ps
CPU time 0.89 seconds
Started Aug 07 05:26:30 PM PDT 24
Finished Aug 07 05:26:31 PM PDT 24
Peak memory 196580 kb
Host smart-1dedbe0f-cc93-4f3b-883b-7ae692b48e58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894635244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.894635244
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.4038291270
Short name T304
Test name
Test status
Simulation time 20876674 ps
CPU time 0.66 seconds
Started Aug 07 05:26:31 PM PDT 24
Finished Aug 07 05:26:32 PM PDT 24
Peak memory 194832 kb
Host smart-d1983ea8-c955-484b-9863-92ee43fc9bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038291270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.4038291270
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.841208194
Short name T123
Test name
Test status
Simulation time 34690302 ps
CPU time 0.89 seconds
Started Aug 07 05:26:29 PM PDT 24
Finished Aug 07 05:26:30 PM PDT 24
Peak memory 197060 kb
Host smart-45cb19df-31ff-48ac-9112-7589e1bccdd3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841208194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.841208194
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1698134617
Short name T188
Test name
Test status
Simulation time 872796229 ps
CPU time 3.54 seconds
Started Aug 07 05:26:42 PM PDT 24
Finished Aug 07 05:26:46 PM PDT 24
Peak memory 198604 kb
Host smart-dbd75636-35d3-4a71-b3d8-ee63a0f36acf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698134617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1698134617
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1722608487
Short name T45
Test name
Test status
Simulation time 308454061 ps
CPU time 0.92 seconds
Started Aug 07 05:26:38 PM PDT 24
Finished Aug 07 05:26:39 PM PDT 24
Peak memory 215408 kb
Host smart-20f6adff-5807-4348-9a03-f9ce69e214b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722608487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1722608487
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.422015276
Short name T232
Test name
Test status
Simulation time 37240515 ps
CPU time 0.99 seconds
Started Aug 07 05:26:32 PM PDT 24
Finished Aug 07 05:26:33 PM PDT 24
Peak memory 196016 kb
Host smart-7b9301c6-b517-45a2-b562-ff6bf316e8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422015276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.422015276
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1536542118
Short name T712
Test name
Test status
Simulation time 43091528 ps
CPU time 1.22 seconds
Started Aug 07 05:26:33 PM PDT 24
Finished Aug 07 05:26:35 PM PDT 24
Peak memory 198560 kb
Host smart-b37ba665-3799-49fd-b328-715b9513de0d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536542118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1536542118
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2863163184
Short name T622
Test name
Test status
Simulation time 6094063823 ps
CPU time 154.47 seconds
Started Aug 07 05:26:38 PM PDT 24
Finished Aug 07 05:29:13 PM PDT 24
Peak memory 198696 kb
Host smart-e5181191-775d-490b-9a22-b349f0aa5d6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863163184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2863163184
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2869972003
Short name T527
Test name
Test status
Simulation time 13118382 ps
CPU time 0.57 seconds
Started Aug 07 05:27:30 PM PDT 24
Finished Aug 07 05:27:31 PM PDT 24
Peak memory 194460 kb
Host smart-fc3acf57-0cc2-488a-8a27-ce08ce07b834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869972003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2869972003
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.26839623
Short name T423
Test name
Test status
Simulation time 487007425 ps
CPU time 0.82 seconds
Started Aug 07 05:27:24 PM PDT 24
Finished Aug 07 05:27:25 PM PDT 24
Peak memory 196500 kb
Host smart-ce088daa-c78c-4415-9369-72eb59f6518a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26839623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.26839623
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.784447779
Short name T30
Test name
Test status
Simulation time 1139495356 ps
CPU time 10.46 seconds
Started Aug 07 05:27:36 PM PDT 24
Finished Aug 07 05:27:47 PM PDT 24
Peak memory 198560 kb
Host smart-8f589149-da97-460c-aa36-9e22500ebbe7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784447779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stres
s.784447779
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3098204022
Short name T273
Test name
Test status
Simulation time 107830397 ps
CPU time 0.72 seconds
Started Aug 07 05:27:28 PM PDT 24
Finished Aug 07 05:27:29 PM PDT 24
Peak memory 196316 kb
Host smart-34a2670f-5977-4b58-8103-72283a3b6f51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098204022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3098204022
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1775683281
Short name T581
Test name
Test status
Simulation time 84556490 ps
CPU time 0.73 seconds
Started Aug 07 05:27:24 PM PDT 24
Finished Aug 07 05:27:25 PM PDT 24
Peak memory 195652 kb
Host smart-7d9d8b1c-83e2-4de4-82f2-50af38a0b57a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775683281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1775683281
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1864876903
Short name T635
Test name
Test status
Simulation time 34584339 ps
CPU time 1.4 seconds
Started Aug 07 05:27:29 PM PDT 24
Finished Aug 07 05:27:31 PM PDT 24
Peak memory 197140 kb
Host smart-cd307e4d-f82a-4c49-a4ac-a48ebfbae034
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864876903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1864876903
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1534053817
Short name T593
Test name
Test status
Simulation time 97158057 ps
CPU time 1.35 seconds
Started Aug 07 05:27:36 PM PDT 24
Finished Aug 07 05:27:38 PM PDT 24
Peak memory 197736 kb
Host smart-5e609f6a-fa73-45dd-be1e-6aff75dd0527
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534053817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1534053817
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2148670916
Short name T597
Test name
Test status
Simulation time 82719172 ps
CPU time 0.96 seconds
Started Aug 07 05:27:27 PM PDT 24
Finished Aug 07 05:27:28 PM PDT 24
Peak memory 197060 kb
Host smart-bd385ca3-1c83-40c5-8f25-fb424a45827c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148670916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2148670916
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2661894571
Short name T266
Test name
Test status
Simulation time 105167888 ps
CPU time 1.2 seconds
Started Aug 07 05:27:25 PM PDT 24
Finished Aug 07 05:27:26 PM PDT 24
Peak memory 197540 kb
Host smart-722ec10b-6fd6-4f5a-b320-58098ee8804d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661894571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2661894571
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3242721096
Short name T379
Test name
Test status
Simulation time 500993416 ps
CPU time 2.38 seconds
Started Aug 07 05:27:30 PM PDT 24
Finished Aug 07 05:27:33 PM PDT 24
Peak memory 198572 kb
Host smart-1c663512-7776-4190-a092-3a418efdb7b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242721096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3242721096
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.4293117127
Short name T495
Test name
Test status
Simulation time 194276780 ps
CPU time 1.05 seconds
Started Aug 07 05:27:24 PM PDT 24
Finished Aug 07 05:27:26 PM PDT 24
Peak memory 196020 kb
Host smart-d00e3cf9-02cd-4811-a809-0b6a7cf79258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293117127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.4293117127
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.714302932
Short name T278
Test name
Test status
Simulation time 78136951 ps
CPU time 0.67 seconds
Started Aug 07 05:27:23 PM PDT 24
Finished Aug 07 05:27:24 PM PDT 24
Peak memory 194688 kb
Host smart-a8d362bf-58c4-49ba-bc2a-d4dd77811b31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714302932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.714302932
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1562077779
Short name T92
Test name
Test status
Simulation time 173549418010 ps
CPU time 1258.73 seconds
Started Aug 07 05:27:30 PM PDT 24
Finished Aug 07 05:48:29 PM PDT 24
Peak memory 198884 kb
Host smart-1ca26fec-e89a-433d-bbcc-b86fd628df68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1562077779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1562077779
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.465731160
Short name T586
Test name
Test status
Simulation time 19116611 ps
CPU time 0.62 seconds
Started Aug 07 05:27:37 PM PDT 24
Finished Aug 07 05:27:38 PM PDT 24
Peak memory 194440 kb
Host smart-037411a6-2661-49ff-8976-1f0f481cebcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465731160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.465731160
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2935211314
Short name T312
Test name
Test status
Simulation time 36015466 ps
CPU time 0.68 seconds
Started Aug 07 05:27:38 PM PDT 24
Finished Aug 07 05:27:38 PM PDT 24
Peak memory 195312 kb
Host smart-78653a49-19da-45a2-bb5f-5e2a8bddd5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935211314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2935211314
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.913542986
Short name T257
Test name
Test status
Simulation time 13243826097 ps
CPU time 19.09 seconds
Started Aug 07 05:27:36 PM PDT 24
Finished Aug 07 05:27:55 PM PDT 24
Peak memory 198608 kb
Host smart-86987759-2df3-4ff3-a363-e74180d4cd4d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913542986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stres
s.913542986
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.4167727354
Short name T339
Test name
Test status
Simulation time 39534445 ps
CPU time 0.65 seconds
Started Aug 07 05:27:36 PM PDT 24
Finished Aug 07 05:27:36 PM PDT 24
Peak memory 195068 kb
Host smart-131632dc-b883-4d8e-a024-1ab6c5c7ef0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167727354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.4167727354
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2156843155
Short name T360
Test name
Test status
Simulation time 81541567 ps
CPU time 0.69 seconds
Started Aug 07 05:27:39 PM PDT 24
Finished Aug 07 05:27:40 PM PDT 24
Peak memory 195636 kb
Host smart-730a855e-0459-4d12-9d09-f0ecbace444d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156843155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2156843155
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1860415265
Short name T722
Test name
Test status
Simulation time 875639890 ps
CPU time 1.98 seconds
Started Aug 07 05:27:38 PM PDT 24
Finished Aug 07 05:27:40 PM PDT 24
Peak memory 198576 kb
Host smart-b7b3feec-21e5-4e21-a61c-4bd04f4307b5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860415265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1860415265
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2983383621
Short name T485
Test name
Test status
Simulation time 2138260816 ps
CPU time 3.25 seconds
Started Aug 07 05:27:37 PM PDT 24
Finished Aug 07 05:27:40 PM PDT 24
Peak memory 198564 kb
Host smart-6b8cbd8d-98ca-4e45-aa2f-92569903ee4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983383621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2983383621
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2215886583
Short name T358
Test name
Test status
Simulation time 80086184 ps
CPU time 0.89 seconds
Started Aug 07 05:27:39 PM PDT 24
Finished Aug 07 05:27:40 PM PDT 24
Peak memory 196544 kb
Host smart-7682ae3b-6d25-4f29-b615-405e20f7700c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215886583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2215886583
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2777819419
Short name T512
Test name
Test status
Simulation time 36862733 ps
CPU time 0.77 seconds
Started Aug 07 05:27:37 PM PDT 24
Finished Aug 07 05:27:38 PM PDT 24
Peak memory 197184 kb
Host smart-681b8605-f053-40c1-873d-c2650e5f8514
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777819419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2777819419
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3832208845
Short name T7
Test name
Test status
Simulation time 432554585 ps
CPU time 5.1 seconds
Started Aug 07 05:27:39 PM PDT 24
Finished Aug 07 05:27:45 PM PDT 24
Peak memory 198564 kb
Host smart-b6c95369-c6bf-4108-8872-81c63a4f97f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832208845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3832208845
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.969171133
Short name T113
Test name
Test status
Simulation time 60657490 ps
CPU time 1.07 seconds
Started Aug 07 05:27:29 PM PDT 24
Finished Aug 07 05:27:31 PM PDT 24
Peak memory 197108 kb
Host smart-c3850ecb-cbf3-439c-bbf8-6c4a244f9612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969171133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.969171133
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2801016538
Short name T487
Test name
Test status
Simulation time 126317392 ps
CPU time 1.02 seconds
Started Aug 07 05:27:30 PM PDT 24
Finished Aug 07 05:27:31 PM PDT 24
Peak memory 196068 kb
Host smart-e1c34cc7-fb60-40b1-99b7-94a785820958
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801016538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2801016538
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3808599925
Short name T412
Test name
Test status
Simulation time 22204489799 ps
CPU time 241.16 seconds
Started Aug 07 05:27:37 PM PDT 24
Finished Aug 07 05:31:38 PM PDT 24
Peak memory 198724 kb
Host smart-416f4e71-9b46-4dd8-a557-85eba097ef58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808599925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3808599925
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.993283529
Short name T671
Test name
Test status
Simulation time 30981490 ps
CPU time 0.57 seconds
Started Aug 07 05:27:43 PM PDT 24
Finished Aug 07 05:27:44 PM PDT 24
Peak memory 195204 kb
Host smart-898fef91-544d-4423-95ff-f6bbb1c77a16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993283529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.993283529
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3485532646
Short name T708
Test name
Test status
Simulation time 44024281 ps
CPU time 0.7 seconds
Started Aug 07 05:27:38 PM PDT 24
Finished Aug 07 05:27:38 PM PDT 24
Peak memory 195432 kb
Host smart-5e585986-bb4d-4ae9-ba34-07c066c6893b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485532646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3485532646
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3044429837
Short name T108
Test name
Test status
Simulation time 882944940 ps
CPU time 10.93 seconds
Started Aug 07 05:27:39 PM PDT 24
Finished Aug 07 05:27:50 PM PDT 24
Peak memory 198564 kb
Host smart-6d6f195f-49f0-4e7b-926a-e8e51bfd3214
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044429837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3044429837
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1066334855
Short name T587
Test name
Test status
Simulation time 69328910 ps
CPU time 1.08 seconds
Started Aug 07 05:28:15 PM PDT 24
Finished Aug 07 05:28:16 PM PDT 24
Peak memory 198620 kb
Host smart-a2d2dd82-9500-4c51-b33f-e81425bc3a10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066334855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1066334855
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2545572225
Short name T328
Test name
Test status
Simulation time 30786635 ps
CPU time 0.99 seconds
Started Aug 07 05:27:39 PM PDT 24
Finished Aug 07 05:27:40 PM PDT 24
Peak memory 196576 kb
Host smart-4c3ac6ae-fd49-488b-b94e-a6b1f6f753fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545572225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2545572225
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.583161032
Short name T286
Test name
Test status
Simulation time 27286150 ps
CPU time 1.15 seconds
Started Aug 07 05:27:35 PM PDT 24
Finished Aug 07 05:27:36 PM PDT 24
Peak memory 198560 kb
Host smart-e5a6602b-a3d1-47b0-bbe1-51f5a4e83455
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583161032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.583161032
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1588704259
Short name T317
Test name
Test status
Simulation time 114337754 ps
CPU time 1.28 seconds
Started Aug 07 05:27:35 PM PDT 24
Finished Aug 07 05:27:36 PM PDT 24
Peak memory 197376 kb
Host smart-f8f71265-4130-4397-ba7b-2e09877f1869
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588704259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1588704259
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3277385664
Short name T689
Test name
Test status
Simulation time 105481309 ps
CPU time 1.21 seconds
Started Aug 07 05:27:37 PM PDT 24
Finished Aug 07 05:27:39 PM PDT 24
Peak memory 197348 kb
Host smart-342d09c0-6ffb-4088-a778-886992d60b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277385664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3277385664
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.936579113
Short name T220
Test name
Test status
Simulation time 43074367 ps
CPU time 1.01 seconds
Started Aug 07 05:27:38 PM PDT 24
Finished Aug 07 05:27:39 PM PDT 24
Peak memory 196572 kb
Host smart-e244cfe5-ee0c-41f6-a1c7-154488d44e9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936579113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.936579113
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2542008563
Short name T489
Test name
Test status
Simulation time 212875820 ps
CPU time 1.76 seconds
Started Aug 07 05:27:42 PM PDT 24
Finished Aug 07 05:27:44 PM PDT 24
Peak memory 198416 kb
Host smart-970be06f-b1b0-4387-b7fd-e609b96b314c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542008563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2542008563
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3025431339
Short name T24
Test name
Test status
Simulation time 214540644 ps
CPU time 1.21 seconds
Started Aug 07 05:27:35 PM PDT 24
Finished Aug 07 05:27:37 PM PDT 24
Peak memory 198556 kb
Host smart-19473ab2-3bfd-4892-8afe-d792145868f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025431339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3025431339
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1946772974
Short name T14
Test name
Test status
Simulation time 421343653 ps
CPU time 1.43 seconds
Started Aug 07 05:27:38 PM PDT 24
Finished Aug 07 05:27:39 PM PDT 24
Peak memory 197280 kb
Host smart-3607e371-af01-4d1e-8fd6-85bbc4d9a6d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946772974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1946772974
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.612872954
Short name T673
Test name
Test status
Simulation time 35955663120 ps
CPU time 169.55 seconds
Started Aug 07 05:27:41 PM PDT 24
Finished Aug 07 05:30:31 PM PDT 24
Peak memory 198744 kb
Host smart-32627298-ac05-44f4-8d6f-a9a068b4923e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612872954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.g
pio_stress_all.612872954
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1725782685
Short name T638
Test name
Test status
Simulation time 473511466834 ps
CPU time 2380.01 seconds
Started Aug 07 05:27:43 PM PDT 24
Finished Aug 07 06:07:23 PM PDT 24
Peak memory 198856 kb
Host smart-9bd7a7fd-cb91-410f-9f29-7b90769edddb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1725782685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1725782685
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.941878982
Short name T222
Test name
Test status
Simulation time 61544589 ps
CPU time 0.57 seconds
Started Aug 07 05:27:56 PM PDT 24
Finished Aug 07 05:27:56 PM PDT 24
Peak memory 194488 kb
Host smart-592a3b9e-6b8c-4417-a06a-359dfdf271ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941878982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.941878982
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.4219162411
Short name T313
Test name
Test status
Simulation time 32477238 ps
CPU time 0.94 seconds
Started Aug 07 05:27:43 PM PDT 24
Finished Aug 07 05:27:44 PM PDT 24
Peak memory 197216 kb
Host smart-89a6a490-5a20-4973-9266-bef86d69282d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219162411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.4219162411
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.4150637179
Short name T663
Test name
Test status
Simulation time 1230203947 ps
CPU time 9.27 seconds
Started Aug 07 05:27:43 PM PDT 24
Finished Aug 07 05:27:53 PM PDT 24
Peak memory 197064 kb
Host smart-97618c3f-9e08-4813-a076-9068e2d39ba2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150637179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.4150637179
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1241135718
Short name T677
Test name
Test status
Simulation time 170533223 ps
CPU time 1.02 seconds
Started Aug 07 05:27:48 PM PDT 24
Finished Aug 07 05:27:49 PM PDT 24
Peak memory 198452 kb
Host smart-b5a838d5-4ff3-4727-b2cd-6ab936d855f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241135718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1241135718
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3752211393
Short name T634
Test name
Test status
Simulation time 68338254 ps
CPU time 1.2 seconds
Started Aug 07 05:27:42 PM PDT 24
Finished Aug 07 05:27:43 PM PDT 24
Peak memory 196744 kb
Host smart-405e166e-2031-4103-ba1d-8336d08fb696
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752211393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3752211393
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1950735678
Short name T347
Test name
Test status
Simulation time 201012614 ps
CPU time 2.24 seconds
Started Aug 07 05:27:41 PM PDT 24
Finished Aug 07 05:27:43 PM PDT 24
Peak memory 197024 kb
Host smart-7636b4fa-2806-449e-b766-d7bde2aecf30
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950735678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1950735678
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.913146251
Short name T299
Test name
Test status
Simulation time 45718776 ps
CPU time 1.08 seconds
Started Aug 07 05:27:42 PM PDT 24
Finished Aug 07 05:27:43 PM PDT 24
Peak memory 196016 kb
Host smart-817ff36d-2a26-4a56-b490-b55007c1f26e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913146251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
913146251
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1771093806
Short name T156
Test name
Test status
Simulation time 71219727 ps
CPU time 0.97 seconds
Started Aug 07 05:27:42 PM PDT 24
Finished Aug 07 05:27:43 PM PDT 24
Peak memory 196476 kb
Host smart-f1e6d67f-5bc1-4ebc-ba7b-8f94089139a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771093806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1771093806
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.223913832
Short name T416
Test name
Test status
Simulation time 89756329 ps
CPU time 0.76 seconds
Started Aug 07 05:27:43 PM PDT 24
Finished Aug 07 05:27:44 PM PDT 24
Peak memory 195944 kb
Host smart-b26a6b2e-c300-4c04-b0d6-4a2ace906629
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223913832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.223913832
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.4015874420
Short name T31
Test name
Test status
Simulation time 344207910 ps
CPU time 4.25 seconds
Started Aug 07 05:27:42 PM PDT 24
Finished Aug 07 05:27:46 PM PDT 24
Peak memory 198572 kb
Host smart-bb7f5d34-2cde-4a5e-9db4-73602701716a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015874420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.4015874420
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.654843005
Short name T598
Test name
Test status
Simulation time 23221006 ps
CPU time 0.78 seconds
Started Aug 07 05:27:40 PM PDT 24
Finished Aug 07 05:27:41 PM PDT 24
Peak memory 196500 kb
Host smart-2eade3d6-ba61-4ad6-8fd9-fad33470c262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654843005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.654843005
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1115301002
Short name T56
Test name
Test status
Simulation time 645165386 ps
CPU time 1.2 seconds
Started Aug 07 05:27:43 PM PDT 24
Finished Aug 07 05:27:44 PM PDT 24
Peak memory 196272 kb
Host smart-d0e8da26-33b1-422f-b2e5-077f2c157e95
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115301002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1115301002
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2928909625
Short name T305
Test name
Test status
Simulation time 21884398320 ps
CPU time 58.23 seconds
Started Aug 07 05:27:52 PM PDT 24
Finished Aug 07 05:28:51 PM PDT 24
Peak memory 198728 kb
Host smart-eb993b9c-7e5c-426e-88da-a3004a6d63a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928909625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2928909625
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.2666887904
Short name T51
Test name
Test status
Simulation time 96197749142 ps
CPU time 1991.55 seconds
Started Aug 07 05:27:50 PM PDT 24
Finished Aug 07 06:01:02 PM PDT 24
Peak memory 198860 kb
Host smart-d032d193-cb30-404e-adc3-f2e0d6d95caa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2666887904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.2666887904
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3677522241
Short name T650
Test name
Test status
Simulation time 38369422 ps
CPU time 0.56 seconds
Started Aug 07 05:27:48 PM PDT 24
Finished Aug 07 05:27:49 PM PDT 24
Peak memory 195132 kb
Host smart-664a5d01-eb7e-40ab-8c8e-def8287601ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677522241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3677522241
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3765727806
Short name T576
Test name
Test status
Simulation time 124968852 ps
CPU time 0.81 seconds
Started Aug 07 05:27:47 PM PDT 24
Finished Aug 07 05:27:48 PM PDT 24
Peak memory 196464 kb
Host smart-79737403-b658-48c3-90e1-ad3f9c6d1cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765727806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3765727806
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.395448658
Short name T310
Test name
Test status
Simulation time 4172641790 ps
CPU time 21.89 seconds
Started Aug 07 05:27:47 PM PDT 24
Finished Aug 07 05:28:09 PM PDT 24
Peak memory 198776 kb
Host smart-64601fad-79c9-45ab-8010-58091ee5b4df
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395448658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres
s.395448658
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.977935808
Short name T187
Test name
Test status
Simulation time 376981028 ps
CPU time 0.9 seconds
Started Aug 07 05:27:51 PM PDT 24
Finished Aug 07 05:27:52 PM PDT 24
Peak memory 197204 kb
Host smart-47e65142-1143-4ec1-bd7a-233783300313
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977935808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.977935808
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.701068948
Short name T594
Test name
Test status
Simulation time 90880786 ps
CPU time 1.22 seconds
Started Aug 07 05:27:48 PM PDT 24
Finished Aug 07 05:27:49 PM PDT 24
Peak memory 197160 kb
Host smart-b2b86771-34f5-4bc3-a7b4-355b296d2249
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701068948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.701068948
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3400482628
Short name T302
Test name
Test status
Simulation time 161287034 ps
CPU time 1.47 seconds
Started Aug 07 05:27:48 PM PDT 24
Finished Aug 07 05:27:50 PM PDT 24
Peak memory 197092 kb
Host smart-1fbff047-4253-4278-b221-b96560efec99
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400482628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3400482628
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1300297751
Short name T169
Test name
Test status
Simulation time 237441548 ps
CPU time 2.68 seconds
Started Aug 07 05:27:49 PM PDT 24
Finished Aug 07 05:27:52 PM PDT 24
Peak memory 197772 kb
Host smart-ab7e97f8-15ca-454a-894c-4dd1ff6e2bb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300297751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1300297751
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.4039271936
Short name T464
Test name
Test status
Simulation time 50713274 ps
CPU time 0.97 seconds
Started Aug 07 05:27:47 PM PDT 24
Finished Aug 07 05:27:48 PM PDT 24
Peak memory 196432 kb
Host smart-2436b9f1-4c3d-4c2e-8be4-bde8c43f28de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039271936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.4039271936
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.4256753287
Short name T224
Test name
Test status
Simulation time 178982303 ps
CPU time 1.04 seconds
Started Aug 07 05:27:50 PM PDT 24
Finished Aug 07 05:27:51 PM PDT 24
Peak memory 196548 kb
Host smart-5aea3e7f-5288-46fe-984c-59a835c99d76
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256753287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.4256753287
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2751981795
Short name T247
Test name
Test status
Simulation time 420063649 ps
CPU time 2.01 seconds
Started Aug 07 05:27:49 PM PDT 24
Finished Aug 07 05:27:52 PM PDT 24
Peak memory 198416 kb
Host smart-ad85bd48-2e16-4afc-b318-7f33477bbca9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751981795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2751981795
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.318542353
Short name T340
Test name
Test status
Simulation time 82771696 ps
CPU time 0.94 seconds
Started Aug 07 05:27:50 PM PDT 24
Finished Aug 07 05:27:52 PM PDT 24
Peak memory 196328 kb
Host smart-465f06f2-7980-4de6-816c-8f4edacc106d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318542353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.318542353
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3905651426
Short name T557
Test name
Test status
Simulation time 251575571 ps
CPU time 1.13 seconds
Started Aug 07 05:27:46 PM PDT 24
Finished Aug 07 05:27:47 PM PDT 24
Peak memory 196336 kb
Host smart-0e2fed98-a676-4577-80be-b467b376ab2c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905651426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3905651426
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2120443730
Short name T509
Test name
Test status
Simulation time 91094051233 ps
CPU time 219 seconds
Started Aug 07 05:27:47 PM PDT 24
Finished Aug 07 05:31:26 PM PDT 24
Peak memory 198628 kb
Host smart-722b1b1b-ac1f-4526-b119-56b4c5f54391
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120443730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2120443730
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3419856226
Short name T352
Test name
Test status
Simulation time 13272997 ps
CPU time 0.57 seconds
Started Aug 07 05:28:06 PM PDT 24
Finished Aug 07 05:28:07 PM PDT 24
Peak memory 195176 kb
Host smart-bcff257c-534a-40c2-b6e9-48cc629ba5f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419856226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3419856226
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3912747390
Short name T249
Test name
Test status
Simulation time 41435919 ps
CPU time 0.75 seconds
Started Aug 07 05:27:57 PM PDT 24
Finished Aug 07 05:27:58 PM PDT 24
Peak memory 195912 kb
Host smart-b6f94d05-e041-4cb3-881a-c86b4547ef6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912747390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3912747390
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1940680207
Short name T325
Test name
Test status
Simulation time 2137048839 ps
CPU time 15.46 seconds
Started Aug 07 05:27:58 PM PDT 24
Finished Aug 07 05:28:14 PM PDT 24
Peak memory 197020 kb
Host smart-1f08bc95-f214-4f91-9022-05085b36b478
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940680207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1940680207
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.524791742
Short name T190
Test name
Test status
Simulation time 57879816 ps
CPU time 0.65 seconds
Started Aug 07 05:27:56 PM PDT 24
Finished Aug 07 05:27:56 PM PDT 24
Peak memory 195096 kb
Host smart-5544060d-9ec9-4381-93ca-307c2197728d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524791742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.524791742
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.1123187658
Short name T370
Test name
Test status
Simulation time 92533342 ps
CPU time 0.67 seconds
Started Aug 07 05:28:06 PM PDT 24
Finished Aug 07 05:28:07 PM PDT 24
Peak memory 195644 kb
Host smart-98de81b2-db21-400c-8cdd-cc026cdef883
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123187658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.1123187658
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3099330931
Short name T446
Test name
Test status
Simulation time 66319996 ps
CPU time 0.91 seconds
Started Aug 07 05:27:59 PM PDT 24
Finished Aug 07 05:28:00 PM PDT 24
Peak memory 196500 kb
Host smart-295fa8ef-f760-4c1c-bc4c-506f1f5c3e61
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099330931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3099330931
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.3393219414
Short name T245
Test name
Test status
Simulation time 183568196 ps
CPU time 2.19 seconds
Started Aug 07 05:27:56 PM PDT 24
Finished Aug 07 05:27:59 PM PDT 24
Peak memory 197924 kb
Host smart-625b2386-8d60-4454-9e3f-cbaac02d48c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393219414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.3393219414
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3128596580
Short name T155
Test name
Test status
Simulation time 347290969 ps
CPU time 0.78 seconds
Started Aug 07 05:27:56 PM PDT 24
Finished Aug 07 05:27:57 PM PDT 24
Peak memory 195968 kb
Host smart-f9cedc74-6bb6-429a-a965-b220a46128e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128596580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3128596580
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.2936518443
Short name T653
Test name
Test status
Simulation time 22901025 ps
CPU time 0.62 seconds
Started Aug 07 05:27:58 PM PDT 24
Finished Aug 07 05:27:59 PM PDT 24
Peak memory 194792 kb
Host smart-affae1c9-ab0f-4c31-910c-65a63f482e61
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936518443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.2936518443
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.580541303
Short name T180
Test name
Test status
Simulation time 320664691 ps
CPU time 3.8 seconds
Started Aug 07 05:27:59 PM PDT 24
Finished Aug 07 05:28:02 PM PDT 24
Peak memory 198516 kb
Host smart-5eb10819-df47-4824-88fa-11c43b874fa0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580541303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.580541303
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.605217503
Short name T143
Test name
Test status
Simulation time 127397731 ps
CPU time 1.27 seconds
Started Aug 07 05:28:07 PM PDT 24
Finished Aug 07 05:28:09 PM PDT 24
Peak memory 197260 kb
Host smart-9d8c7590-a3b4-4004-a39a-b541c22ca0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605217503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.605217503
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3307314327
Short name T386
Test name
Test status
Simulation time 131008561 ps
CPU time 1.31 seconds
Started Aug 07 05:27:56 PM PDT 24
Finished Aug 07 05:27:58 PM PDT 24
Peak memory 196116 kb
Host smart-cdd08051-8686-4b24-9422-448c4b346670
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307314327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3307314327
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.4063743511
Short name T138
Test name
Test status
Simulation time 32873951743 ps
CPU time 119 seconds
Started Aug 07 05:27:59 PM PDT 24
Finished Aug 07 05:29:58 PM PDT 24
Peak memory 198784 kb
Host smart-c27ff11a-ac61-4294-9d88-af1783397102
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063743511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.4063743511
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.3968889560
Short name T713
Test name
Test status
Simulation time 237960099249 ps
CPU time 1325.23 seconds
Started Aug 07 05:27:55 PM PDT 24
Finished Aug 07 05:50:01 PM PDT 24
Peak memory 198876 kb
Host smart-5f39d6fc-20a0-4540-87bc-a4615033ff93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3968889560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.3968889560
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1441706922
Short name T508
Test name
Test status
Simulation time 14826491 ps
CPU time 0.6 seconds
Started Aug 07 05:28:03 PM PDT 24
Finished Aug 07 05:28:03 PM PDT 24
Peak memory 195200 kb
Host smart-dbe6398e-a0ae-4adb-91e6-44b6748c1a8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441706922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1441706922
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3516795922
Short name T649
Test name
Test status
Simulation time 53710790 ps
CPU time 0.65 seconds
Started Aug 07 05:27:57 PM PDT 24
Finished Aug 07 05:27:58 PM PDT 24
Peak memory 194640 kb
Host smart-639b119b-66a7-4081-921c-602a7ea54869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516795922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3516795922
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.454594839
Short name T152
Test name
Test status
Simulation time 270456703 ps
CPU time 13.47 seconds
Started Aug 07 05:27:52 PM PDT 24
Finished Aug 07 05:28:06 PM PDT 24
Peak memory 197424 kb
Host smart-1a46a400-ee17-49ff-99b6-2f04e099e23d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454594839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.454594839
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.801864773
Short name T158
Test name
Test status
Simulation time 91698944 ps
CPU time 0.92 seconds
Started Aug 07 05:27:59 PM PDT 24
Finished Aug 07 05:28:00 PM PDT 24
Peak memory 196316 kb
Host smart-3f448c89-98e3-4182-b89d-0c83b512f190
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801864773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.801864773
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2866693251
Short name T206
Test name
Test status
Simulation time 542685796 ps
CPU time 0.96 seconds
Started Aug 07 05:27:55 PM PDT 24
Finished Aug 07 05:27:56 PM PDT 24
Peak memory 196692 kb
Host smart-bc72ad4b-8e59-4d9d-9e28-f57db2f48100
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866693251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2866693251
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.661204463
Short name T588
Test name
Test status
Simulation time 75111277 ps
CPU time 2.77 seconds
Started Aug 07 05:28:07 PM PDT 24
Finished Aug 07 05:28:10 PM PDT 24
Peak memory 196868 kb
Host smart-af686534-9fb3-4164-a528-2e89b5571d48
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661204463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.gpio_intr_with_filter_rand_intr_event.661204463
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2778029009
Short name T717
Test name
Test status
Simulation time 643799988 ps
CPU time 1.78 seconds
Started Aug 07 05:27:56 PM PDT 24
Finished Aug 07 05:27:58 PM PDT 24
Peak memory 196472 kb
Host smart-1f10bf58-dabe-4d40-9aec-2464de399104
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778029009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2778029009
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3116997364
Short name T332
Test name
Test status
Simulation time 34337087 ps
CPU time 1.24 seconds
Started Aug 07 05:27:56 PM PDT 24
Finished Aug 07 05:27:57 PM PDT 24
Peak memory 197428 kb
Host smart-b1dd9fe4-21d8-4ab5-882e-64f0b4bf84e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116997364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3116997364
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.109425484
Short name T166
Test name
Test status
Simulation time 212390324 ps
CPU time 1.21 seconds
Started Aug 07 05:28:07 PM PDT 24
Finished Aug 07 05:28:09 PM PDT 24
Peak memory 197288 kb
Host smart-ddc7cece-ffb4-41fb-8de6-cc810d1bfe61
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109425484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.109425484
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2696302462
Short name T533
Test name
Test status
Simulation time 385622769 ps
CPU time 4.4 seconds
Started Aug 07 05:27:59 PM PDT 24
Finished Aug 07 05:28:04 PM PDT 24
Peak memory 198464 kb
Host smart-0b6c21c2-ac81-42bf-949c-b2039248045e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696302462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2696302462
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.1689999767
Short name T337
Test name
Test status
Simulation time 82167677 ps
CPU time 1.05 seconds
Started Aug 07 05:28:07 PM PDT 24
Finished Aug 07 05:28:08 PM PDT 24
Peak memory 196092 kb
Host smart-bb904193-67bf-47f2-87f0-9b9f81d3803c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689999767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1689999767
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.868006781
Short name T688
Test name
Test status
Simulation time 147053711 ps
CPU time 1.09 seconds
Started Aug 07 05:28:06 PM PDT 24
Finished Aug 07 05:28:08 PM PDT 24
Peak memory 196388 kb
Host smart-c97c1ef0-af74-458b-b4d0-638ca1167f64
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868006781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.868006781
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.3045970560
Short name T439
Test name
Test status
Simulation time 8524138166 ps
CPU time 111.13 seconds
Started Aug 07 05:28:05 PM PDT 24
Finished Aug 07 05:29:56 PM PDT 24
Peak memory 198632 kb
Host smart-e5e961a2-5e7f-4e4c-84b9-0f8ddd2584cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045970560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.3045970560
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.2151946463
Short name T52
Test name
Test status
Simulation time 131551800191 ps
CPU time 1822.29 seconds
Started Aug 07 05:28:04 PM PDT 24
Finished Aug 07 05:58:27 PM PDT 24
Peak memory 198904 kb
Host smart-920914c3-48ee-4344-b804-d50616be23e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2151946463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.2151946463
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2671843801
Short name T425
Test name
Test status
Simulation time 31735005 ps
CPU time 0.56 seconds
Started Aug 07 05:28:06 PM PDT 24
Finished Aug 07 05:28:06 PM PDT 24
Peak memory 194496 kb
Host smart-419ab508-c9ee-4870-82f0-a5f3ce53f72a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671843801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2671843801
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1371271800
Short name T501
Test name
Test status
Simulation time 60016702 ps
CPU time 0.62 seconds
Started Aug 07 05:28:04 PM PDT 24
Finished Aug 07 05:28:05 PM PDT 24
Peak memory 194480 kb
Host smart-e26cb3e1-0f6d-4c66-9385-2cf3e4649e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371271800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1371271800
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.275411669
Short name T140
Test name
Test status
Simulation time 1121916685 ps
CPU time 18.61 seconds
Started Aug 07 05:28:06 PM PDT 24
Finished Aug 07 05:28:25 PM PDT 24
Peak memory 198560 kb
Host smart-0af53420-6309-44bf-a81f-07abec4c71e2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275411669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres
s.275411669
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1571208656
Short name T473
Test name
Test status
Simulation time 575290426 ps
CPU time 1.12 seconds
Started Aug 07 05:28:05 PM PDT 24
Finished Aug 07 05:28:06 PM PDT 24
Peak memory 197116 kb
Host smart-4881b70e-8b41-41b0-b959-ee3ffddd0fa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571208656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1571208656
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2371263952
Short name T714
Test name
Test status
Simulation time 255031118 ps
CPU time 0.87 seconds
Started Aug 07 05:28:06 PM PDT 24
Finished Aug 07 05:28:07 PM PDT 24
Peak memory 196216 kb
Host smart-5db3eed6-a0d7-4caa-8ebb-ae991cb8155b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371263952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2371263952
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.957030578
Short name T601
Test name
Test status
Simulation time 86625500 ps
CPU time 1.14 seconds
Started Aug 07 05:28:02 PM PDT 24
Finished Aug 07 05:28:03 PM PDT 24
Peak memory 197248 kb
Host smart-b6995715-cbc9-46b6-a233-7ba596ac516f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957030578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.957030578
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1966508839
Short name T357
Test name
Test status
Simulation time 567126618 ps
CPU time 2.79 seconds
Started Aug 07 05:28:04 PM PDT 24
Finished Aug 07 05:28:08 PM PDT 24
Peak memory 197624 kb
Host smart-094b7c5d-5b82-4aac-a647-7569bbf1c0ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966508839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1966508839
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3412582432
Short name T526
Test name
Test status
Simulation time 90096001 ps
CPU time 0.96 seconds
Started Aug 07 05:28:04 PM PDT 24
Finished Aug 07 05:28:05 PM PDT 24
Peak memory 197276 kb
Host smart-f0198798-ba86-4109-a1f5-1b742d150692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412582432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3412582432
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.382316618
Short name T163
Test name
Test status
Simulation time 18224080 ps
CPU time 0.69 seconds
Started Aug 07 05:28:02 PM PDT 24
Finished Aug 07 05:28:03 PM PDT 24
Peak memory 195932 kb
Host smart-155c2422-16f7-40a5-8607-99ae37a745f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382316618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.382316618
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2340868409
Short name T6
Test name
Test status
Simulation time 1539946908 ps
CPU time 3.12 seconds
Started Aug 07 05:28:03 PM PDT 24
Finished Aug 07 05:28:06 PM PDT 24
Peak memory 198580 kb
Host smart-906d300b-aa36-4b51-a544-51635f9f2eec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340868409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.2340868409
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1293098256
Short name T470
Test name
Test status
Simulation time 77455376 ps
CPU time 1.19 seconds
Started Aug 07 05:28:04 PM PDT 24
Finished Aug 07 05:28:05 PM PDT 24
Peak memory 196892 kb
Host smart-206b9927-aefb-4673-b130-7ae12bfb63a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293098256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1293098256
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1941856719
Short name T499
Test name
Test status
Simulation time 20806843 ps
CPU time 0.68 seconds
Started Aug 07 05:28:03 PM PDT 24
Finished Aug 07 05:28:03 PM PDT 24
Peak memory 194748 kb
Host smart-9d0d3b55-7e92-4f12-ba16-ac1c67ef8031
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941856719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1941856719
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3765150882
Short name T362
Test name
Test status
Simulation time 2150349700 ps
CPU time 56.04 seconds
Started Aug 07 05:28:05 PM PDT 24
Finished Aug 07 05:29:01 PM PDT 24
Peak memory 198692 kb
Host smart-65348e9c-aa06-487b-88d4-1968fdd2452b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765150882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3765150882
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3394239658
Short name T364
Test name
Test status
Simulation time 31886221 ps
CPU time 0.56 seconds
Started Aug 07 05:28:07 PM PDT 24
Finished Aug 07 05:28:08 PM PDT 24
Peak memory 195436 kb
Host smart-431c1572-3b96-4754-bf25-69a306b6903f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394239658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3394239658
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1657039379
Short name T682
Test name
Test status
Simulation time 19665749 ps
CPU time 0.69 seconds
Started Aug 07 05:28:05 PM PDT 24
Finished Aug 07 05:28:06 PM PDT 24
Peak memory 195824 kb
Host smart-94a49025-33d6-4cb3-8fde-f04a5b12fd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657039379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1657039379
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1779276175
Short name T361
Test name
Test status
Simulation time 559592107 ps
CPU time 14.83 seconds
Started Aug 07 05:28:10 PM PDT 24
Finished Aug 07 05:28:25 PM PDT 24
Peak memory 197296 kb
Host smart-a88982bb-d9cc-4497-90ac-d4cc3111e583
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779276175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1779276175
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1544666706
Short name T440
Test name
Test status
Simulation time 41492105 ps
CPU time 0.76 seconds
Started Aug 07 05:28:09 PM PDT 24
Finished Aug 07 05:28:10 PM PDT 24
Peak memory 196308 kb
Host smart-229c4dc9-b500-4499-9b86-f86f93b052ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544666706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1544666706
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2978925392
Short name T201
Test name
Test status
Simulation time 97250517 ps
CPU time 1.38 seconds
Started Aug 07 05:28:08 PM PDT 24
Finished Aug 07 05:28:09 PM PDT 24
Peak memory 196424 kb
Host smart-56941e6b-0bb1-48cc-91d7-563fd1567060
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978925392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2978925392
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.713665163
Short name T99
Test name
Test status
Simulation time 227727425 ps
CPU time 2.4 seconds
Started Aug 07 05:28:24 PM PDT 24
Finished Aug 07 05:28:26 PM PDT 24
Peak memory 197760 kb
Host smart-ab7fb4dc-9b27-4307-a140-5d4e59125a57
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713665163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.713665163
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2869544340
Short name T320
Test name
Test status
Simulation time 683428559 ps
CPU time 1.45 seconds
Started Aug 07 05:28:08 PM PDT 24
Finished Aug 07 05:28:10 PM PDT 24
Peak memory 196648 kb
Host smart-01f19619-89ba-4feb-81be-c54e0b24bf35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869544340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2869544340
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1686894146
Short name T520
Test name
Test status
Simulation time 24101702 ps
CPU time 0.65 seconds
Started Aug 07 05:28:06 PM PDT 24
Finished Aug 07 05:28:06 PM PDT 24
Peak memory 195528 kb
Host smart-912201f0-7719-44fc-ad31-d7d99c815ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686894146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1686894146
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3018155520
Short name T569
Test name
Test status
Simulation time 81399122 ps
CPU time 1.43 seconds
Started Aug 07 05:28:04 PM PDT 24
Finished Aug 07 05:28:06 PM PDT 24
Peak memory 196368 kb
Host smart-4fc9eb1c-daa8-45a9-ad91-633ebd9bc94e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018155520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3018155520
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2890709553
Short name T331
Test name
Test status
Simulation time 131668238 ps
CPU time 5.72 seconds
Started Aug 07 05:28:10 PM PDT 24
Finished Aug 07 05:28:16 PM PDT 24
Peak memory 198560 kb
Host smart-6e2f2c18-6652-4d39-8450-890fd6e0b0a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890709553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2890709553
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.403399490
Short name T142
Test name
Test status
Simulation time 55241785 ps
CPU time 1.2 seconds
Started Aug 07 05:28:04 PM PDT 24
Finished Aug 07 05:28:05 PM PDT 24
Peak memory 197364 kb
Host smart-200a9871-4348-432f-9de6-184ca6da9f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403399490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.403399490
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1537082115
Short name T306
Test name
Test status
Simulation time 100117040 ps
CPU time 0.93 seconds
Started Aug 07 05:28:04 PM PDT 24
Finished Aug 07 05:28:06 PM PDT 24
Peak memory 196128 kb
Host smart-72427e9f-4b0f-4c19-a469-d400e3dfa6d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537082115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1537082115
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.244841351
Short name T469
Test name
Test status
Simulation time 21555562889 ps
CPU time 153.35 seconds
Started Aug 07 05:28:11 PM PDT 24
Finished Aug 07 05:30:44 PM PDT 24
Peak memory 198760 kb
Host smart-6f7ae449-cca5-4b04-aec3-942a2a0ffeb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244841351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.244841351
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.2518228123
Short name T54
Test name
Test status
Simulation time 130830988310 ps
CPU time 410.36 seconds
Started Aug 07 05:28:09 PM PDT 24
Finished Aug 07 05:35:00 PM PDT 24
Peak memory 198864 kb
Host smart-07da4ca7-6f0c-4044-92f8-622f2732c1e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2518228123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.2518228123
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.4279728085
Short name T183
Test name
Test status
Simulation time 23523643 ps
CPU time 0.56 seconds
Started Aug 07 05:28:19 PM PDT 24
Finished Aug 07 05:28:19 PM PDT 24
Peak memory 194648 kb
Host smart-0587df07-883b-441e-a0f7-9b96a7c9346e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279728085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.4279728085
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1262666276
Short name T233
Test name
Test status
Simulation time 85432585 ps
CPU time 0.69 seconds
Started Aug 07 05:28:16 PM PDT 24
Finished Aug 07 05:28:16 PM PDT 24
Peak memory 194572 kb
Host smart-95531e67-aae2-41f0-8c73-15f55ed5e932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262666276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1262666276
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.447223907
Short name T644
Test name
Test status
Simulation time 750276549 ps
CPU time 20.66 seconds
Started Aug 07 05:28:15 PM PDT 24
Finished Aug 07 05:28:35 PM PDT 24
Peak memory 196072 kb
Host smart-b100c8d7-2999-4594-ab24-eb0392c5692a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447223907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.447223907
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3130024147
Short name T3
Test name
Test status
Simulation time 146223555 ps
CPU time 1.06 seconds
Started Aug 07 05:28:13 PM PDT 24
Finished Aug 07 05:28:14 PM PDT 24
Peak memory 196948 kb
Host smart-6b65bd23-15fc-4753-8b55-27e67e8f163d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130024147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3130024147
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2406253538
Short name T445
Test name
Test status
Simulation time 69010591 ps
CPU time 0.88 seconds
Started Aug 07 05:28:18 PM PDT 24
Finished Aug 07 05:28:19 PM PDT 24
Peak memory 196048 kb
Host smart-52883c60-2eea-4a26-95f3-0d19c1fd03cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406253538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2406253538
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3026357809
Short name T283
Test name
Test status
Simulation time 50062911 ps
CPU time 1.14 seconds
Started Aug 07 05:28:13 PM PDT 24
Finished Aug 07 05:28:14 PM PDT 24
Peak memory 196780 kb
Host smart-d8fa4c08-15d8-4e0d-800f-209d9a0455d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026357809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3026357809
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.4271972745
Short name T616
Test name
Test status
Simulation time 44722567 ps
CPU time 0.73 seconds
Started Aug 07 05:28:17 PM PDT 24
Finished Aug 07 05:28:18 PM PDT 24
Peak memory 195844 kb
Host smart-6e286241-e8e2-456c-819d-5097882880c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271972745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.4271972745
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.218248378
Short name T268
Test name
Test status
Simulation time 144384606 ps
CPU time 0.91 seconds
Started Aug 07 05:28:09 PM PDT 24
Finished Aug 07 05:28:10 PM PDT 24
Peak memory 196432 kb
Host smart-f6e95a24-feb8-4773-a7be-d122e317b36b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218248378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.218248378
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2659752916
Short name T535
Test name
Test status
Simulation time 127624108 ps
CPU time 1.53 seconds
Started Aug 07 05:28:14 PM PDT 24
Finished Aug 07 05:28:15 PM PDT 24
Peak memory 198612 kb
Host smart-89eebb5d-26c5-4bec-9c97-a6754c92fe68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659752916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2659752916
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.4281972071
Short name T702
Test name
Test status
Simulation time 303168141 ps
CPU time 1.13 seconds
Started Aug 07 05:28:09 PM PDT 24
Finished Aug 07 05:28:10 PM PDT 24
Peak memory 196964 kb
Host smart-261ae762-bc23-47dc-93c5-47173fa0d78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281972071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.4281972071
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1247477670
Short name T295
Test name
Test status
Simulation time 404021546 ps
CPU time 0.8 seconds
Started Aug 07 05:28:10 PM PDT 24
Finished Aug 07 05:28:11 PM PDT 24
Peak memory 196544 kb
Host smart-286b6253-7592-4794-8611-f470b1869cf3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247477670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1247477670
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1360137978
Short name T8
Test name
Test status
Simulation time 4613269351 ps
CPU time 48.24 seconds
Started Aug 07 05:28:16 PM PDT 24
Finished Aug 07 05:29:05 PM PDT 24
Peak memory 198748 kb
Host smart-75e4d37d-36c0-48e1-862b-d831dc167b0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360137978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1360137978
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3667495202
Short name T130
Test name
Test status
Simulation time 11116528 ps
CPU time 0.56 seconds
Started Aug 07 05:26:44 PM PDT 24
Finished Aug 07 05:26:45 PM PDT 24
Peak memory 193280 kb
Host smart-3b54b035-a524-41e6-823d-f36c7dc9677a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667495202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3667495202
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2813928720
Short name T264
Test name
Test status
Simulation time 59233843 ps
CPU time 0.7 seconds
Started Aug 07 05:26:39 PM PDT 24
Finished Aug 07 05:26:40 PM PDT 24
Peak memory 195644 kb
Host smart-ff5b7d54-325a-4d87-8308-45b4c8115b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813928720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2813928720
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.22248068
Short name T614
Test name
Test status
Simulation time 4667883758 ps
CPU time 26.35 seconds
Started Aug 07 05:26:43 PM PDT 24
Finished Aug 07 05:27:09 PM PDT 24
Peak memory 198668 kb
Host smart-acbf3909-abb5-4279-8283-a3e4f225d074
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22248068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress.22248068
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.243712167
Short name T559
Test name
Test status
Simulation time 165972299 ps
CPU time 0.87 seconds
Started Aug 07 05:26:45 PM PDT 24
Finished Aug 07 05:26:46 PM PDT 24
Peak memory 197752 kb
Host smart-ee4e27fe-a9e9-47fa-aeae-4b28891e32f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243712167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.243712167
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.4212640649
Short name T465
Test name
Test status
Simulation time 373349024 ps
CPU time 1.3 seconds
Started Aug 07 05:26:42 PM PDT 24
Finished Aug 07 05:26:43 PM PDT 24
Peak memory 197656 kb
Host smart-6caf0421-e4fd-4b1e-ae2f-6d39ac37cdfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212640649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.4212640649
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3102159997
Short name T437
Test name
Test status
Simulation time 110314043 ps
CPU time 1.24 seconds
Started Aug 07 05:26:47 PM PDT 24
Finished Aug 07 05:26:48 PM PDT 24
Peak memory 196912 kb
Host smart-55e463f1-eff3-4df6-87e8-0c6fc9186948
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102159997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3102159997
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.439688316
Short name T521
Test name
Test status
Simulation time 55652764 ps
CPU time 1.06 seconds
Started Aug 07 05:26:51 PM PDT 24
Finished Aug 07 05:26:52 PM PDT 24
Peak memory 196876 kb
Host smart-740913d1-8117-4d4b-b8e9-67060000782e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439688316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.439688316
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.4012211172
Short name T552
Test name
Test status
Simulation time 46487106 ps
CPU time 0.96 seconds
Started Aug 07 05:26:42 PM PDT 24
Finished Aug 07 05:26:43 PM PDT 24
Peak memory 197120 kb
Host smart-90c2b225-95ab-41f1-93c8-827f012950d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012211172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.4012211172
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2823742878
Short name T289
Test name
Test status
Simulation time 76644972 ps
CPU time 0.88 seconds
Started Aug 07 05:26:41 PM PDT 24
Finished Aug 07 05:26:42 PM PDT 24
Peak memory 196552 kb
Host smart-ef8ae1ea-0b21-4ae7-bdf3-18281196ecc0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823742878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2823742878
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.312827592
Short name T217
Test name
Test status
Simulation time 395102324 ps
CPU time 1.9 seconds
Started Aug 07 05:26:44 PM PDT 24
Finished Aug 07 05:26:46 PM PDT 24
Peak memory 198540 kb
Host smart-07516e52-0163-4763-96e0-583898501ab4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312827592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.312827592
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.4169900507
Short name T46
Test name
Test status
Simulation time 158497475 ps
CPU time 0.92 seconds
Started Aug 07 05:26:49 PM PDT 24
Finished Aug 07 05:26:50 PM PDT 24
Peak memory 215532 kb
Host smart-f5c4e43a-aca3-47e0-9d6b-e4d682a81121
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169900507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.4169900507
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.991300750
Short name T372
Test name
Test status
Simulation time 409741903 ps
CPU time 0.99 seconds
Started Aug 07 05:26:39 PM PDT 24
Finished Aug 07 05:26:40 PM PDT 24
Peak memory 196772 kb
Host smart-fcc3a596-ba69-40e6-b620-ebab0bcd1065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991300750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.991300750
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2637521154
Short name T314
Test name
Test status
Simulation time 59934978 ps
CPU time 1.12 seconds
Started Aug 07 05:26:39 PM PDT 24
Finished Aug 07 05:26:40 PM PDT 24
Peak memory 196276 kb
Host smart-4b9f557f-116c-4e35-bed6-f6738c01a077
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637521154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2637521154
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.2896353404
Short name T678
Test name
Test status
Simulation time 16915215836 ps
CPU time 174.57 seconds
Started Aug 07 05:26:47 PM PDT 24
Finished Aug 07 05:29:41 PM PDT 24
Peak memory 192664 kb
Host smart-3eb0a526-5358-4f77-8f43-f517b7b6eb20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896353404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2896353404
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.3218497169
Short name T568
Test name
Test status
Simulation time 27650243806 ps
CPU time 207.48 seconds
Started Aug 07 05:26:46 PM PDT 24
Finished Aug 07 05:30:13 PM PDT 24
Peak memory 198884 kb
Host smart-ca5d5454-4000-4858-ac4f-2ef75a95444f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3218497169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.3218497169
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1923513806
Short name T693
Test name
Test status
Simulation time 31253174 ps
CPU time 0.64 seconds
Started Aug 07 05:28:18 PM PDT 24
Finished Aug 07 05:28:18 PM PDT 24
Peak memory 195324 kb
Host smart-452f9fbe-db0e-43d0-bd64-a1273b8732c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923513806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1923513806
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1647838063
Short name T694
Test name
Test status
Simulation time 704000918 ps
CPU time 18.11 seconds
Started Aug 07 05:28:19 PM PDT 24
Finished Aug 07 05:28:37 PM PDT 24
Peak memory 198556 kb
Host smart-5c2821ce-1f4b-48c8-a220-f5889a8c9691
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647838063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1647838063
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.966719488
Short name T161
Test name
Test status
Simulation time 110161392 ps
CPU time 0.7 seconds
Started Aug 07 05:28:34 PM PDT 24
Finished Aug 07 05:28:35 PM PDT 24
Peak memory 196156 kb
Host smart-329e73e0-8f06-4fa1-b810-f04897e88b24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966719488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.966719488
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.3924696738
Short name T596
Test name
Test status
Simulation time 98136972 ps
CPU time 1.13 seconds
Started Aug 07 05:28:17 PM PDT 24
Finished Aug 07 05:28:18 PM PDT 24
Peak memory 197736 kb
Host smart-b5574d69-e4a3-4d67-8d7f-750fd1b3f19f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924696738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.3924696738
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.600540362
Short name T298
Test name
Test status
Simulation time 48882481 ps
CPU time 2.02 seconds
Started Aug 07 05:28:13 PM PDT 24
Finished Aug 07 05:28:15 PM PDT 24
Peak memory 198688 kb
Host smart-276b4541-f2c3-41ef-bf18-ab3448ea1452
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600540362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.600540362
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1473528899
Short name T109
Test name
Test status
Simulation time 77282809 ps
CPU time 1.91 seconds
Started Aug 07 05:28:14 PM PDT 24
Finished Aug 07 05:28:16 PM PDT 24
Peak memory 197432 kb
Host smart-b4a6df23-11c1-4d7e-a280-4f52a9888970
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473528899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1473528899
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1231157582
Short name T394
Test name
Test status
Simulation time 36659775 ps
CPU time 0.75 seconds
Started Aug 07 05:28:14 PM PDT 24
Finished Aug 07 05:28:15 PM PDT 24
Peak memory 195820 kb
Host smart-2ff4070d-ea54-4db4-976f-5c39d24b2144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231157582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1231157582
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.597726948
Short name T392
Test name
Test status
Simulation time 18477462 ps
CPU time 0.61 seconds
Started Aug 07 05:28:21 PM PDT 24
Finished Aug 07 05:28:21 PM PDT 24
Peak memory 194712 kb
Host smart-d0fb47c0-6b83-4304-b21a-aa507a2ac873
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597726948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup
_pulldown.597726948
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3949933792
Short name T658
Test name
Test status
Simulation time 477222672 ps
CPU time 5.57 seconds
Started Aug 07 05:28:16 PM PDT 24
Finished Aug 07 05:28:22 PM PDT 24
Peak memory 198548 kb
Host smart-3266a5cc-1ba5-4358-bcbd-37c9a9ebb79f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949933792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3949933792
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2070424624
Short name T336
Test name
Test status
Simulation time 85112203 ps
CPU time 1.31 seconds
Started Aug 07 05:28:15 PM PDT 24
Finished Aug 07 05:28:16 PM PDT 24
Peak memory 197296 kb
Host smart-c0953284-d2a2-4842-b7a5-062fb55a18f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070424624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2070424624
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.4255920283
Short name T112
Test name
Test status
Simulation time 34902465 ps
CPU time 0.79 seconds
Started Aug 07 05:28:16 PM PDT 24
Finished Aug 07 05:28:17 PM PDT 24
Peak memory 195840 kb
Host smart-f869f4ff-f42c-4bfc-a386-aacba8d54d7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255920283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.4255920283
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1813428459
Short name T480
Test name
Test status
Simulation time 3912765690 ps
CPU time 53 seconds
Started Aug 07 05:28:13 PM PDT 24
Finished Aug 07 05:29:06 PM PDT 24
Peak memory 198712 kb
Host smart-02c6292a-c42e-44a0-909e-8adf9bca66e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813428459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1813428459
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.945342214
Short name T719
Test name
Test status
Simulation time 13071731 ps
CPU time 0.58 seconds
Started Aug 07 05:28:21 PM PDT 24
Finished Aug 07 05:28:22 PM PDT 24
Peak memory 194484 kb
Host smart-a66ad6cf-28a2-454f-a5e8-40df9591ce27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945342214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.945342214
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2703967616
Short name T135
Test name
Test status
Simulation time 46500871 ps
CPU time 0.87 seconds
Started Aug 07 05:28:19 PM PDT 24
Finished Aug 07 05:28:20 PM PDT 24
Peak memory 197036 kb
Host smart-14bf864b-ff56-4bda-8440-ba15e06ef3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703967616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2703967616
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.231737931
Short name T590
Test name
Test status
Simulation time 619069465 ps
CPU time 7.47 seconds
Started Aug 07 05:28:22 PM PDT 24
Finished Aug 07 05:28:30 PM PDT 24
Peak memory 196820 kb
Host smart-d1854dda-0a3f-4c11-80b6-a19cb4211d54
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231737931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stres
s.231737931
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.3600247168
Short name T181
Test name
Test status
Simulation time 272602539 ps
CPU time 0.96 seconds
Started Aug 07 05:28:21 PM PDT 24
Finished Aug 07 05:28:22 PM PDT 24
Peak memory 198368 kb
Host smart-e1a6a4cc-bc85-414b-bf4d-44c395265ea4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600247168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3600247168
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3862983555
Short name T408
Test name
Test status
Simulation time 234493471 ps
CPU time 0.99 seconds
Started Aug 07 05:28:22 PM PDT 24
Finished Aug 07 05:28:23 PM PDT 24
Peak memory 196744 kb
Host smart-cd0b99f6-e85e-4b5f-878a-6284b427dbda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862983555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3862983555
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3993035946
Short name T98
Test name
Test status
Simulation time 46975819 ps
CPU time 1.94 seconds
Started Aug 07 05:28:22 PM PDT 24
Finished Aug 07 05:28:24 PM PDT 24
Peak memory 198508 kb
Host smart-d25097f3-ef7d-47aa-95d9-1966ef8fe241
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993035946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3993035946
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1408732120
Short name T486
Test name
Test status
Simulation time 115713216 ps
CPU time 2.33 seconds
Started Aug 07 05:28:18 PM PDT 24
Finished Aug 07 05:28:20 PM PDT 24
Peak memory 196376 kb
Host smart-3b726bf3-7e38-41e6-80f7-43fab4eea14d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408732120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1408732120
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3585453289
Short name T145
Test name
Test status
Simulation time 116025740 ps
CPU time 0.89 seconds
Started Aug 07 05:28:23 PM PDT 24
Finished Aug 07 05:28:24 PM PDT 24
Peak memory 195952 kb
Host smart-d3c17b8a-5c06-477b-b383-ab48c890fed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585453289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3585453289
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.4275122889
Short name T589
Test name
Test status
Simulation time 60598478 ps
CPU time 1.24 seconds
Started Aug 07 05:28:21 PM PDT 24
Finished Aug 07 05:28:22 PM PDT 24
Peak memory 197596 kb
Host smart-abaca95a-8a6e-4e41-b528-9078e6883286
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275122889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.4275122889
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.989012642
Short name T341
Test name
Test status
Simulation time 426513486 ps
CPU time 2.26 seconds
Started Aug 07 05:28:22 PM PDT 24
Finished Aug 07 05:28:25 PM PDT 24
Peak memory 198584 kb
Host smart-03556de8-26f0-4977-9819-90d04a687951
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989012642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.989012642
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1197478144
Short name T351
Test name
Test status
Simulation time 211704378 ps
CPU time 1.01 seconds
Started Aug 07 05:28:16 PM PDT 24
Finished Aug 07 05:28:17 PM PDT 24
Peak memory 197096 kb
Host smart-4d4fe045-0b97-4412-ab6f-b1cee644cf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197478144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1197478144
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2265381017
Short name T376
Test name
Test status
Simulation time 127875846 ps
CPU time 1.14 seconds
Started Aug 07 05:28:21 PM PDT 24
Finished Aug 07 05:28:23 PM PDT 24
Peak memory 196836 kb
Host smart-33c61c35-085c-4edf-ae7f-d9b2b634fef7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265381017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2265381017
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1193811112
Short name T625
Test name
Test status
Simulation time 4776289640 ps
CPU time 120.85 seconds
Started Aug 07 05:28:21 PM PDT 24
Finished Aug 07 05:30:22 PM PDT 24
Peak memory 198752 kb
Host smart-05170267-2f43-45d6-943e-fea68dc149e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193811112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1193811112
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.2158504453
Short name T455
Test name
Test status
Simulation time 37350653916 ps
CPU time 674.68 seconds
Started Aug 07 05:28:23 PM PDT 24
Finished Aug 07 05:39:38 PM PDT 24
Peak memory 198936 kb
Host smart-b06b61df-e1a9-4b8e-a874-0ffb11d8b881
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2158504453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.2158504453
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2536303081
Short name T200
Test name
Test status
Simulation time 105490545 ps
CPU time 0.57 seconds
Started Aug 07 05:28:28 PM PDT 24
Finished Aug 07 05:28:28 PM PDT 24
Peak memory 194476 kb
Host smart-46fd75ef-8344-43c0-90bf-710d75b6fefc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536303081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2536303081
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2671934091
Short name T237
Test name
Test status
Simulation time 27418416 ps
CPU time 0.83 seconds
Started Aug 07 05:28:26 PM PDT 24
Finished Aug 07 05:28:27 PM PDT 24
Peak memory 195936 kb
Host smart-87653209-4974-4f8b-88fd-e1c9a8bd6aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671934091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2671934091
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.548242508
Short name T59
Test name
Test status
Simulation time 882319258 ps
CPU time 11.41 seconds
Started Aug 07 05:28:28 PM PDT 24
Finished Aug 07 05:28:39 PM PDT 24
Peak memory 196816 kb
Host smart-aa054764-1fb7-4ced-9ebb-2ba23b256028
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548242508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.548242508
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.374867964
Short name T20
Test name
Test status
Simulation time 303310125 ps
CPU time 0.87 seconds
Started Aug 07 05:28:27 PM PDT 24
Finished Aug 07 05:28:28 PM PDT 24
Peak memory 197660 kb
Host smart-cbea90b5-0873-4074-93b5-cfe89dc1528f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374867964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.374867964
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2250637703
Short name T531
Test name
Test status
Simulation time 79553941 ps
CPU time 0.7 seconds
Started Aug 07 05:28:27 PM PDT 24
Finished Aug 07 05:28:28 PM PDT 24
Peak memory 195472 kb
Host smart-81b8315d-9522-4218-8d74-dacba60d0ebf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250637703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2250637703
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.4133133944
Short name T690
Test name
Test status
Simulation time 96108504 ps
CPU time 3.43 seconds
Started Aug 07 05:28:29 PM PDT 24
Finished Aug 07 05:28:33 PM PDT 24
Peak memory 198548 kb
Host smart-7bd597f4-b3a3-4aba-a792-718c09fe43e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133133944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.4133133944
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.4053741162
Short name T637
Test name
Test status
Simulation time 49656354 ps
CPU time 1.26 seconds
Started Aug 07 05:28:27 PM PDT 24
Finished Aug 07 05:28:28 PM PDT 24
Peak memory 197188 kb
Host smart-e00e1112-45e1-42a3-a796-9e3337f8f4cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053741162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.4053741162
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.676079345
Short name T164
Test name
Test status
Simulation time 27984582 ps
CPU time 1.02 seconds
Started Aug 07 05:28:22 PM PDT 24
Finished Aug 07 05:28:23 PM PDT 24
Peak memory 196968 kb
Host smart-700677d8-30e8-47b1-bd92-cf4b3740cd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676079345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.676079345
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1790884231
Short name T342
Test name
Test status
Simulation time 281596283 ps
CPU time 0.99 seconds
Started Aug 07 05:28:21 PM PDT 24
Finished Aug 07 05:28:22 PM PDT 24
Peak memory 196640 kb
Host smart-28f5e511-8eec-456e-a217-045c92bf0d80
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790884231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1790884231
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.718235832
Short name T642
Test name
Test status
Simulation time 704843394 ps
CPU time 5.45 seconds
Started Aug 07 05:28:26 PM PDT 24
Finished Aug 07 05:28:32 PM PDT 24
Peak memory 198512 kb
Host smart-ddec2a07-8d4e-4860-894b-25e91d9fa83b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718235832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.718235832
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3598416503
Short name T251
Test name
Test status
Simulation time 32172127 ps
CPU time 0.92 seconds
Started Aug 07 05:28:20 PM PDT 24
Finished Aug 07 05:28:21 PM PDT 24
Peak memory 196724 kb
Host smart-badfacd3-5dfe-45f6-86e4-65ec7365a5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598416503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3598416503
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2547790309
Short name T385
Test name
Test status
Simulation time 453008350 ps
CPU time 1.13 seconds
Started Aug 07 05:28:26 PM PDT 24
Finished Aug 07 05:28:27 PM PDT 24
Peak memory 196996 kb
Host smart-e6f65d95-0f71-4b60-83ee-fc29f9d9c934
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547790309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2547790309
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3849008064
Short name T275
Test name
Test status
Simulation time 63780393109 ps
CPU time 180.48 seconds
Started Aug 07 05:28:27 PM PDT 24
Finished Aug 07 05:31:27 PM PDT 24
Peak memory 198704 kb
Host smart-2a6de35d-bb8b-4c7b-a22c-e22693735ff1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849008064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3849008064
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2426467062
Short name T585
Test name
Test status
Simulation time 14464026 ps
CPU time 0.58 seconds
Started Aug 07 05:28:32 PM PDT 24
Finished Aug 07 05:28:32 PM PDT 24
Peak memory 195212 kb
Host smart-9911a023-49d5-4995-ad8a-e57bb0b3ede6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426467062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2426467062
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3497194542
Short name T627
Test name
Test status
Simulation time 164928205 ps
CPU time 0.9 seconds
Started Aug 07 05:28:28 PM PDT 24
Finished Aug 07 05:28:29 PM PDT 24
Peak memory 197208 kb
Host smart-0bd9d881-493b-4b51-ae16-0de15e20a1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497194542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3497194542
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.315058054
Short name T316
Test name
Test status
Simulation time 727279630 ps
CPU time 23.26 seconds
Started Aug 07 05:28:37 PM PDT 24
Finished Aug 07 05:29:00 PM PDT 24
Peak memory 198624 kb
Host smart-a3679b8b-d30b-4107-b9ba-2e6e0daeb094
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315058054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.315058054
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1827629359
Short name T632
Test name
Test status
Simulation time 595960928 ps
CPU time 0.92 seconds
Started Aug 07 05:28:35 PM PDT 24
Finished Aug 07 05:28:36 PM PDT 24
Peak memory 197620 kb
Host smart-a181dd3c-c205-4125-b0ef-46ce5f02740b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827629359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1827629359
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2976635153
Short name T131
Test name
Test status
Simulation time 107146626 ps
CPU time 0.79 seconds
Started Aug 07 05:28:25 PM PDT 24
Finished Aug 07 05:28:26 PM PDT 24
Peak memory 196092 kb
Host smart-f2709d46-cb5f-42a6-8f15-7c2d0b215550
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976635153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2976635153
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1934171835
Short name T375
Test name
Test status
Simulation time 201957599 ps
CPU time 2.09 seconds
Started Aug 07 05:28:35 PM PDT 24
Finished Aug 07 05:28:38 PM PDT 24
Peak memory 197084 kb
Host smart-358d004f-720c-4e0c-8113-ab4f22c39763
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934171835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1934171835
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.877119599
Short name T507
Test name
Test status
Simulation time 294531335 ps
CPU time 2.15 seconds
Started Aug 07 05:28:27 PM PDT 24
Finished Aug 07 05:28:30 PM PDT 24
Peak memory 196424 kb
Host smart-933cb2c0-f367-46e1-a6a5-71254fac8bd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877119599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
877119599
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.54411944
Short name T189
Test name
Test status
Simulation time 58256322 ps
CPU time 0.73 seconds
Started Aug 07 05:28:29 PM PDT 24
Finished Aug 07 05:28:30 PM PDT 24
Peak memory 195948 kb
Host smart-8e8807dd-c0ce-48b7-b315-449573256968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54411944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.54411944
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2609108785
Short name T355
Test name
Test status
Simulation time 259249282 ps
CPU time 1.18 seconds
Started Aug 07 05:28:27 PM PDT 24
Finished Aug 07 05:28:28 PM PDT 24
Peak memory 197148 kb
Host smart-a4465e3b-42f2-4b24-b9a8-7172a4a8d12a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609108785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2609108785
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2149449952
Short name T400
Test name
Test status
Simulation time 87349121 ps
CPU time 3.91 seconds
Started Aug 07 05:28:33 PM PDT 24
Finished Aug 07 05:28:37 PM PDT 24
Peak memory 198552 kb
Host smart-f2e295ab-3e39-4139-bc80-c9e02678141d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149449952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2149449952
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2646193037
Short name T555
Test name
Test status
Simulation time 48353776 ps
CPU time 1.22 seconds
Started Aug 07 05:28:28 PM PDT 24
Finished Aug 07 05:28:29 PM PDT 24
Peak memory 196400 kb
Host smart-42243e86-ad10-46b9-b6ea-04e629b91641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646193037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2646193037
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.29578544
Short name T175
Test name
Test status
Simulation time 93932677 ps
CPU time 1.21 seconds
Started Aug 07 05:28:28 PM PDT 24
Finished Aug 07 05:28:29 PM PDT 24
Peak memory 196812 kb
Host smart-54684ded-1e1c-4acd-ae12-ed4cd6c436c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29578544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.29578544
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2630165658
Short name T240
Test name
Test status
Simulation time 33737960818 ps
CPU time 104.68 seconds
Started Aug 07 05:28:35 PM PDT 24
Finished Aug 07 05:30:19 PM PDT 24
Peak memory 198740 kb
Host smart-73d2db13-703f-4b3a-9206-ced3f57fc4c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630165658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2630165658
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1125234766
Short name T657
Test name
Test status
Simulation time 23364929 ps
CPU time 0.6 seconds
Started Aug 07 05:28:42 PM PDT 24
Finished Aug 07 05:28:43 PM PDT 24
Peak memory 194376 kb
Host smart-e69520ca-b4e2-4b70-94f8-fcbe2d2809f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125234766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1125234766
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1835567700
Short name T551
Test name
Test status
Simulation time 16059359 ps
CPU time 0.66 seconds
Started Aug 07 05:28:34 PM PDT 24
Finished Aug 07 05:28:34 PM PDT 24
Peak memory 194660 kb
Host smart-e07d2f78-4d36-4e88-ae89-5618ed276106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835567700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1835567700
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.573860930
Short name T378
Test name
Test status
Simulation time 314687201 ps
CPU time 4.05 seconds
Started Aug 07 05:28:40 PM PDT 24
Finished Aug 07 05:28:44 PM PDT 24
Peak memory 196088 kb
Host smart-7f779348-abad-4b61-a805-0f80d5d36436
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573860930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stres
s.573860930
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.2451730474
Short name T577
Test name
Test status
Simulation time 22487075 ps
CPU time 0.65 seconds
Started Aug 07 05:28:43 PM PDT 24
Finished Aug 07 05:28:44 PM PDT 24
Peak memory 194828 kb
Host smart-24a21336-dc8d-424d-a6bb-0742ecd442a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451730474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.2451730474
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1635343803
Short name T647
Test name
Test status
Simulation time 118731667 ps
CPU time 1 seconds
Started Aug 07 05:28:34 PM PDT 24
Finished Aug 07 05:28:36 PM PDT 24
Peak memory 196600 kb
Host smart-5cd60075-9dca-4e9c-8901-11bf743b784d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635343803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1635343803
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3351531339
Short name T436
Test name
Test status
Simulation time 61686515 ps
CPU time 2.26 seconds
Started Aug 07 05:28:37 PM PDT 24
Finished Aug 07 05:28:40 PM PDT 24
Peak memory 198636 kb
Host smart-e0acfc3e-a3c7-4847-9a61-ad2b20c3e64f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351531339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3351531339
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3579806326
Short name T567
Test name
Test status
Simulation time 68946338 ps
CPU time 1.47 seconds
Started Aug 07 05:28:35 PM PDT 24
Finished Aug 07 05:28:37 PM PDT 24
Peak memory 196592 kb
Host smart-d677664f-5412-4623-b07b-9c56859c141a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579806326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3579806326
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1013656170
Short name T356
Test name
Test status
Simulation time 24009803 ps
CPU time 0.89 seconds
Started Aug 07 05:28:34 PM PDT 24
Finished Aug 07 05:28:35 PM PDT 24
Peak memory 196540 kb
Host smart-8c114b22-aa63-4de5-ad11-a85f91951cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013656170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1013656170
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2236802618
Short name T243
Test name
Test status
Simulation time 34386608 ps
CPU time 0.82 seconds
Started Aug 07 05:28:35 PM PDT 24
Finished Aug 07 05:28:36 PM PDT 24
Peak memory 196852 kb
Host smart-3dafe229-3830-4186-9dde-ccf584864047
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236802618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.2236802618
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.4140693818
Short name T102
Test name
Test status
Simulation time 120311656 ps
CPU time 5.71 seconds
Started Aug 07 05:28:41 PM PDT 24
Finished Aug 07 05:28:47 PM PDT 24
Peak memory 198564 kb
Host smart-a59c2da7-5ac6-44bd-9000-da707fd90722
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140693818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.4140693818
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.4155790098
Short name T492
Test name
Test status
Simulation time 75020773 ps
CPU time 1.24 seconds
Started Aug 07 05:28:36 PM PDT 24
Finished Aug 07 05:28:37 PM PDT 24
Peak memory 197396 kb
Host smart-f702a548-d2cc-4417-b63c-bd2f364760ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155790098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.4155790098
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.577822189
Short name T229
Test name
Test status
Simulation time 71844762 ps
CPU time 0.74 seconds
Started Aug 07 05:28:35 PM PDT 24
Finished Aug 07 05:28:36 PM PDT 24
Peak memory 196508 kb
Host smart-77c09b68-9a73-4cec-a18b-57679b40ddb4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577822189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.577822189
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.651481322
Short name T311
Test name
Test status
Simulation time 48557932021 ps
CPU time 103.16 seconds
Started Aug 07 05:28:40 PM PDT 24
Finished Aug 07 05:30:23 PM PDT 24
Peak memory 198728 kb
Host smart-5eb19a72-2104-4fe3-8dde-054b92be9805
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651481322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.651481322
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.4194832389
Short name T435
Test name
Test status
Simulation time 11959297 ps
CPU time 0.57 seconds
Started Aug 07 05:28:45 PM PDT 24
Finished Aug 07 05:28:45 PM PDT 24
Peak memory 194700 kb
Host smart-21b789cc-a055-49ed-89f4-37333feaba89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194832389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.4194832389
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1945615001
Short name T157
Test name
Test status
Simulation time 102258171 ps
CPU time 0.73 seconds
Started Aug 07 05:28:42 PM PDT 24
Finished Aug 07 05:28:43 PM PDT 24
Peak memory 195644 kb
Host smart-c60761c7-cedb-4378-a62d-de8432194a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945615001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1945615001
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.387628141
Short name T611
Test name
Test status
Simulation time 209966803 ps
CPU time 5.39 seconds
Started Aug 07 05:28:43 PM PDT 24
Finished Aug 07 05:28:48 PM PDT 24
Peak memory 197304 kb
Host smart-53c962a5-391a-4fba-a031-9a5f7158d73a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387628141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.387628141
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2700067051
Short name T256
Test name
Test status
Simulation time 83914983 ps
CPU time 0.64 seconds
Started Aug 07 05:28:40 PM PDT 24
Finished Aug 07 05:28:40 PM PDT 24
Peak memory 195132 kb
Host smart-d2737ab8-077d-4b96-a1fb-912a3f4eaf3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700067051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2700067051
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.180938689
Short name T205
Test name
Test status
Simulation time 248264725 ps
CPU time 0.74 seconds
Started Aug 07 05:28:45 PM PDT 24
Finished Aug 07 05:28:45 PM PDT 24
Peak memory 196720 kb
Host smart-6a75abd6-89c3-42f4-a92f-9297d105b3ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180938689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.180938689
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3532086637
Short name T230
Test name
Test status
Simulation time 51796905 ps
CPU time 1.09 seconds
Started Aug 07 05:28:41 PM PDT 24
Finished Aug 07 05:28:43 PM PDT 24
Peak memory 197780 kb
Host smart-ad2948b9-c7d2-4993-9a33-23b940e33822
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532086637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3532086637
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3686135458
Short name T432
Test name
Test status
Simulation time 127625860 ps
CPU time 2.83 seconds
Started Aug 07 05:28:48 PM PDT 24
Finished Aug 07 05:28:51 PM PDT 24
Peak memory 196300 kb
Host smart-be0ce454-d612-4734-9f1e-6848c5f8185e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686135458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3686135458
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3983668019
Short name T246
Test name
Test status
Simulation time 189065363 ps
CPU time 1.3 seconds
Started Aug 07 05:28:39 PM PDT 24
Finished Aug 07 05:28:40 PM PDT 24
Peak memory 198612 kb
Host smart-505ff2e9-4824-4d34-8392-77e4909d67b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983668019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3983668019
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.361317080
Short name T580
Test name
Test status
Simulation time 23594972 ps
CPU time 0.68 seconds
Started Aug 07 05:28:42 PM PDT 24
Finished Aug 07 05:28:43 PM PDT 24
Peak memory 195576 kb
Host smart-9c3c21d1-1ffa-488b-95cc-2d8313f50ffe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361317080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.361317080
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3163645496
Short name T641
Test name
Test status
Simulation time 239086858 ps
CPU time 1.27 seconds
Started Aug 07 05:28:42 PM PDT 24
Finished Aug 07 05:28:43 PM PDT 24
Peak memory 198460 kb
Host smart-910f8af0-b705-477b-b51b-899e7f50f691
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163645496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3163645496
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.34654061
Short name T483
Test name
Test status
Simulation time 23319417 ps
CPU time 0.71 seconds
Started Aug 07 05:28:38 PM PDT 24
Finished Aug 07 05:28:39 PM PDT 24
Peak memory 196276 kb
Host smart-c1b52f00-0b31-4253-9282-439c52820d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34654061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.34654061
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3944842801
Short name T471
Test name
Test status
Simulation time 260156963 ps
CPU time 1.36 seconds
Started Aug 07 05:28:43 PM PDT 24
Finished Aug 07 05:28:44 PM PDT 24
Peak memory 197356 kb
Host smart-e9266d95-9a8b-495f-859c-42eb5894eda4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944842801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3944842801
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.639080935
Short name T101
Test name
Test status
Simulation time 35132754243 ps
CPU time 211.87 seconds
Started Aug 07 05:28:45 PM PDT 24
Finished Aug 07 05:32:17 PM PDT 24
Peak memory 198700 kb
Host smart-206fc5b0-6f3b-4e0a-816c-2f720dec3ece
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639080935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.639080935
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.517162093
Short name T288
Test name
Test status
Simulation time 15006708 ps
CPU time 0.55 seconds
Started Aug 07 05:28:47 PM PDT 24
Finished Aug 07 05:28:48 PM PDT 24
Peak memory 194448 kb
Host smart-a995cc32-b2b9-4040-a817-4bbccd42ed45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517162093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.517162093
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1642355661
Short name T411
Test name
Test status
Simulation time 25344901 ps
CPU time 0.7 seconds
Started Aug 07 05:28:51 PM PDT 24
Finished Aug 07 05:28:52 PM PDT 24
Peak memory 195680 kb
Host smart-9cdbe1db-345a-4318-87a0-9fbe2df315ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642355661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1642355661
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2365116378
Short name T213
Test name
Test status
Simulation time 1783403022 ps
CPU time 22.79 seconds
Started Aug 07 05:28:48 PM PDT 24
Finished Aug 07 05:29:11 PM PDT 24
Peak memory 198556 kb
Host smart-35415a51-7c65-4ca6-8232-6755d6042b83
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365116378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2365116378
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1561813575
Short name T558
Test name
Test status
Simulation time 450862643 ps
CPU time 0.9 seconds
Started Aug 07 05:28:48 PM PDT 24
Finished Aug 07 05:28:49 PM PDT 24
Peak memory 197584 kb
Host smart-79ff839c-d412-4360-b9d1-081cba0de5bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561813575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1561813575
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.491808123
Short name T126
Test name
Test status
Simulation time 155647328 ps
CPU time 0.85 seconds
Started Aug 07 05:28:46 PM PDT 24
Finished Aug 07 05:28:47 PM PDT 24
Peak memory 197240 kb
Host smart-dd0e7693-8c39-41e1-9c92-a0b65376a586
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491808123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.491808123
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2003501214
Short name T254
Test name
Test status
Simulation time 657755083 ps
CPU time 2.24 seconds
Started Aug 07 05:28:48 PM PDT 24
Finished Aug 07 05:28:50 PM PDT 24
Peak memory 198464 kb
Host smart-af203d3f-8cb1-4146-989f-0f0a47d65f39
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003501214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2003501214
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1694725196
Short name T389
Test name
Test status
Simulation time 159408566 ps
CPU time 3.34 seconds
Started Aug 07 05:28:47 PM PDT 24
Finished Aug 07 05:28:50 PM PDT 24
Peak memory 198612 kb
Host smart-ab04d042-cce7-4679-a724-8c064d461ab6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694725196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1694725196
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.3190006473
Short name T701
Test name
Test status
Simulation time 50583719 ps
CPU time 0.68 seconds
Started Aug 07 05:28:48 PM PDT 24
Finished Aug 07 05:28:49 PM PDT 24
Peak memory 195792 kb
Host smart-6111e2f6-eb3a-4b3a-beb3-b144407116f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190006473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.3190006473
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.113901689
Short name T573
Test name
Test status
Simulation time 1051341590 ps
CPU time 1.26 seconds
Started Aug 07 05:28:45 PM PDT 24
Finished Aug 07 05:28:46 PM PDT 24
Peak memory 197648 kb
Host smart-89f584f6-9b83-419d-8caa-329b903cbf0c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113901689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.113901689
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1517256174
Short name T63
Test name
Test status
Simulation time 363917436 ps
CPU time 5.83 seconds
Started Aug 07 05:28:48 PM PDT 24
Finished Aug 07 05:28:54 PM PDT 24
Peak memory 198544 kb
Host smart-0c1cc91b-05b3-4593-8edd-ceb169bd683c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517256174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1517256174
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.108358635
Short name T263
Test name
Test status
Simulation time 40643409 ps
CPU time 0.74 seconds
Started Aug 07 05:28:44 PM PDT 24
Finished Aug 07 05:28:45 PM PDT 24
Peak memory 195664 kb
Host smart-e0aa084c-27a3-4608-9f7e-1c6e8a11e663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108358635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.108358635
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2641153692
Short name T321
Test name
Test status
Simulation time 106782653 ps
CPU time 0.8 seconds
Started Aug 07 05:28:47 PM PDT 24
Finished Aug 07 05:28:48 PM PDT 24
Peak memory 195776 kb
Host smart-fc781c8f-e270-4b59-a348-33011d58e55c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641153692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2641153692
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3670070752
Short name T575
Test name
Test status
Simulation time 25536143831 ps
CPU time 67 seconds
Started Aug 07 05:28:47 PM PDT 24
Finished Aug 07 05:29:55 PM PDT 24
Peak memory 198736 kb
Host smart-ad416135-67f7-4886-b65a-696dd6134d56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670070752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3670070752
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3772325952
Short name T40
Test name
Test status
Simulation time 19495149 ps
CPU time 0.58 seconds
Started Aug 07 05:28:50 PM PDT 24
Finished Aug 07 05:28:51 PM PDT 24
Peak memory 194484 kb
Host smart-69298e37-c941-4c2b-9d6a-0d17726ca8a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772325952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3772325952
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3442924681
Short name T672
Test name
Test status
Simulation time 112925396 ps
CPU time 0.89 seconds
Started Aug 07 05:28:51 PM PDT 24
Finished Aug 07 05:28:52 PM PDT 24
Peak memory 196440 kb
Host smart-fb0f0fcf-4914-486b-85ff-33555f7e2c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442924681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3442924681
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.10793930
Short name T579
Test name
Test status
Simulation time 1460650715 ps
CPU time 10.62 seconds
Started Aug 07 05:28:46 PM PDT 24
Finished Aug 07 05:28:57 PM PDT 24
Peak memory 197452 kb
Host smart-2977ca59-ae8a-48c7-b282-e71964a3d071
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10793930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stress
.10793930
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3193514169
Short name T479
Test name
Test status
Simulation time 29607651 ps
CPU time 0.71 seconds
Started Aug 07 05:28:50 PM PDT 24
Finished Aug 07 05:28:51 PM PDT 24
Peak memory 195232 kb
Host smart-5af0e805-52aa-4f94-9bbd-636a7bf1f389
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193514169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3193514169
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3562258987
Short name T721
Test name
Test status
Simulation time 282075321 ps
CPU time 1.21 seconds
Started Aug 07 05:28:50 PM PDT 24
Finished Aug 07 05:28:51 PM PDT 24
Peak memory 196596 kb
Host smart-d629f8db-4ffd-472c-834c-5afdb8bb85a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562258987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3562258987
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2929694057
Short name T704
Test name
Test status
Simulation time 53119703 ps
CPU time 2.24 seconds
Started Aug 07 05:28:52 PM PDT 24
Finished Aug 07 05:28:54 PM PDT 24
Peak memory 198596 kb
Host smart-0bf7d27e-a281-4450-a03d-34df5aa19ba8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929694057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2929694057
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3211414089
Short name T607
Test name
Test status
Simulation time 563209491 ps
CPU time 3.11 seconds
Started Aug 07 05:28:50 PM PDT 24
Finished Aug 07 05:28:53 PM PDT 24
Peak memory 197632 kb
Host smart-5152e420-f8fe-44a2-8a26-83d055c2a8f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211414089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3211414089
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3605863571
Short name T396
Test name
Test status
Simulation time 34432585 ps
CPU time 1.2 seconds
Started Aug 07 05:28:47 PM PDT 24
Finished Aug 07 05:28:49 PM PDT 24
Peak memory 198616 kb
Host smart-dfdc0d51-67f6-485f-b09b-ea9c3e3ef8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605863571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3605863571
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.907173554
Short name T106
Test name
Test status
Simulation time 135319969 ps
CPU time 0.83 seconds
Started Aug 07 05:28:44 PM PDT 24
Finished Aug 07 05:28:45 PM PDT 24
Peak memory 197160 kb
Host smart-d3658226-e84a-491b-bfcf-29febf79d730
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907173554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.907173554
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2218209952
Short name T538
Test name
Test status
Simulation time 126001255 ps
CPU time 1.46 seconds
Started Aug 07 05:28:48 PM PDT 24
Finished Aug 07 05:28:50 PM PDT 24
Peak memory 198452 kb
Host smart-8a563453-d41a-4fef-9144-44213a2432d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218209952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2218209952
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2527481382
Short name T422
Test name
Test status
Simulation time 206292113 ps
CPU time 0.99 seconds
Started Aug 07 05:28:47 PM PDT 24
Finished Aug 07 05:28:48 PM PDT 24
Peak memory 196968 kb
Host smart-6191e021-9193-498c-bd2a-ba4151b616f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527481382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2527481382
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3300753388
Short name T115
Test name
Test status
Simulation time 51448103 ps
CPU time 1.02 seconds
Started Aug 07 05:28:45 PM PDT 24
Finished Aug 07 05:28:46 PM PDT 24
Peak memory 196956 kb
Host smart-ddfc5053-66ec-4059-84ae-e0ccf662cf05
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300753388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3300753388
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2951719914
Short name T454
Test name
Test status
Simulation time 9157238616 ps
CPU time 55.08 seconds
Started Aug 07 05:28:48 PM PDT 24
Finished Aug 07 05:29:43 PM PDT 24
Peak memory 198712 kb
Host smart-2f01e9bc-c1c0-4ae3-b114-974a439d8bb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951719914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2951719914
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.831342418
Short name T566
Test name
Test status
Simulation time 66486928888 ps
CPU time 448.25 seconds
Started Aug 07 05:28:45 PM PDT 24
Finished Aug 07 05:36:14 PM PDT 24
Peak memory 198852 kb
Host smart-84520509-0262-4d72-aa98-32653a039024
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=831342418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.831342418
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2351335724
Short name T238
Test name
Test status
Simulation time 48601235 ps
CPU time 0.56 seconds
Started Aug 07 05:28:53 PM PDT 24
Finished Aug 07 05:28:54 PM PDT 24
Peak memory 194372 kb
Host smart-1c14f064-f956-40ba-b9c4-830965d8c5e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351335724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2351335724
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3909546262
Short name T550
Test name
Test status
Simulation time 103241148 ps
CPU time 0.86 seconds
Started Aug 07 05:28:50 PM PDT 24
Finished Aug 07 05:28:51 PM PDT 24
Peak memory 195664 kb
Host smart-d8a8b63b-e36f-4315-acc4-11813834d4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909546262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3909546262
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.4072450548
Short name T563
Test name
Test status
Simulation time 2466413636 ps
CPU time 17.57 seconds
Started Aug 07 05:28:50 PM PDT 24
Finished Aug 07 05:29:07 PM PDT 24
Peak memory 196432 kb
Host smart-01b49e45-48ae-48f9-a110-3bc1ccdfc9de
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072450548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.4072450548
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2800140823
Short name T414
Test name
Test status
Simulation time 92176867 ps
CPU time 0.77 seconds
Started Aug 07 05:28:54 PM PDT 24
Finished Aug 07 05:28:55 PM PDT 24
Peak memory 197056 kb
Host smart-74cae5c7-f7db-434c-aeb7-351f6abec012
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800140823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2800140823
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.331077677
Short name T405
Test name
Test status
Simulation time 339236878 ps
CPU time 1.39 seconds
Started Aug 07 05:28:50 PM PDT 24
Finished Aug 07 05:28:52 PM PDT 24
Peak memory 198564 kb
Host smart-949fa23a-94f9-4f8e-a2fd-5f0518525f19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331077677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.331077677
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3222594373
Short name T595
Test name
Test status
Simulation time 79226163 ps
CPU time 1.7 seconds
Started Aug 07 05:28:57 PM PDT 24
Finished Aug 07 05:28:58 PM PDT 24
Peak memory 198744 kb
Host smart-16d1a10b-5b5a-4035-aa94-e6a1b9faff6c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222594373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3222594373
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.452711929
Short name T195
Test name
Test status
Simulation time 300164652 ps
CPU time 1.78 seconds
Started Aug 07 05:28:53 PM PDT 24
Finished Aug 07 05:28:55 PM PDT 24
Peak memory 196352 kb
Host smart-6039626b-0f3e-4f89-ab49-f0f6d6e0f940
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452711929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
452711929
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.2816274827
Short name T103
Test name
Test status
Simulation time 32567924 ps
CPU time 1.1 seconds
Started Aug 07 05:28:55 PM PDT 24
Finished Aug 07 05:28:57 PM PDT 24
Peak memory 196356 kb
Host smart-a526323d-2506-402a-9430-e70039b22434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816274827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.2816274827
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.128150395
Short name T269
Test name
Test status
Simulation time 262695313 ps
CPU time 0.92 seconds
Started Aug 07 05:28:50 PM PDT 24
Finished Aug 07 05:28:52 PM PDT 24
Peak memory 196540 kb
Host smart-9fdc7dbe-6270-40e9-aa90-91e50ddc4831
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128150395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.128150395
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3135114615
Short name T448
Test name
Test status
Simulation time 398153212 ps
CPU time 4.62 seconds
Started Aug 07 05:28:53 PM PDT 24
Finished Aug 07 05:28:58 PM PDT 24
Peak memory 198268 kb
Host smart-26e1245c-b9d0-4df4-b040-0661a7a7aa49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135114615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3135114615
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.780894224
Short name T202
Test name
Test status
Simulation time 235506700 ps
CPU time 0.99 seconds
Started Aug 07 05:28:53 PM PDT 24
Finished Aug 07 05:28:54 PM PDT 24
Peak memory 196876 kb
Host smart-8767f9a2-25e4-4082-8ae9-aa0a8b34f9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780894224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.780894224
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.259450930
Short name T659
Test name
Test status
Simulation time 407848302 ps
CPU time 0.86 seconds
Started Aug 07 05:28:52 PM PDT 24
Finished Aug 07 05:28:53 PM PDT 24
Peak memory 196876 kb
Host smart-df9c0a19-d652-468a-9dce-cd1432d4b6a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259450930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.259450930
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3732590785
Short name T116
Test name
Test status
Simulation time 2263304413 ps
CPU time 30.21 seconds
Started Aug 07 05:28:52 PM PDT 24
Finished Aug 07 05:29:22 PM PDT 24
Peak memory 198716 kb
Host smart-92cb0ace-72a2-4cdf-be49-f0c32074d9a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732590785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3732590785
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.2223999500
Short name T33
Test name
Test status
Simulation time 258147912848 ps
CPU time 1463.53 seconds
Started Aug 07 05:28:57 PM PDT 24
Finished Aug 07 05:53:20 PM PDT 24
Peak memory 198892 kb
Host smart-4acd1b01-933d-4f1b-84f7-1307c48dfb46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2223999500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.2223999500
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3078580802
Short name T231
Test name
Test status
Simulation time 12993714 ps
CPU time 0.58 seconds
Started Aug 07 05:28:58 PM PDT 24
Finished Aug 07 05:28:59 PM PDT 24
Peak memory 194420 kb
Host smart-39ac2e0f-db9c-4b88-8fb7-d6811eefdff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078580802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3078580802
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.75076984
Short name T270
Test name
Test status
Simulation time 154865205 ps
CPU time 0.8 seconds
Started Aug 07 05:28:53 PM PDT 24
Finished Aug 07 05:28:54 PM PDT 24
Peak memory 196448 kb
Host smart-d3a7f3b5-e825-49b8-90c8-bd147483ce2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75076984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.75076984
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.1266100135
Short name T17
Test name
Test status
Simulation time 4425459828 ps
CPU time 27.35 seconds
Started Aug 07 05:28:53 PM PDT 24
Finished Aug 07 05:29:21 PM PDT 24
Peak memory 197512 kb
Host smart-b4edfd19-ed99-45b0-aacd-970dda32087d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266100135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.1266100135
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1611630956
Short name T497
Test name
Test status
Simulation time 362648422 ps
CPU time 0.94 seconds
Started Aug 07 05:29:02 PM PDT 24
Finished Aug 07 05:29:03 PM PDT 24
Peak memory 197076 kb
Host smart-6f19b5a2-dfe1-4030-835f-eac53d604cfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611630956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1611630956
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2715663162
Short name T104
Test name
Test status
Simulation time 357353173 ps
CPU time 1.29 seconds
Started Aug 07 05:28:53 PM PDT 24
Finished Aug 07 05:28:54 PM PDT 24
Peak memory 196396 kb
Host smart-731de3fe-18c6-4095-abe3-51cebb01ead9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715663162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2715663162
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.640375846
Short name T500
Test name
Test status
Simulation time 216920389 ps
CPU time 2.09 seconds
Started Aug 07 05:28:55 PM PDT 24
Finished Aug 07 05:28:57 PM PDT 24
Peak memory 198596 kb
Host smart-717e7eda-9fe8-43e3-ac2e-5f8f7ee6804a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640375846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.640375846
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2222970347
Short name T482
Test name
Test status
Simulation time 61445085 ps
CPU time 0.88 seconds
Started Aug 07 05:28:54 PM PDT 24
Finished Aug 07 05:28:55 PM PDT 24
Peak memory 196664 kb
Host smart-9bf42539-415b-415a-8640-65f21b050fe7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222970347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2222970347
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.4031884120
Short name T18
Test name
Test status
Simulation time 344590544 ps
CPU time 0.8 seconds
Started Aug 07 05:28:51 PM PDT 24
Finished Aug 07 05:28:52 PM PDT 24
Peak memory 196980 kb
Host smart-452ee4f2-15e4-421d-b978-cce3bc6b14e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031884120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.4031884120
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3702405741
Short name T204
Test name
Test status
Simulation time 67276756 ps
CPU time 0.72 seconds
Started Aug 07 05:28:53 PM PDT 24
Finished Aug 07 05:28:54 PM PDT 24
Peak memory 196000 kb
Host smart-e15a7581-a499-4853-b086-e9a49960e462
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702405741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3702405741
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.305231271
Short name T382
Test name
Test status
Simulation time 112513985 ps
CPU time 5.25 seconds
Started Aug 07 05:28:52 PM PDT 24
Finished Aug 07 05:28:58 PM PDT 24
Peak memory 198556 kb
Host smart-644dbc16-6deb-4f7e-8e3b-cf9c82f87a07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305231271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ran
dom_long_reg_writes_reg_reads.305231271
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3727203931
Short name T12
Test name
Test status
Simulation time 36705754 ps
CPU time 0.93 seconds
Started Aug 07 05:28:56 PM PDT 24
Finished Aug 07 05:28:57 PM PDT 24
Peak memory 197836 kb
Host smart-a741e4eb-30ba-4e5c-98d4-78b715e46948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727203931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3727203931
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.120455819
Short name T353
Test name
Test status
Simulation time 191378070 ps
CPU time 0.82 seconds
Started Aug 07 05:28:53 PM PDT 24
Finished Aug 07 05:28:53 PM PDT 24
Peak memory 195968 kb
Host smart-0eef9896-1bcf-4bdb-b349-112b24f13e6f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120455819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.120455819
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.3842446623
Short name T199
Test name
Test status
Simulation time 35396667747 ps
CPU time 169.22 seconds
Started Aug 07 05:29:01 PM PDT 24
Finished Aug 07 05:31:50 PM PDT 24
Peak memory 198740 kb
Host smart-c318d07d-384d-46f2-b524-c8c3faab67e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842446623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3842446623
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.322528415
Short name T53
Test name
Test status
Simulation time 100232831754 ps
CPU time 593.45 seconds
Started Aug 07 05:29:01 PM PDT 24
Finished Aug 07 05:38:55 PM PDT 24
Peak memory 198900 kb
Host smart-98d3574b-b030-49de-b9c7-ce4775281dd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=322528415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.322528415
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.4259755917
Short name T420
Test name
Test status
Simulation time 12296795 ps
CPU time 0.55 seconds
Started Aug 07 05:26:59 PM PDT 24
Finished Aug 07 05:26:59 PM PDT 24
Peak memory 194444 kb
Host smart-942cd95a-d457-4604-a69e-a1dcca664329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259755917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.4259755917
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1909625102
Short name T434
Test name
Test status
Simulation time 64357235 ps
CPU time 0.62 seconds
Started Aug 07 05:26:51 PM PDT 24
Finished Aug 07 05:26:52 PM PDT 24
Peak memory 194492 kb
Host smart-ed12fbbd-bfcf-486c-9de9-85bfc5aef601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909625102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1909625102
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3272066475
Short name T675
Test name
Test status
Simulation time 1014189976 ps
CPU time 21.21 seconds
Started Aug 07 05:26:54 PM PDT 24
Finished Aug 07 05:27:16 PM PDT 24
Peak memory 197476 kb
Host smart-7649a41c-b062-4591-9e6e-6d264ac70f86
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272066475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3272066475
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.4001388532
Short name T1
Test name
Test status
Simulation time 96421643 ps
CPU time 0.81 seconds
Started Aug 07 05:26:53 PM PDT 24
Finished Aug 07 05:26:54 PM PDT 24
Peak memory 197044 kb
Host smart-70b134a8-327b-4abe-8aa5-1d12f1b2fcef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001388532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.4001388532
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2369780071
Short name T645
Test name
Test status
Simulation time 32772812 ps
CPU time 1.02 seconds
Started Aug 07 05:26:53 PM PDT 24
Finished Aug 07 05:26:55 PM PDT 24
Peak memory 197356 kb
Host smart-a27d1b52-ce0e-434d-9ff2-18c841de0ef1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369780071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2369780071
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1603833608
Short name T661
Test name
Test status
Simulation time 210639760 ps
CPU time 2.2 seconds
Started Aug 07 05:26:53 PM PDT 24
Finished Aug 07 05:26:56 PM PDT 24
Peak memory 198552 kb
Host smart-24580b82-c55e-4c09-947c-88a4ec9fcd9b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603833608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1603833608
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2070849220
Short name T410
Test name
Test status
Simulation time 337256865 ps
CPU time 3.39 seconds
Started Aug 07 05:26:55 PM PDT 24
Finished Aug 07 05:26:59 PM PDT 24
Peak memory 198668 kb
Host smart-ee7edfe3-89de-487a-a53f-e7573ae9afd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070849220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2070849220
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1831752023
Short name T431
Test name
Test status
Simulation time 202229724 ps
CPU time 0.97 seconds
Started Aug 07 05:26:44 PM PDT 24
Finished Aug 07 05:26:45 PM PDT 24
Peak memory 196556 kb
Host smart-979541c3-ae76-40bb-b5da-31dc965ed8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831752023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1831752023
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1022545873
Short name T463
Test name
Test status
Simulation time 40286876 ps
CPU time 1 seconds
Started Aug 07 05:26:46 PM PDT 24
Finished Aug 07 05:26:47 PM PDT 24
Peak memory 196444 kb
Host smart-a6001ce3-cb55-4f5e-8037-b07cb5ba1897
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022545873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1022545873
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2434718227
Short name T666
Test name
Test status
Simulation time 868000708 ps
CPU time 3.05 seconds
Started Aug 07 05:26:50 PM PDT 24
Finished Aug 07 05:26:54 PM PDT 24
Peak memory 198596 kb
Host smart-519d7916-e3a8-4524-ad1f-02f2cd0b592c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434718227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2434718227
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.95196203
Short name T39
Test name
Test status
Simulation time 470832296 ps
CPU time 0.99 seconds
Started Aug 07 05:27:02 PM PDT 24
Finished Aug 07 05:27:03 PM PDT 24
Peak memory 215552 kb
Host smart-672cface-74a3-47f4-ba15-9cf25c7511b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95196203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.95196203
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.1083254287
Short name T696
Test name
Test status
Simulation time 34975839 ps
CPU time 1 seconds
Started Aug 07 05:26:47 PM PDT 24
Finished Aug 07 05:26:48 PM PDT 24
Peak memory 196372 kb
Host smart-4ed7daf2-9dfb-484f-9258-586c51d70f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083254287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1083254287
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.518785160
Short name T225
Test name
Test status
Simulation time 102444857 ps
CPU time 1.11 seconds
Started Aug 07 05:26:44 PM PDT 24
Finished Aug 07 05:26:45 PM PDT 24
Peak memory 196364 kb
Host smart-052e4875-643d-433d-a2cc-93ee7603578b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518785160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.518785160
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.4199481150
Short name T685
Test name
Test status
Simulation time 15790644990 ps
CPU time 191.99 seconds
Started Aug 07 05:26:57 PM PDT 24
Finished Aug 07 05:30:09 PM PDT 24
Peak memory 198720 kb
Host smart-55be62d9-410f-4e91-ab73-4768bd717c86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199481150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.4199481150
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3870421482
Short name T208
Test name
Test status
Simulation time 95226678 ps
CPU time 0.56 seconds
Started Aug 07 05:29:00 PM PDT 24
Finished Aug 07 05:29:01 PM PDT 24
Peak memory 195156 kb
Host smart-bac39ee1-52d9-4c7c-86db-1c1839597880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870421482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3870421482
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1309645262
Short name T542
Test name
Test status
Simulation time 43159819 ps
CPU time 0.89 seconds
Started Aug 07 05:28:58 PM PDT 24
Finished Aug 07 05:28:59 PM PDT 24
Peak memory 197832 kb
Host smart-16798405-0d07-4a57-9412-88f78e0803c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309645262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1309645262
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.75752098
Short name T319
Test name
Test status
Simulation time 2522789312 ps
CPU time 21.2 seconds
Started Aug 07 05:29:04 PM PDT 24
Finished Aug 07 05:29:25 PM PDT 24
Peak memory 198628 kb
Host smart-ee167623-02db-4c04-adaa-570e9544d5d6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75752098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stress
.75752098
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.192929254
Short name T16
Test name
Test status
Simulation time 43172456 ps
CPU time 0.79 seconds
Started Aug 07 05:28:59 PM PDT 24
Finished Aug 07 05:29:00 PM PDT 24
Peak memory 196468 kb
Host smart-1f54a27e-f79d-42fa-a4d3-f5fdc91a9807
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192929254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.192929254
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1676828108
Short name T530
Test name
Test status
Simulation time 269380213 ps
CPU time 1.06 seconds
Started Aug 07 05:28:57 PM PDT 24
Finished Aug 07 05:28:58 PM PDT 24
Peak memory 197088 kb
Host smart-70d7d8eb-0fb2-481c-aff4-f024f885bb3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676828108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1676828108
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.4221175874
Short name T239
Test name
Test status
Simulation time 244560016 ps
CPU time 1.59 seconds
Started Aug 07 05:29:01 PM PDT 24
Finished Aug 07 05:29:03 PM PDT 24
Peak memory 197476 kb
Host smart-e4b18ba9-2081-4122-918e-5e3507210a83
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221175874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.4221175874
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2053193311
Short name T545
Test name
Test status
Simulation time 510690114 ps
CPU time 3.41 seconds
Started Aug 07 05:29:01 PM PDT 24
Finished Aug 07 05:29:04 PM PDT 24
Peak memory 198544 kb
Host smart-638bd6fc-c918-4a18-bf2b-830d1a876f09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053193311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2053193311
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3412334890
Short name T720
Test name
Test status
Simulation time 102036101 ps
CPU time 0.97 seconds
Started Aug 07 05:29:00 PM PDT 24
Finished Aug 07 05:29:01 PM PDT 24
Peak memory 196524 kb
Host smart-b18f3e90-d7d0-4a8e-8fe9-0553a48ffada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412334890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3412334890
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1041591955
Short name T250
Test name
Test status
Simulation time 19613521 ps
CPU time 0.81 seconds
Started Aug 07 05:28:59 PM PDT 24
Finished Aug 07 05:29:00 PM PDT 24
Peak memory 197100 kb
Host smart-d1546d34-a621-49f1-81b1-6afbd7f1d806
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041591955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.1041591955
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2834155664
Short name T618
Test name
Test status
Simulation time 316536443 ps
CPU time 1.34 seconds
Started Aug 07 05:28:58 PM PDT 24
Finished Aug 07 05:28:59 PM PDT 24
Peak memory 198568 kb
Host smart-3d7d33ad-dfda-43a9-9c07-0d87896e3885
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834155664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2834155664
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.4043700154
Short name T271
Test name
Test status
Simulation time 74047370 ps
CPU time 1.16 seconds
Started Aug 07 05:29:02 PM PDT 24
Finished Aug 07 05:29:03 PM PDT 24
Peak memory 196160 kb
Host smart-39bb1384-2fcf-455e-803b-b4b04724aa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043700154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.4043700154
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2246784132
Short name T203
Test name
Test status
Simulation time 275848392 ps
CPU time 1.37 seconds
Started Aug 07 05:29:00 PM PDT 24
Finished Aug 07 05:29:01 PM PDT 24
Peak memory 197300 kb
Host smart-5e115df2-807f-4165-a757-c512109ce082
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246784132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2246784132
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2661026760
Short name T506
Test name
Test status
Simulation time 9344081580 ps
CPU time 124.6 seconds
Started Aug 07 05:28:58 PM PDT 24
Finished Aug 07 05:31:03 PM PDT 24
Peak memory 198620 kb
Host smart-27344373-326c-4d19-b093-d684c6fbae70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661026760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2661026760
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2646893605
Short name T119
Test name
Test status
Simulation time 19259067 ps
CPU time 0.54 seconds
Started Aug 07 05:29:05 PM PDT 24
Finished Aug 07 05:29:06 PM PDT 24
Peak memory 194448 kb
Host smart-20c15570-96d8-4701-a879-64565f517957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646893605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2646893605
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2009471186
Short name T211
Test name
Test status
Simulation time 37543750 ps
CPU time 0.57 seconds
Started Aug 07 05:29:05 PM PDT 24
Finished Aug 07 05:29:06 PM PDT 24
Peak memory 194448 kb
Host smart-ea7d5be8-41d6-41a5-92c0-bf0661e8f28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009471186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2009471186
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2249696704
Short name T716
Test name
Test status
Simulation time 506066273 ps
CPU time 16.21 seconds
Started Aug 07 05:29:05 PM PDT 24
Finished Aug 07 05:29:21 PM PDT 24
Peak memory 197404 kb
Host smart-e04197ba-2eec-40ed-a4b3-5baf4ccbb43b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249696704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2249696704
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.4228097539
Short name T218
Test name
Test status
Simulation time 206374207 ps
CPU time 0.86 seconds
Started Aug 07 05:29:06 PM PDT 24
Finished Aug 07 05:29:07 PM PDT 24
Peak memory 197600 kb
Host smart-06271dfc-cf96-43a7-9f07-055c81361cfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228097539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.4228097539
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1068521838
Short name T613
Test name
Test status
Simulation time 142822445 ps
CPU time 0.8 seconds
Started Aug 07 05:29:05 PM PDT 24
Finished Aug 07 05:29:06 PM PDT 24
Peak memory 196612 kb
Host smart-1cf9b602-1e8b-433e-af92-7eedbc570e2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068521838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1068521838
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.4196496817
Short name T477
Test name
Test status
Simulation time 200328070 ps
CPU time 2.01 seconds
Started Aug 07 05:29:05 PM PDT 24
Finished Aug 07 05:29:07 PM PDT 24
Peak memory 198712 kb
Host smart-3c09a083-eac9-4dd8-bdd5-269c82c8d272
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196496817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.4196496817
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.34474719
Short name T494
Test name
Test status
Simulation time 98055482 ps
CPU time 2.07 seconds
Started Aug 07 05:29:06 PM PDT 24
Finished Aug 07 05:29:08 PM PDT 24
Peak memory 197648 kb
Host smart-da541344-e35b-4e4d-ad36-c691bdd2b49e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34474719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.34474719
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1526201894
Short name T562
Test name
Test status
Simulation time 46223050 ps
CPU time 1.07 seconds
Started Aug 07 05:29:01 PM PDT 24
Finished Aug 07 05:29:02 PM PDT 24
Peak memory 197244 kb
Host smart-e98b731a-01f0-4bce-969d-5e8d668508c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526201894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1526201894
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.32095501
Short name T600
Test name
Test status
Simulation time 97376930 ps
CPU time 1.02 seconds
Started Aug 07 05:29:00 PM PDT 24
Finished Aug 07 05:29:01 PM PDT 24
Peak memory 196492 kb
Host smart-bed851af-f78e-4af3-9698-7b8e6833eb96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32095501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup_
pulldown.32095501
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1480843030
Short name T120
Test name
Test status
Simulation time 81613641 ps
CPU time 1.56 seconds
Started Aug 07 05:29:04 PM PDT 24
Finished Aug 07 05:29:06 PM PDT 24
Peak memory 198400 kb
Host smart-49e9d55b-ef41-464b-b6c4-9042c544dbba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480843030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1480843030
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.473604923
Short name T197
Test name
Test status
Simulation time 235569999 ps
CPU time 1.22 seconds
Started Aug 07 05:28:58 PM PDT 24
Finished Aug 07 05:29:00 PM PDT 24
Peak memory 197568 kb
Host smart-dda38bfb-9983-4690-9249-fbe0dcb77a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473604923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.473604923
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3861607110
Short name T172
Test name
Test status
Simulation time 264018701 ps
CPU time 1.15 seconds
Started Aug 07 05:29:01 PM PDT 24
Finished Aug 07 05:29:02 PM PDT 24
Peak memory 196260 kb
Host smart-6f140798-933b-43f6-bfbd-dc21cabc7dac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861607110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3861607110
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.25820638
Short name T327
Test name
Test status
Simulation time 12279744565 ps
CPU time 36.08 seconds
Started Aug 07 05:29:06 PM PDT 24
Finished Aug 07 05:29:42 PM PDT 24
Peak memory 198636 kb
Host smart-8b0fbae1-92cd-4b9f-a8fa-e4e8399a868d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25820638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gp
io_stress_all.25820638
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.3887229889
Short name T706
Test name
Test status
Simulation time 428551026142 ps
CPU time 2303.25 seconds
Started Aug 07 05:29:05 PM PDT 24
Finished Aug 07 06:07:29 PM PDT 24
Peak memory 198900 kb
Host smart-c9c22b39-ef7d-4a5d-ab8d-9ebb049a12aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3887229889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.3887229889
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3630745319
Short name T515
Test name
Test status
Simulation time 37356278 ps
CPU time 0.56 seconds
Started Aug 07 05:29:12 PM PDT 24
Finished Aug 07 05:29:13 PM PDT 24
Peak memory 194668 kb
Host smart-c441b8c5-a1f4-4671-948b-33c5640ef5fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630745319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3630745319
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3242521016
Short name T460
Test name
Test status
Simulation time 26242936 ps
CPU time 0.76 seconds
Started Aug 07 05:29:02 PM PDT 24
Finished Aug 07 05:29:03 PM PDT 24
Peak memory 195928 kb
Host smart-830b6122-d43b-4a9b-a4e9-85dfabfd9d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242521016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3242521016
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3773848383
Short name T513
Test name
Test status
Simulation time 125031731 ps
CPU time 3.93 seconds
Started Aug 07 05:29:06 PM PDT 24
Finished Aug 07 05:29:10 PM PDT 24
Peak memory 196816 kb
Host smart-b117912a-8a16-4fb6-bf4e-b9b752d2f156
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773848383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3773848383
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.951665667
Short name T519
Test name
Test status
Simulation time 103928311 ps
CPU time 0.87 seconds
Started Aug 07 05:29:07 PM PDT 24
Finished Aug 07 05:29:08 PM PDT 24
Peak memory 197552 kb
Host smart-80b9915c-e149-4468-a3df-0903711a131f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951665667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.951665667
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2557472112
Short name T193
Test name
Test status
Simulation time 311857320 ps
CPU time 1.3 seconds
Started Aug 07 05:29:05 PM PDT 24
Finished Aug 07 05:29:06 PM PDT 24
Peak memory 197448 kb
Host smart-40fa83a9-1f61-4ee8-a3d9-8253efb30e77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557472112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2557472112
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1720448774
Short name T404
Test name
Test status
Simulation time 85171229 ps
CPU time 3.27 seconds
Started Aug 07 05:29:05 PM PDT 24
Finished Aug 07 05:29:08 PM PDT 24
Peak memory 198636 kb
Host smart-29ee9353-0541-4e7e-b671-be243a1ac9f8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720448774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1720448774
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2443614700
Short name T100
Test name
Test status
Simulation time 425265679 ps
CPU time 2.25 seconds
Started Aug 07 05:29:05 PM PDT 24
Finished Aug 07 05:29:07 PM PDT 24
Peak memory 197224 kb
Host smart-848a93da-c7ff-4b7a-a0d3-766e0699000a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443614700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2443614700
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.1339152144
Short name T652
Test name
Test status
Simulation time 32420187 ps
CPU time 1.12 seconds
Started Aug 07 05:29:06 PM PDT 24
Finished Aug 07 05:29:07 PM PDT 24
Peak memory 198628 kb
Host smart-0dc2b105-d6fd-4ebd-9871-961d3eb2b8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339152144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.1339152144
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2156258651
Short name T182
Test name
Test status
Simulation time 101683722 ps
CPU time 0.8 seconds
Started Aug 07 05:29:08 PM PDT 24
Finished Aug 07 05:29:09 PM PDT 24
Peak memory 197900 kb
Host smart-fc7e3c76-b6e7-4b37-b0b6-833eb0f089ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156258651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2156258651
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1521948048
Short name T668
Test name
Test status
Simulation time 347629070 ps
CPU time 3.89 seconds
Started Aug 07 05:29:04 PM PDT 24
Finished Aug 07 05:29:08 PM PDT 24
Peak memory 198512 kb
Host smart-b73b3898-e9e7-4def-892f-0b626f307423
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521948048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1521948048
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.3036963571
Short name T114
Test name
Test status
Simulation time 85607485 ps
CPU time 0.97 seconds
Started Aug 07 05:29:04 PM PDT 24
Finished Aug 07 05:29:05 PM PDT 24
Peak memory 196392 kb
Host smart-635b7321-139e-4138-89dc-6f7a5bd4e17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036963571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3036963571
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.144436454
Short name T111
Test name
Test status
Simulation time 57336626 ps
CPU time 1.13 seconds
Started Aug 07 05:29:05 PM PDT 24
Finished Aug 07 05:29:06 PM PDT 24
Peak memory 196988 kb
Host smart-51ddf958-1415-4453-812e-e0b3fcecde58
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144436454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.144436454
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1518445942
Short name T648
Test name
Test status
Simulation time 17375295033 ps
CPU time 212.17 seconds
Started Aug 07 05:29:07 PM PDT 24
Finished Aug 07 05:32:39 PM PDT 24
Peak memory 198760 kb
Host smart-bb5278c9-f2d5-4ff1-b559-0c37ad3b860b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518445942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1518445942
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2603889876
Short name T326
Test name
Test status
Simulation time 130999256 ps
CPU time 0.61 seconds
Started Aug 07 05:29:10 PM PDT 24
Finished Aug 07 05:29:10 PM PDT 24
Peak memory 194604 kb
Host smart-50dccc71-c0d7-42bc-be3c-cd0986138870
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603889876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2603889876
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2387335883
Short name T296
Test name
Test status
Simulation time 26552679 ps
CPU time 0.76 seconds
Started Aug 07 05:29:10 PM PDT 24
Finished Aug 07 05:29:11 PM PDT 24
Peak memory 196472 kb
Host smart-59166e6e-6df5-4b00-a03d-c7b305ddf396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387335883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2387335883
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3340511721
Short name T516
Test name
Test status
Simulation time 172538008 ps
CPU time 5.4 seconds
Started Aug 07 05:29:11 PM PDT 24
Finished Aug 07 05:29:16 PM PDT 24
Peak memory 197304 kb
Host smart-3d1f6efa-592e-4742-b1fd-6ed004b01e25
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340511721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3340511721
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.657305163
Short name T426
Test name
Test status
Simulation time 93128845 ps
CPU time 0.64 seconds
Started Aug 07 05:29:09 PM PDT 24
Finished Aug 07 05:29:10 PM PDT 24
Peak memory 195656 kb
Host smart-42914649-b550-4794-a299-a2d2e4b88abe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657305163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.657305163
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1612730866
Short name T343
Test name
Test status
Simulation time 183551918 ps
CPU time 0.97 seconds
Started Aug 07 05:29:12 PM PDT 24
Finished Aug 07 05:29:13 PM PDT 24
Peak memory 196360 kb
Host smart-26f8d187-5ecb-477e-a8b5-e457a2b2fbbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612730866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1612730866
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.806388185
Short name T466
Test name
Test status
Simulation time 30090857 ps
CPU time 0.96 seconds
Started Aug 07 05:29:08 PM PDT 24
Finished Aug 07 05:29:10 PM PDT 24
Peak memory 196432 kb
Host smart-f3d7d9dd-a2df-439c-80c1-ed10e85b02a0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806388185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.gpio_intr_with_filter_rand_intr_event.806388185
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1125100997
Short name T198
Test name
Test status
Simulation time 270374653 ps
CPU time 2.97 seconds
Started Aug 07 05:29:10 PM PDT 24
Finished Aug 07 05:29:13 PM PDT 24
Peak memory 197540 kb
Host smart-113ddd42-a6fe-4af5-9092-f723a4a56e82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125100997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1125100997
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1310725895
Short name T413
Test name
Test status
Simulation time 188538124 ps
CPU time 0.78 seconds
Started Aug 07 05:29:11 PM PDT 24
Finished Aug 07 05:29:12 PM PDT 24
Peak memory 197848 kb
Host smart-2e773fc0-58d1-48ed-a654-58405af8d94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310725895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1310725895
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1813027286
Short name T287
Test name
Test status
Simulation time 29535630 ps
CPU time 0.8 seconds
Started Aug 07 05:29:07 PM PDT 24
Finished Aug 07 05:29:08 PM PDT 24
Peak memory 196704 kb
Host smart-2865a978-9af4-47ec-83d5-82c1e34690a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813027286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1813027286
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2436182378
Short name T603
Test name
Test status
Simulation time 95545454 ps
CPU time 4.43 seconds
Started Aug 07 05:29:11 PM PDT 24
Finished Aug 07 05:29:15 PM PDT 24
Peak memory 198532 kb
Host smart-555d0995-b430-437c-8080-c4f2c2912b7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436182378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2436182378
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.1513212835
Short name T179
Test name
Test status
Simulation time 110239237 ps
CPU time 1.12 seconds
Started Aug 07 05:29:13 PM PDT 24
Finished Aug 07 05:29:14 PM PDT 24
Peak memory 197292 kb
Host smart-b11e0123-20ef-4c2c-8177-a0dd8ee50784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513212835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.1513212835
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2136924385
Short name T617
Test name
Test status
Simulation time 109096892 ps
CPU time 0.96 seconds
Started Aug 07 05:29:09 PM PDT 24
Finished Aug 07 05:29:10 PM PDT 24
Peak memory 196184 kb
Host smart-75f9d66f-837d-4b7d-af2b-695005a79620
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136924385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2136924385
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3761832352
Short name T300
Test name
Test status
Simulation time 29905119162 ps
CPU time 102.8 seconds
Started Aug 07 05:29:12 PM PDT 24
Finished Aug 07 05:30:55 PM PDT 24
Peak memory 198736 kb
Host smart-fbb1e212-de9a-405b-820b-5844684e6e57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761832352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3761832352
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.944667310
Short name T93
Test name
Test status
Simulation time 56304465432 ps
CPU time 1571.43 seconds
Started Aug 07 05:29:12 PM PDT 24
Finished Aug 07 05:55:24 PM PDT 24
Peak memory 198924 kb
Host smart-092debc7-a9e9-4f25-8f79-d46525269f92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=944667310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.944667310
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.940418491
Short name T242
Test name
Test status
Simulation time 41041991 ps
CPU time 0.56 seconds
Started Aug 07 05:29:20 PM PDT 24
Finished Aug 07 05:29:21 PM PDT 24
Peak memory 194064 kb
Host smart-fb025510-31ca-4e0f-97d5-c3b3b6b75a19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940418491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.940418491
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3499100639
Short name T415
Test name
Test status
Simulation time 30504268 ps
CPU time 0.78 seconds
Started Aug 07 05:29:18 PM PDT 24
Finished Aug 07 05:29:19 PM PDT 24
Peak memory 196496 kb
Host smart-b06a018e-3a5f-4f32-b656-346f424d1a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499100639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3499100639
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2320695007
Short name T252
Test name
Test status
Simulation time 1046223953 ps
CPU time 25.61 seconds
Started Aug 07 05:29:18 PM PDT 24
Finished Aug 07 05:29:44 PM PDT 24
Peak memory 197528 kb
Host smart-818c8775-38d3-4143-92d3-2ef33a103757
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320695007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2320695007
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2072088868
Short name T10
Test name
Test status
Simulation time 75588699 ps
CPU time 0.92 seconds
Started Aug 07 05:29:18 PM PDT 24
Finished Aug 07 05:29:19 PM PDT 24
Peak memory 197420 kb
Host smart-85a140ad-96c1-4ffd-b2c4-fbf8f8fc46d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072088868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2072088868
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1140211708
Short name T110
Test name
Test status
Simulation time 211476571 ps
CPU time 1 seconds
Started Aug 07 05:29:16 PM PDT 24
Finished Aug 07 05:29:17 PM PDT 24
Peak memory 196624 kb
Host smart-69e3c064-79d9-4c79-a98e-702e3bbbd350
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140211708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1140211708
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3289431116
Short name T186
Test name
Test status
Simulation time 38699270 ps
CPU time 1.67 seconds
Started Aug 07 05:29:27 PM PDT 24
Finished Aug 07 05:29:29 PM PDT 24
Peak memory 198584 kb
Host smart-bd4f0481-56cf-49e3-bc2c-77680c2542ed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289431116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3289431116
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.680276266
Short name T646
Test name
Test status
Simulation time 31608781 ps
CPU time 1.08 seconds
Started Aug 07 05:29:19 PM PDT 24
Finished Aug 07 05:29:20 PM PDT 24
Peak memory 196260 kb
Host smart-0a9c4013-6e59-4d28-88a9-fc761483c6b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680276266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
680276266
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2042078773
Short name T548
Test name
Test status
Simulation time 22893575 ps
CPU time 0.69 seconds
Started Aug 07 05:29:15 PM PDT 24
Finished Aug 07 05:29:16 PM PDT 24
Peak memory 195860 kb
Host smart-1e6b6d63-15db-4fad-be1d-6b9ecb6d3d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042078773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2042078773
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2292035791
Short name T219
Test name
Test status
Simulation time 47613177 ps
CPU time 0.68 seconds
Started Aug 07 05:29:18 PM PDT 24
Finished Aug 07 05:29:19 PM PDT 24
Peak memory 195928 kb
Host smart-58719b77-3f71-4a18-865d-940a2fc5e0fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292035791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2292035791
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1549983066
Short name T345
Test name
Test status
Simulation time 52146101 ps
CPU time 2.4 seconds
Started Aug 07 05:29:19 PM PDT 24
Finished Aug 07 05:29:21 PM PDT 24
Peak memory 198600 kb
Host smart-c7316fe9-c44c-46c9-8c2c-49e5dce513a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549983066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1549983066
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3638534128
Short name T478
Test name
Test status
Simulation time 324751533 ps
CPU time 1.25 seconds
Started Aug 07 05:29:18 PM PDT 24
Finished Aug 07 05:29:19 PM PDT 24
Peak memory 196080 kb
Host smart-55dce35e-103d-4ed1-a30e-a0ba1d5d1cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638534128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3638534128
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3299870456
Short name T700
Test name
Test status
Simulation time 44816842 ps
CPU time 0.96 seconds
Started Aug 07 05:29:18 PM PDT 24
Finished Aug 07 05:29:19 PM PDT 24
Peak memory 196344 kb
Host smart-db1515b1-2f5a-46b1-b7f1-c634b47b2d08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299870456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3299870456
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2146340278
Short name T368
Test name
Test status
Simulation time 7362733317 ps
CPU time 182.03 seconds
Started Aug 07 05:29:24 PM PDT 24
Finished Aug 07 05:32:27 PM PDT 24
Peak memory 198604 kb
Host smart-504fc0d1-64bc-42b1-93cc-bddafdcf41bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146340278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2146340278
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.2061377187
Short name T639
Test name
Test status
Simulation time 44047054904 ps
CPU time 1189.47 seconds
Started Aug 07 05:29:26 PM PDT 24
Finished Aug 07 05:49:15 PM PDT 24
Peak memory 198892 kb
Host smart-614ed98a-3c8c-4e20-ae78-60e6c7b43156
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2061377187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.2061377187
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.587092162
Short name T381
Test name
Test status
Simulation time 15187478 ps
CPU time 0.56 seconds
Started Aug 07 05:29:21 PM PDT 24
Finished Aug 07 05:29:21 PM PDT 24
Peak memory 194696 kb
Host smart-02c6e9eb-fd0c-43a5-8b6b-0b3dcde9431d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587092162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.587092162
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2264694340
Short name T654
Test name
Test status
Simulation time 33179227 ps
CPU time 0.8 seconds
Started Aug 07 05:29:25 PM PDT 24
Finished Aug 07 05:29:26 PM PDT 24
Peak memory 195780 kb
Host smart-4458336b-dd32-40e5-bc1b-d3fcccd69d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264694340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2264694340
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2584268638
Short name T171
Test name
Test status
Simulation time 939838944 ps
CPU time 12.24 seconds
Started Aug 07 05:29:26 PM PDT 24
Finished Aug 07 05:29:39 PM PDT 24
Peak memory 198576 kb
Host smart-5891d014-cd0a-482f-87b0-1ed7eeeecb49
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584268638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2584268638
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.752723778
Short name T338
Test name
Test status
Simulation time 106806292 ps
CPU time 0.66 seconds
Started Aug 07 05:29:25 PM PDT 24
Finished Aug 07 05:29:25 PM PDT 24
Peak memory 195052 kb
Host smart-ab2eb8d2-4616-403b-b53c-f9ad41b3b668
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752723778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.752723778
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1414512394
Short name T401
Test name
Test status
Simulation time 579404928 ps
CPU time 1.08 seconds
Started Aug 07 05:29:25 PM PDT 24
Finished Aug 07 05:29:26 PM PDT 24
Peak memory 196364 kb
Host smart-3608c413-d0e2-4163-bfbe-8571f0626338
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414512394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1414512394
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3885150373
Short name T606
Test name
Test status
Simulation time 126619540 ps
CPU time 2.5 seconds
Started Aug 07 05:29:22 PM PDT 24
Finished Aug 07 05:29:24 PM PDT 24
Peak memory 198576 kb
Host smart-205fc6ae-8b85-49ad-998b-c560ae5abb09
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885150373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3885150373
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3943839968
Short name T502
Test name
Test status
Simulation time 121316762 ps
CPU time 3.52 seconds
Started Aug 07 05:29:24 PM PDT 24
Finished Aug 07 05:29:27 PM PDT 24
Peak memory 197880 kb
Host smart-c7b6ae6c-2b4b-4000-893d-6a96ccc6e212
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943839968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3943839968
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.739369960
Short name T655
Test name
Test status
Simulation time 25812155 ps
CPU time 0.81 seconds
Started Aug 07 05:29:25 PM PDT 24
Finished Aug 07 05:29:26 PM PDT 24
Peak memory 195868 kb
Host smart-5f2bc23d-9081-421c-a941-2cf4f9da9889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739369960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.739369960
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2216462863
Short name T636
Test name
Test status
Simulation time 27471062 ps
CPU time 0.78 seconds
Started Aug 07 05:29:25 PM PDT 24
Finished Aug 07 05:29:26 PM PDT 24
Peak memory 196108 kb
Host smart-95c081a2-5c23-4262-9b6a-0488c5374db2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216462863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2216462863
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3438360930
Short name T260
Test name
Test status
Simulation time 600904174 ps
CPU time 2.03 seconds
Started Aug 07 05:29:25 PM PDT 24
Finished Aug 07 05:29:27 PM PDT 24
Peak memory 198572 kb
Host smart-b660c5fe-6b08-4f69-af58-e595ee759e19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438360930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3438360930
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1545559948
Short name T366
Test name
Test status
Simulation time 206808366 ps
CPU time 1.17 seconds
Started Aug 07 05:29:24 PM PDT 24
Finished Aug 07 05:29:26 PM PDT 24
Peak memory 196860 kb
Host smart-a6befd88-f3d8-480f-a298-a2392f83f57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545559948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1545559948
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2639560501
Short name T503
Test name
Test status
Simulation time 28039130 ps
CPU time 0.88 seconds
Started Aug 07 05:29:22 PM PDT 24
Finished Aug 07 05:29:23 PM PDT 24
Peak memory 196148 kb
Host smart-71f682bb-d6f9-4958-b5be-be889da646cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639560501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2639560501
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1348216942
Short name T32
Test name
Test status
Simulation time 4303579983 ps
CPU time 30.13 seconds
Started Aug 07 05:29:23 PM PDT 24
Finished Aug 07 05:29:53 PM PDT 24
Peak memory 198672 kb
Host smart-6d7ad9e9-298c-4b8d-8d75-2dfabe2451b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348216942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1348216942
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.4201781041
Short name T623
Test name
Test status
Simulation time 53450469 ps
CPU time 0.57 seconds
Started Aug 07 05:29:29 PM PDT 24
Finished Aug 07 05:29:30 PM PDT 24
Peak memory 194620 kb
Host smart-56ff3a40-9be4-41f0-9434-1d02262623e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201781041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.4201781041
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2132117822
Short name T602
Test name
Test status
Simulation time 75986679 ps
CPU time 0.69 seconds
Started Aug 07 05:29:22 PM PDT 24
Finished Aug 07 05:29:23 PM PDT 24
Peak memory 196432 kb
Host smart-1bdbc56a-f8db-4f6f-8cfc-d1a58eedebaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132117822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2132117822
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2539545631
Short name T695
Test name
Test status
Simulation time 913594407 ps
CPU time 8.75 seconds
Started Aug 07 05:29:31 PM PDT 24
Finished Aug 07 05:29:40 PM PDT 24
Peak memory 198548 kb
Host smart-28d7093c-9c7e-4f69-a26a-14120fa2d2ab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539545631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2539545631
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.4002910677
Short name T185
Test name
Test status
Simulation time 112199071 ps
CPU time 0.8 seconds
Started Aug 07 05:29:34 PM PDT 24
Finished Aug 07 05:29:35 PM PDT 24
Peak memory 196288 kb
Host smart-84fef14c-dd43-4e2a-b216-636841506559
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002910677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.4002910677
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.657073919
Short name T301
Test name
Test status
Simulation time 41033470 ps
CPU time 0.79 seconds
Started Aug 07 05:29:25 PM PDT 24
Finished Aug 07 05:29:26 PM PDT 24
Peak memory 196176 kb
Host smart-e3db691e-774b-49ef-be1c-92af24f81df6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657073919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.657073919
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1588916162
Short name T524
Test name
Test status
Simulation time 52999266 ps
CPU time 1.22 seconds
Started Aug 07 05:29:32 PM PDT 24
Finished Aug 07 05:29:33 PM PDT 24
Peak memory 197512 kb
Host smart-e7abd624-1bf4-46b3-abac-a630ea28f049
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588916162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1588916162
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1534662497
Short name T192
Test name
Test status
Simulation time 200369756 ps
CPU time 1.55 seconds
Started Aug 07 05:29:32 PM PDT 24
Finished Aug 07 05:29:34 PM PDT 24
Peak memory 196368 kb
Host smart-8480d889-7b1e-4151-99e7-989bcab575a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534662497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1534662497
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2850567011
Short name T165
Test name
Test status
Simulation time 90241577 ps
CPU time 1.07 seconds
Started Aug 07 05:29:25 PM PDT 24
Finished Aug 07 05:29:26 PM PDT 24
Peak memory 196540 kb
Host smart-669ab55c-db3e-44a5-ab9b-17fbaefe3659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850567011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2850567011
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.865560391
Short name T255
Test name
Test status
Simulation time 60133227 ps
CPU time 1.1 seconds
Started Aug 07 05:29:24 PM PDT 24
Finished Aug 07 05:29:26 PM PDT 24
Peak memory 196540 kb
Host smart-840b3091-3ed7-43d2-8249-d970666ae908
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865560391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.865560391
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.209756191
Short name T442
Test name
Test status
Simulation time 108029748 ps
CPU time 4.58 seconds
Started Aug 07 05:29:36 PM PDT 24
Finished Aug 07 05:29:41 PM PDT 24
Peak memory 197568 kb
Host smart-d0254b8b-7197-4d2c-8f21-957206ce3d9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209756191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.209756191
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1372412016
Short name T698
Test name
Test status
Simulation time 80047524 ps
CPU time 1.32 seconds
Started Aug 07 05:29:20 PM PDT 24
Finished Aug 07 05:29:22 PM PDT 24
Peak memory 196080 kb
Host smart-d201578e-8a24-4717-b72b-48d2afc29afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372412016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1372412016
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2237963837
Short name T496
Test name
Test status
Simulation time 27169760 ps
CPU time 0.71 seconds
Started Aug 07 05:29:20 PM PDT 24
Finished Aug 07 05:29:21 PM PDT 24
Peak memory 196524 kb
Host smart-346c96f0-9b04-4465-adc7-2b1d5261647a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237963837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2237963837
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.644480064
Short name T9
Test name
Test status
Simulation time 162293396351 ps
CPU time 167.46 seconds
Started Aug 07 05:29:34 PM PDT 24
Finished Aug 07 05:32:22 PM PDT 24
Peak memory 198576 kb
Host smart-dbceb2ee-94fc-4cdc-8cb7-c1e6b9289e22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644480064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.644480064
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.989361160
Short name T608
Test name
Test status
Simulation time 79344189654 ps
CPU time 2201.94 seconds
Started Aug 07 05:29:28 PM PDT 24
Finished Aug 07 06:06:10 PM PDT 24
Peak memory 198908 kb
Host smart-b55bf0bd-6dac-4670-85d4-f288ac704ec9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=989361160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.989361160
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1678848886
Short name T207
Test name
Test status
Simulation time 16309526 ps
CPU time 0.6 seconds
Started Aug 07 05:29:31 PM PDT 24
Finished Aug 07 05:29:32 PM PDT 24
Peak memory 194672 kb
Host smart-624a0374-4376-4a59-91ce-bdfbcdce326f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678848886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1678848886
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3171239028
Short name T528
Test name
Test status
Simulation time 205740452 ps
CPU time 0.68 seconds
Started Aug 07 05:29:28 PM PDT 24
Finished Aug 07 05:29:29 PM PDT 24
Peak memory 195248 kb
Host smart-acc167e6-1cef-40e6-9302-fc65df716aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171239028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3171239028
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.4003653859
Short name T710
Test name
Test status
Simulation time 186587831 ps
CPU time 8.14 seconds
Started Aug 07 05:29:27 PM PDT 24
Finished Aug 07 05:29:35 PM PDT 24
Peak memory 198432 kb
Host smart-b5c7c438-d097-4e09-8b9c-d09941578c68
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003653859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.4003653859
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2889463430
Short name T481
Test name
Test status
Simulation time 26231773 ps
CPU time 0.62 seconds
Started Aug 07 05:29:31 PM PDT 24
Finished Aug 07 05:29:32 PM PDT 24
Peak memory 194612 kb
Host smart-26684175-e67b-4e18-82fa-539acc6ba3bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889463430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2889463430
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3045367482
Short name T543
Test name
Test status
Simulation time 54667018 ps
CPU time 1.32 seconds
Started Aug 07 05:29:34 PM PDT 24
Finished Aug 07 05:29:36 PM PDT 24
Peak memory 197772 kb
Host smart-d2ff24a0-d79e-4564-974f-fdb6a13f58d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045367482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3045367482
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3405657107
Short name T681
Test name
Test status
Simulation time 296118049 ps
CPU time 2.79 seconds
Started Aug 07 05:29:35 PM PDT 24
Finished Aug 07 05:29:38 PM PDT 24
Peak memory 197060 kb
Host smart-28af30d9-a418-40e3-a907-6eb75282e1a6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405657107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3405657107
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.871691766
Short name T214
Test name
Test status
Simulation time 406396357 ps
CPU time 2.79 seconds
Started Aug 07 05:29:32 PM PDT 24
Finished Aug 07 05:29:35 PM PDT 24
Peak memory 197116 kb
Host smart-85324aef-a232-47f3-a9d3-a9c4a2fdffc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871691766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
871691766
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2737899049
Short name T630
Test name
Test status
Simulation time 32272666 ps
CPU time 1.13 seconds
Started Aug 07 05:29:31 PM PDT 24
Finished Aug 07 05:29:32 PM PDT 24
Peak memory 197172 kb
Host smart-3a6826e0-a548-40ef-8661-c313859be79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737899049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2737899049
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.983510599
Short name T117
Test name
Test status
Simulation time 66759107 ps
CPU time 0.86 seconds
Started Aug 07 05:29:35 PM PDT 24
Finished Aug 07 05:29:36 PM PDT 24
Peak memory 197252 kb
Host smart-26a5368d-0eb3-4e3a-a411-3198cdd104d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983510599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup
_pulldown.983510599
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2651231281
Short name T261
Test name
Test status
Simulation time 103030999 ps
CPU time 4.63 seconds
Started Aug 07 05:29:36 PM PDT 24
Finished Aug 07 05:29:41 PM PDT 24
Peak memory 198516 kb
Host smart-c4677550-676b-49e4-a753-f8fd20c4488c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651231281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.2651231281
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.980339689
Short name T669
Test name
Test status
Simulation time 47695504 ps
CPU time 1.33 seconds
Started Aug 07 05:29:34 PM PDT 24
Finished Aug 07 05:29:36 PM PDT 24
Peak memory 198464 kb
Host smart-2a07465e-bf10-4106-98a4-fbebc8adfa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980339689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.980339689
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.245663731
Short name T591
Test name
Test status
Simulation time 227129798 ps
CPU time 1.2 seconds
Started Aug 07 05:29:34 PM PDT 24
Finished Aug 07 05:29:36 PM PDT 24
Peak memory 196988 kb
Host smart-6f720f50-44cf-4e3d-9f4f-bb21155839be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245663731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.245663731
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.846733422
Short name T449
Test name
Test status
Simulation time 3388402721 ps
CPU time 86.36 seconds
Started Aug 07 05:29:32 PM PDT 24
Finished Aug 07 05:30:59 PM PDT 24
Peak memory 198696 kb
Host smart-e8a5dcc5-d854-43e7-a033-c69b820a2aad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846733422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.846733422
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.3456297879
Short name T236
Test name
Test status
Simulation time 13197599 ps
CPU time 0.55 seconds
Started Aug 07 05:29:37 PM PDT 24
Finished Aug 07 05:29:37 PM PDT 24
Peak memory 194500 kb
Host smart-0464557e-504f-4021-87f1-214aae536b6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456297879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.3456297879
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.3998163868
Short name T574
Test name
Test status
Simulation time 131336804 ps
CPU time 0.63 seconds
Started Aug 07 05:29:32 PM PDT 24
Finished Aug 07 05:29:33 PM PDT 24
Peak memory 194432 kb
Host smart-51fe1ded-ebeb-4756-aada-1e9d392a2222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998163868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.3998163868
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2819783257
Short name T679
Test name
Test status
Simulation time 364908257 ps
CPU time 9.2 seconds
Started Aug 07 05:29:30 PM PDT 24
Finished Aug 07 05:29:39 PM PDT 24
Peak memory 197492 kb
Host smart-f494f45c-f9d0-4484-9603-bdcba81ab505
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819783257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2819783257
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2530291021
Short name T384
Test name
Test status
Simulation time 686556908 ps
CPU time 0.73 seconds
Started Aug 07 05:29:40 PM PDT 24
Finished Aug 07 05:29:41 PM PDT 24
Peak memory 196056 kb
Host smart-6aa41be6-a286-425d-95ef-b7239e662dc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530291021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2530291021
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2113068236
Short name T514
Test name
Test status
Simulation time 75201059 ps
CPU time 1.29 seconds
Started Aug 07 05:29:34 PM PDT 24
Finished Aug 07 05:29:35 PM PDT 24
Peak memory 196736 kb
Host smart-e99e8748-8b19-4a78-b10c-5cca972552a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113068236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2113068236
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1679778013
Short name T133
Test name
Test status
Simulation time 363302112 ps
CPU time 3.64 seconds
Started Aug 07 05:29:31 PM PDT 24
Finished Aug 07 05:29:35 PM PDT 24
Peak memory 198620 kb
Host smart-5d8a7126-d920-422a-95a1-ce33492acd12
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679778013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1679778013
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.4119558466
Short name T279
Test name
Test status
Simulation time 745525789 ps
CPU time 2.42 seconds
Started Aug 07 05:29:29 PM PDT 24
Finished Aug 07 05:29:32 PM PDT 24
Peak memory 196428 kb
Host smart-d0ab2bd4-aa77-4a32-a368-188a5e623f12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119558466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.4119558466
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.444935839
Short name T624
Test name
Test status
Simulation time 20770917 ps
CPU time 0.79 seconds
Started Aug 07 05:29:32 PM PDT 24
Finished Aug 07 05:29:32 PM PDT 24
Peak memory 195996 kb
Host smart-074ca84c-9392-449f-ae3d-679eb66de4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444935839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.444935839
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3374718562
Short name T525
Test name
Test status
Simulation time 30713800 ps
CPU time 1.06 seconds
Started Aug 07 05:29:32 PM PDT 24
Finished Aug 07 05:29:34 PM PDT 24
Peak memory 196412 kb
Host smart-6908df1e-3220-45c6-8d3c-4cdea24db3e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374718562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3374718562
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1751636085
Short name T534
Test name
Test status
Simulation time 194003744 ps
CPU time 1.95 seconds
Started Aug 07 05:29:35 PM PDT 24
Finished Aug 07 05:29:37 PM PDT 24
Peak memory 198568 kb
Host smart-5f12936b-2418-43c8-9178-5b8064ec1435
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751636085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1751636085
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2474621586
Short name T124
Test name
Test status
Simulation time 298298183 ps
CPU time 1.2 seconds
Started Aug 07 05:29:32 PM PDT 24
Finished Aug 07 05:29:34 PM PDT 24
Peak memory 196204 kb
Host smart-87a66d90-e9f7-4c07-be1e-0b2376ae8ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474621586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2474621586
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.471719742
Short name T262
Test name
Test status
Simulation time 328541393 ps
CPU time 1.42 seconds
Started Aug 07 05:29:32 PM PDT 24
Finished Aug 07 05:29:33 PM PDT 24
Peak memory 197412 kb
Host smart-df5e5b84-2992-4e82-b504-f5732965035a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471719742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.471719742
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.289452472
Short name T329
Test name
Test status
Simulation time 21236382926 ps
CPU time 186.96 seconds
Started Aug 07 05:29:37 PM PDT 24
Finished Aug 07 05:32:44 PM PDT 24
Peak memory 192604 kb
Host smart-ae2193df-fadf-42c7-aac2-197cf9382280
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289452472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.289452472
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.3514599375
Short name T488
Test name
Test status
Simulation time 16014539377 ps
CPU time 451.61 seconds
Started Aug 07 05:29:37 PM PDT 24
Finished Aug 07 05:37:09 PM PDT 24
Peak memory 198860 kb
Host smart-8bf1f4e5-ab6c-4679-821f-03533abfd9ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3514599375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.3514599375
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1319871666
Short name T359
Test name
Test status
Simulation time 18593167 ps
CPU time 0.59 seconds
Started Aug 07 05:29:37 PM PDT 24
Finished Aug 07 05:29:38 PM PDT 24
Peak memory 194476 kb
Host smart-5c0abbbf-5c15-4ca9-90b9-06ce0d6b14b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319871666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1319871666
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.542909689
Short name T493
Test name
Test status
Simulation time 56361602 ps
CPU time 0.68 seconds
Started Aug 07 05:29:34 PM PDT 24
Finished Aug 07 05:29:35 PM PDT 24
Peak memory 195652 kb
Host smart-541aeb38-1f9d-41be-8427-73a601f05b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542909689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.542909689
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.2124954773
Short name T121
Test name
Test status
Simulation time 204219884 ps
CPU time 10.52 seconds
Started Aug 07 05:29:37 PM PDT 24
Finished Aug 07 05:29:48 PM PDT 24
Peak memory 197516 kb
Host smart-b93f88f1-fc13-44e8-8c71-730bab201e4a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124954773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.2124954773
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2698010134
Short name T667
Test name
Test status
Simulation time 1412030851 ps
CPU time 0.94 seconds
Started Aug 07 05:29:38 PM PDT 24
Finished Aug 07 05:29:39 PM PDT 24
Peak memory 197264 kb
Host smart-2f8cf2ea-5a8a-4123-bf1f-40ed5673c424
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698010134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2698010134
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.432503688
Short name T691
Test name
Test status
Simulation time 1176192739 ps
CPU time 1.27 seconds
Started Aug 07 05:29:35 PM PDT 24
Finished Aug 07 05:29:36 PM PDT 24
Peak memory 197688 kb
Host smart-ad877154-618d-4407-ba6c-4ec2d3161f8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432503688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.432503688
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2034155133
Short name T544
Test name
Test status
Simulation time 83836887 ps
CPU time 3.54 seconds
Started Aug 07 05:29:35 PM PDT 24
Finished Aug 07 05:29:38 PM PDT 24
Peak memory 198972 kb
Host smart-323a8a51-4b3e-4646-814a-65e2d6589a71
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034155133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2034155133
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.585387328
Short name T227
Test name
Test status
Simulation time 195106831 ps
CPU time 0.84 seconds
Started Aug 07 05:29:42 PM PDT 24
Finished Aug 07 05:29:43 PM PDT 24
Peak memory 194948 kb
Host smart-6d66581f-c7cb-4255-aae7-ab2af027798f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585387328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
585387328
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3441018975
Short name T168
Test name
Test status
Simulation time 17640798 ps
CPU time 0.73 seconds
Started Aug 07 05:29:40 PM PDT 24
Finished Aug 07 05:29:40 PM PDT 24
Peak memory 195928 kb
Host smart-cd54f75c-ce42-48b1-bef5-a94508e2cfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441018975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3441018975
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.486504416
Short name T303
Test name
Test status
Simulation time 60526797 ps
CPU time 1.28 seconds
Started Aug 07 05:29:40 PM PDT 24
Finished Aug 07 05:29:42 PM PDT 24
Peak memory 197544 kb
Host smart-6ca0398b-9f08-4996-8db9-7187af36a230
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486504416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup
_pulldown.486504416
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.4003048457
Short name T664
Test name
Test status
Simulation time 640035914 ps
CPU time 3.27 seconds
Started Aug 07 05:29:41 PM PDT 24
Finished Aug 07 05:29:44 PM PDT 24
Peak memory 198528 kb
Host smart-0c8880c4-11fa-435d-895a-7d67a939160b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003048457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.4003048457
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.4282743448
Short name T424
Test name
Test status
Simulation time 60984918 ps
CPU time 1.05 seconds
Started Aug 07 05:29:34 PM PDT 24
Finished Aug 07 05:29:35 PM PDT 24
Peak memory 196376 kb
Host smart-f31dcdf2-91d2-41a3-9b76-27afba7d127c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282743448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.4282743448
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1389296579
Short name T122
Test name
Test status
Simulation time 49970516 ps
CPU time 1.06 seconds
Started Aug 07 05:29:38 PM PDT 24
Finished Aug 07 05:29:39 PM PDT 24
Peak memory 196148 kb
Host smart-4e953321-1d3b-43b0-9dc9-aaa30977dfb0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389296579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1389296579
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3371398643
Short name T674
Test name
Test status
Simulation time 5565698900 ps
CPU time 62.02 seconds
Started Aug 07 05:29:41 PM PDT 24
Finished Aug 07 05:30:43 PM PDT 24
Peak memory 198748 kb
Host smart-6e8bad30-b093-4d4e-b580-57c10342b69d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371398643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3371398643
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.2638732981
Short name T547
Test name
Test status
Simulation time 120540392530 ps
CPU time 421.42 seconds
Started Aug 07 05:29:33 PM PDT 24
Finished Aug 07 05:36:34 PM PDT 24
Peak memory 198888 kb
Host smart-05c9b51f-ee6e-4618-b2bb-248e26613a47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2638732981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.2638732981
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1235581404
Short name T718
Test name
Test status
Simulation time 32173166 ps
CPU time 0.55 seconds
Started Aug 07 05:26:58 PM PDT 24
Finished Aug 07 05:26:58 PM PDT 24
Peak memory 194684 kb
Host smart-6fe7b8ae-cad6-4a95-908b-2e33a1072584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235581404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1235581404
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.450437612
Short name T107
Test name
Test status
Simulation time 98374963 ps
CPU time 0.7 seconds
Started Aug 07 05:27:00 PM PDT 24
Finished Aug 07 05:27:01 PM PDT 24
Peak memory 195624 kb
Host smart-2dc2f0a7-1d80-470e-abe8-65fbe9bff370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450437612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.450437612
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3324693343
Short name T129
Test name
Test status
Simulation time 450263755 ps
CPU time 12.3 seconds
Started Aug 07 05:26:57 PM PDT 24
Finished Aug 07 05:27:09 PM PDT 24
Peak memory 197648 kb
Host smart-3b643485-f9a0-4f2d-936a-efe4dd1bd560
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324693343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3324693343
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.125473995
Short name T150
Test name
Test status
Simulation time 113972500 ps
CPU time 1.01 seconds
Started Aug 07 05:26:56 PM PDT 24
Finished Aug 07 05:26:58 PM PDT 24
Peak memory 196696 kb
Host smart-d0a10b9c-6eba-4975-9693-89bc70ae53df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125473995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.125473995
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1643437409
Short name T553
Test name
Test status
Simulation time 150252454 ps
CPU time 2.87 seconds
Started Aug 07 05:26:55 PM PDT 24
Finished Aug 07 05:26:58 PM PDT 24
Peak memory 197968 kb
Host smart-b931ad26-def8-48b9-b740-eed1bf0d0b92
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643437409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1643437409
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.1162720314
Short name T354
Test name
Test status
Simulation time 93074271 ps
CPU time 2.54 seconds
Started Aug 07 05:26:55 PM PDT 24
Finished Aug 07 05:26:58 PM PDT 24
Peak memory 197828 kb
Host smart-e192848d-a7d7-4ef9-a0d2-156dc7453865
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162720314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
1162720314
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3881508641
Short name T565
Test name
Test status
Simulation time 47669057 ps
CPU time 1.03 seconds
Started Aug 07 05:27:00 PM PDT 24
Finished Aug 07 05:27:01 PM PDT 24
Peak memory 197208 kb
Host smart-63c6900f-9ccd-4f7c-961c-cc61faa939ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881508641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3881508641
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2613014958
Short name T711
Test name
Test status
Simulation time 93732111 ps
CPU time 1.07 seconds
Started Aug 07 05:26:57 PM PDT 24
Finished Aug 07 05:26:59 PM PDT 24
Peak memory 197644 kb
Host smart-275c5033-661a-4918-8e35-4f5478463eb1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613014958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2613014958
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1545092949
Short name T529
Test name
Test status
Simulation time 450940326 ps
CPU time 4.69 seconds
Started Aug 07 05:26:58 PM PDT 24
Finished Aug 07 05:27:03 PM PDT 24
Peak memory 198484 kb
Host smart-bc846b0e-a8ec-4d47-ac0e-5e4958406a68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545092949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1545092949
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.1242416205
Short name T23
Test name
Test status
Simulation time 370200713 ps
CPU time 0.91 seconds
Started Aug 07 05:26:55 PM PDT 24
Finished Aug 07 05:26:56 PM PDT 24
Peak memory 215476 kb
Host smart-e8f30dd5-b2dc-421b-a59d-372259937bd6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242416205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1242416205
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2853730785
Short name T419
Test name
Test status
Simulation time 132481061 ps
CPU time 0.93 seconds
Started Aug 07 05:26:57 PM PDT 24
Finished Aug 07 05:26:58 PM PDT 24
Peak memory 196784 kb
Host smart-dbadc63a-48b1-40e7-aed4-7673d52d88b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853730785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2853730785
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3060815299
Short name T686
Test name
Test status
Simulation time 41572797 ps
CPU time 0.92 seconds
Started Aug 07 05:26:57 PM PDT 24
Finished Aug 07 05:26:58 PM PDT 24
Peak memory 196164 kb
Host smart-09cbd8b7-3ca6-4f4f-a145-4a940bcaa5a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060815299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3060815299
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.683441327
Short name T308
Test name
Test status
Simulation time 16185040848 ps
CPU time 26.51 seconds
Started Aug 07 05:26:57 PM PDT 24
Finished Aug 07 05:27:23 PM PDT 24
Peak memory 198716 kb
Host smart-0d27e50f-ea33-4bcd-b129-e5a507e0b15f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683441327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.683441327
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.1162614245
Short name T91
Test name
Test status
Simulation time 36095188691 ps
CPU time 539.79 seconds
Started Aug 07 05:27:01 PM PDT 24
Finished Aug 07 05:36:01 PM PDT 24
Peak memory 198856 kb
Host smart-fb4f16dd-6fc6-4a14-98b9-62ba64c5694e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1162614245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.1162614245
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3196253385
Short name T162
Test name
Test status
Simulation time 66186326 ps
CPU time 0.58 seconds
Started Aug 07 05:29:42 PM PDT 24
Finished Aug 07 05:29:42 PM PDT 24
Peak memory 194556 kb
Host smart-7f088c53-d73c-459b-bfde-80ad45402549
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196253385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3196253385
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2794242411
Short name T395
Test name
Test status
Simulation time 40894995 ps
CPU time 0.65 seconds
Started Aug 07 05:29:42 PM PDT 24
Finished Aug 07 05:29:43 PM PDT 24
Peak memory 194528 kb
Host smart-c1986304-dbd1-454d-b776-5b6272ef200c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794242411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2794242411
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1385355764
Short name T670
Test name
Test status
Simulation time 446830684 ps
CPU time 10.63 seconds
Started Aug 07 05:29:39 PM PDT 24
Finished Aug 07 05:29:50 PM PDT 24
Peak memory 196108 kb
Host smart-6d6c323a-4652-4602-9190-f49d087b8b3c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385355764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1385355764
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3477556267
Short name T430
Test name
Test status
Simulation time 71298655 ps
CPU time 0.93 seconds
Started Aug 07 05:29:42 PM PDT 24
Finished Aug 07 05:29:43 PM PDT 24
Peak memory 197784 kb
Host smart-46dace5e-3de8-445a-83c6-8af0899efcf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477556267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3477556267
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2865111777
Short name T715
Test name
Test status
Simulation time 28770915 ps
CPU time 0.85 seconds
Started Aug 07 05:29:37 PM PDT 24
Finished Aug 07 05:29:38 PM PDT 24
Peak memory 197080 kb
Host smart-01c3f803-4d1d-43e8-919d-d6509fa5cd42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865111777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2865111777
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3092732696
Short name T365
Test name
Test status
Simulation time 140909600 ps
CPU time 3.66 seconds
Started Aug 07 05:29:44 PM PDT 24
Finished Aug 07 05:29:48 PM PDT 24
Peak memory 198548 kb
Host smart-3b675b85-ebef-4238-8d54-085397597d9b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092732696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3092732696
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.3150266214
Short name T428
Test name
Test status
Simulation time 254520975 ps
CPU time 2.2 seconds
Started Aug 07 05:29:41 PM PDT 24
Finished Aug 07 05:29:43 PM PDT 24
Peak memory 198624 kb
Host smart-ec5e3e73-ac9b-4b84-a509-b1161df73ab8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150266214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.3150266214
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2949799535
Short name T620
Test name
Test status
Simulation time 19611886 ps
CPU time 0.8 seconds
Started Aug 07 05:29:43 PM PDT 24
Finished Aug 07 05:29:44 PM PDT 24
Peak memory 197764 kb
Host smart-6ea7b218-e1f4-45da-8f35-fa18ded88f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949799535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2949799535
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.314164590
Short name T297
Test name
Test status
Simulation time 86392387 ps
CPU time 0.92 seconds
Started Aug 07 05:29:38 PM PDT 24
Finished Aug 07 05:29:39 PM PDT 24
Peak memory 196488 kb
Host smart-a6dd5f21-f59d-442e-80ed-ba00f748deb4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314164590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup
_pulldown.314164590
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.386599624
Short name T280
Test name
Test status
Simulation time 306612879 ps
CPU time 5.05 seconds
Started Aug 07 05:29:42 PM PDT 24
Finished Aug 07 05:29:47 PM PDT 24
Peak memory 198520 kb
Host smart-4b019800-bb74-415d-b96e-124d8494dfea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386599624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.386599624
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1511597487
Short name T132
Test name
Test status
Simulation time 244840759 ps
CPU time 1.04 seconds
Started Aug 07 05:29:38 PM PDT 24
Finished Aug 07 05:29:39 PM PDT 24
Peak memory 196328 kb
Host smart-269f1ec6-52d3-4047-bcea-d2f4256575d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511597487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1511597487
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.357305795
Short name T26
Test name
Test status
Simulation time 69331679 ps
CPU time 1.26 seconds
Started Aug 07 05:29:37 PM PDT 24
Finished Aug 07 05:29:38 PM PDT 24
Peak memory 197020 kb
Host smart-87d1d7fc-5db4-4d65-8bdf-65764d4b51dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357305795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.357305795
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.144641846
Short name T259
Test name
Test status
Simulation time 11337366646 ps
CPU time 147.35 seconds
Started Aug 07 05:29:47 PM PDT 24
Finished Aug 07 05:32:14 PM PDT 24
Peak memory 198768 kb
Host smart-bec75303-73a8-4e8d-8d53-27642e873fc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144641846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.144641846
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2492279578
Short name T159
Test name
Test status
Simulation time 139496889 ps
CPU time 0.57 seconds
Started Aug 07 05:29:42 PM PDT 24
Finished Aug 07 05:29:43 PM PDT 24
Peak memory 194440 kb
Host smart-c25b2afb-740e-464c-9299-dd19a3c0a05d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492279578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2492279578
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.4061518390
Short name T141
Test name
Test status
Simulation time 418345579 ps
CPU time 0.88 seconds
Started Aug 07 05:29:44 PM PDT 24
Finished Aug 07 05:29:45 PM PDT 24
Peak memory 197160 kb
Host smart-31365db7-5242-4c9a-8c67-7be50154f803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061518390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.4061518390
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1528126778
Short name T660
Test name
Test status
Simulation time 340172988 ps
CPU time 7.98 seconds
Started Aug 07 05:29:42 PM PDT 24
Finished Aug 07 05:29:51 PM PDT 24
Peak memory 197480 kb
Host smart-6e81cb5d-e816-4d3a-8024-645f486960ce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528126778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1528126778
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.2402472951
Short name T221
Test name
Test status
Simulation time 97989304 ps
CPU time 0.68 seconds
Started Aug 07 05:29:44 PM PDT 24
Finished Aug 07 05:29:45 PM PDT 24
Peak memory 195168 kb
Host smart-45830e80-b521-4b59-a969-a4bfe1892fa9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402472951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2402472951
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3577649477
Short name T167
Test name
Test status
Simulation time 42510971 ps
CPU time 0.96 seconds
Started Aug 07 05:29:44 PM PDT 24
Finished Aug 07 05:29:45 PM PDT 24
Peak memory 197284 kb
Host smart-091cd11c-bb8c-4c15-afee-f9e80633d0be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577649477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3577649477
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3589394477
Short name T209
Test name
Test status
Simulation time 208570656 ps
CPU time 2.3 seconds
Started Aug 07 05:29:40 PM PDT 24
Finished Aug 07 05:29:43 PM PDT 24
Peak memory 198720 kb
Host smart-6b7b9bb1-9b8b-4f54-8487-bfc2d6107fd3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589394477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3589394477
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3238135863
Short name T248
Test name
Test status
Simulation time 99357838 ps
CPU time 1.82 seconds
Started Aug 07 05:29:45 PM PDT 24
Finished Aug 07 05:29:47 PM PDT 24
Peak memory 196568 kb
Host smart-61f1a887-bdb7-48b4-9df6-b11bd5a3ec1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238135863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3238135863
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1400251934
Short name T349
Test name
Test status
Simulation time 13196470 ps
CPU time 0.63 seconds
Started Aug 07 05:29:42 PM PDT 24
Finished Aug 07 05:29:43 PM PDT 24
Peak memory 194768 kb
Host smart-85c91e4c-7c94-41fd-9ded-9fd6c96a4b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400251934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1400251934
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.429706206
Short name T536
Test name
Test status
Simulation time 34238014 ps
CPU time 1.14 seconds
Started Aug 07 05:29:41 PM PDT 24
Finished Aug 07 05:29:42 PM PDT 24
Peak memory 198640 kb
Host smart-4b038631-51f7-4930-8e54-7f345f168ee4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429706206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.429706206
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2269124544
Short name T272
Test name
Test status
Simulation time 258898056 ps
CPU time 3.13 seconds
Started Aug 07 05:29:41 PM PDT 24
Finished Aug 07 05:29:45 PM PDT 24
Peak memory 198452 kb
Host smart-ee594e25-6ed9-4caa-bcf7-be93bfb05fbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269124544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2269124544
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1076523371
Short name T467
Test name
Test status
Simulation time 318881779 ps
CPU time 1.21 seconds
Started Aug 07 05:29:49 PM PDT 24
Finished Aug 07 05:29:50 PM PDT 24
Peak memory 196124 kb
Host smart-a11e6228-8993-47bf-b95e-6b33b9621b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076523371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1076523371
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1510591862
Short name T461
Test name
Test status
Simulation time 167195597 ps
CPU time 0.9 seconds
Started Aug 07 05:29:43 PM PDT 24
Finished Aug 07 05:29:44 PM PDT 24
Peak memory 195792 kb
Host smart-ea7c26e3-8dbc-4255-bca0-150661336293
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510591862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1510591862
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.29110404
Short name T684
Test name
Test status
Simulation time 6610092742 ps
CPU time 171.96 seconds
Started Aug 07 05:29:42 PM PDT 24
Finished Aug 07 05:32:34 PM PDT 24
Peak memory 198748 kb
Host smart-5e26f56e-d7fc-4fec-a920-2bc613fa2958
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29110404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gp
io_stress_all.29110404
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.2532527213
Short name T388
Test name
Test status
Simulation time 47620813888 ps
CPU time 273.43 seconds
Started Aug 07 05:29:44 PM PDT 24
Finished Aug 07 05:34:18 PM PDT 24
Peak memory 198816 kb
Host smart-e0c26603-97ab-4bdd-adec-59a5300c6ad5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2532527213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.2532527213
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2132922022
Short name T334
Test name
Test status
Simulation time 36191158 ps
CPU time 0.55 seconds
Started Aug 07 05:29:49 PM PDT 24
Finished Aug 07 05:29:50 PM PDT 24
Peak memory 195340 kb
Host smart-0cdac3e0-4696-411b-9395-f8636967dc6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132922022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2132922022
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3395147631
Short name T323
Test name
Test status
Simulation time 124505461 ps
CPU time 0.8 seconds
Started Aug 07 05:29:44 PM PDT 24
Finished Aug 07 05:29:45 PM PDT 24
Peak memory 195964 kb
Host smart-6749d47e-7013-4534-bf40-fab291284aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395147631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3395147631
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.1849170590
Short name T291
Test name
Test status
Simulation time 252350154 ps
CPU time 6.41 seconds
Started Aug 07 05:29:44 PM PDT 24
Finished Aug 07 05:29:51 PM PDT 24
Peak memory 197612 kb
Host smart-ca69f124-5217-4c12-983b-bb862ec893d2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849170590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.1849170590
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3919908655
Short name T540
Test name
Test status
Simulation time 46003528 ps
CPU time 0.69 seconds
Started Aug 07 05:29:47 PM PDT 24
Finished Aug 07 05:29:48 PM PDT 24
Peak memory 195284 kb
Host smart-50f8814b-0bea-40ad-9986-67480ff07c28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919908655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3919908655
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.448002237
Short name T475
Test name
Test status
Simulation time 25878364 ps
CPU time 0.89 seconds
Started Aug 07 05:29:41 PM PDT 24
Finished Aug 07 05:29:42 PM PDT 24
Peak memory 197948 kb
Host smart-eb282f1c-d7fe-4127-b643-89947daeaa13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448002237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.448002237
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2854091276
Short name T510
Test name
Test status
Simulation time 80402810 ps
CPU time 3.14 seconds
Started Aug 07 05:29:47 PM PDT 24
Finished Aug 07 05:29:50 PM PDT 24
Peak memory 198552 kb
Host smart-f8aa4a7f-2bdb-40e6-aa37-6beb5c832f74
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854091276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2854091276
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2095960068
Short name T282
Test name
Test status
Simulation time 716091041 ps
CPU time 1.8 seconds
Started Aug 07 05:29:44 PM PDT 24
Finished Aug 07 05:29:46 PM PDT 24
Peak memory 197356 kb
Host smart-e00cf285-d3d9-4ba0-b4dd-6a0f333a0582
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095960068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2095960068
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3169187393
Short name T139
Test name
Test status
Simulation time 24457857 ps
CPU time 0.92 seconds
Started Aug 07 05:29:42 PM PDT 24
Finished Aug 07 05:29:43 PM PDT 24
Peak memory 196488 kb
Host smart-1ac799ab-aa22-4272-9de0-84b4d2034d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169187393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3169187393
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1146097152
Short name T626
Test name
Test status
Simulation time 100783237 ps
CPU time 0.97 seconds
Started Aug 07 05:29:45 PM PDT 24
Finished Aug 07 05:29:46 PM PDT 24
Peak memory 197220 kb
Host smart-5f972a5a-2bb9-42f9-a6de-496f6fc52d46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146097152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1146097152
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3788606208
Short name T160
Test name
Test status
Simulation time 146300807 ps
CPU time 1.66 seconds
Started Aug 07 05:29:42 PM PDT 24
Finished Aug 07 05:29:44 PM PDT 24
Peak memory 198564 kb
Host smart-5d3c6f73-f741-4ee2-b76d-5de30aef92a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788606208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3788606208
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2971975708
Short name T570
Test name
Test status
Simulation time 130106331 ps
CPU time 1 seconds
Started Aug 07 05:29:42 PM PDT 24
Finished Aug 07 05:29:44 PM PDT 24
Peak memory 196008 kb
Host smart-c739f623-663d-444a-aad4-adab568bf5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971975708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2971975708
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1482385627
Short name T583
Test name
Test status
Simulation time 60833082 ps
CPU time 0.84 seconds
Started Aug 07 05:29:41 PM PDT 24
Finished Aug 07 05:29:42 PM PDT 24
Peak memory 196948 kb
Host smart-c67f502f-7dee-4f5f-9f3a-38b786a74a3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482385627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1482385627
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3240488167
Short name T505
Test name
Test status
Simulation time 7834496764 ps
CPU time 30.86 seconds
Started Aug 07 05:29:52 PM PDT 24
Finished Aug 07 05:30:23 PM PDT 24
Peak memory 198792 kb
Host smart-a4bb55ad-7da5-43ab-8535-453994f73f3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240488167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3240488167
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.1708140812
Short name T49
Test name
Test status
Simulation time 113161005805 ps
CPU time 1391.12 seconds
Started Aug 07 05:29:50 PM PDT 24
Finished Aug 07 05:53:01 PM PDT 24
Peak memory 198880 kb
Host smart-a334a4a1-63cf-40c4-84dd-0863bc68494f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1708140812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.1708140812
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2723880449
Short name T498
Test name
Test status
Simulation time 54475618 ps
CPU time 0.56 seconds
Started Aug 07 05:29:51 PM PDT 24
Finished Aug 07 05:29:52 PM PDT 24
Peak memory 195204 kb
Host smart-e7a6c712-88f8-46aa-9daa-d6008a0fa751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723880449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2723880449
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2366976096
Short name T258
Test name
Test status
Simulation time 131456137 ps
CPU time 0.85 seconds
Started Aug 07 05:29:48 PM PDT 24
Finished Aug 07 05:29:49 PM PDT 24
Peak memory 197532 kb
Host smart-6ea78674-8caa-464c-8e3a-22dd0166b4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366976096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2366976096
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3956731096
Short name T369
Test name
Test status
Simulation time 317125753 ps
CPU time 7.33 seconds
Started Aug 07 05:29:47 PM PDT 24
Finished Aug 07 05:29:54 PM PDT 24
Peak memory 197544 kb
Host smart-6e422537-49ba-42ea-9663-4a5b4f868545
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956731096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3956731096
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3321445045
Short name T393
Test name
Test status
Simulation time 173360332 ps
CPU time 0.78 seconds
Started Aug 07 05:29:48 PM PDT 24
Finished Aug 07 05:29:49 PM PDT 24
Peak memory 197068 kb
Host smart-dcb463b6-f516-4938-bd46-8b3053eeb36f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321445045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3321445045
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3415930964
Short name T235
Test name
Test status
Simulation time 52073362 ps
CPU time 1 seconds
Started Aug 07 05:29:52 PM PDT 24
Finished Aug 07 05:29:53 PM PDT 24
Peak memory 196372 kb
Host smart-32a2bd3b-5952-44d7-9412-e3bcd01f6692
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415930964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3415930964
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2632812075
Short name T284
Test name
Test status
Simulation time 321002831 ps
CPU time 3.31 seconds
Started Aug 07 05:29:51 PM PDT 24
Finished Aug 07 05:29:54 PM PDT 24
Peak memory 198668 kb
Host smart-8eb56c76-bc58-44a1-b3a6-633be4baacf3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632812075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2632812075
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2837771216
Short name T387
Test name
Test status
Simulation time 760955646 ps
CPU time 3.14 seconds
Started Aug 07 05:29:52 PM PDT 24
Finished Aug 07 05:29:55 PM PDT 24
Peak memory 196436 kb
Host smart-608bf530-5353-444b-9811-3b93241c3237
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837771216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2837771216
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1138417742
Short name T244
Test name
Test status
Simulation time 93375854 ps
CPU time 0.72 seconds
Started Aug 07 05:29:50 PM PDT 24
Finished Aug 07 05:29:51 PM PDT 24
Peak memory 196676 kb
Host smart-0c1ececc-3337-4a65-bf63-0fd36a32e99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138417742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1138417742
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2522826389
Short name T48
Test name
Test status
Simulation time 53834222 ps
CPU time 0.99 seconds
Started Aug 07 05:29:51 PM PDT 24
Finished Aug 07 05:29:52 PM PDT 24
Peak memory 196500 kb
Host smart-0c8a4341-250a-4cfe-9aee-950e2e20de48
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522826389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2522826389
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2029037423
Short name T293
Test name
Test status
Simulation time 515960987 ps
CPU time 6.22 seconds
Started Aug 07 05:29:51 PM PDT 24
Finished Aug 07 05:29:57 PM PDT 24
Peak memory 198512 kb
Host smart-3bbfaf97-a718-45b5-80a9-c89b7fbf0c66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029037423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2029037423
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2853940287
Short name T324
Test name
Test status
Simulation time 101107592 ps
CPU time 1.41 seconds
Started Aug 07 05:29:52 PM PDT 24
Finished Aug 07 05:29:53 PM PDT 24
Peak memory 197160 kb
Host smart-2e92a217-1892-4433-ab24-3681a6216853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853940287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2853940287
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2174700587
Short name T490
Test name
Test status
Simulation time 79893904 ps
CPU time 0.76 seconds
Started Aug 07 05:29:50 PM PDT 24
Finished Aug 07 05:29:51 PM PDT 24
Peak memory 196464 kb
Host smart-0c31c7c1-f3b7-411a-bf6c-c33554f3fa5f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174700587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2174700587
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3305209622
Short name T144
Test name
Test status
Simulation time 15933694558 ps
CPU time 172.82 seconds
Started Aug 07 05:29:50 PM PDT 24
Finished Aug 07 05:32:43 PM PDT 24
Peak memory 198732 kb
Host smart-75136a00-f47b-4230-a27b-8b5d9bb6f21e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305209622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3305209622
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1047634738
Short name T234
Test name
Test status
Simulation time 22634945 ps
CPU time 0.55 seconds
Started Aug 07 05:29:54 PM PDT 24
Finished Aug 07 05:29:55 PM PDT 24
Peak memory 194368 kb
Host smart-50527289-55e2-45ea-bdca-aad9d139a030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047634738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1047634738
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2628883277
Short name T215
Test name
Test status
Simulation time 47222130 ps
CPU time 0.9 seconds
Started Aug 07 05:29:57 PM PDT 24
Finished Aug 07 05:29:58 PM PDT 24
Peak memory 196384 kb
Host smart-01b7c5ee-9090-4ee9-8708-2997e6aa811a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628883277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2628883277
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1826211898
Short name T57
Test name
Test status
Simulation time 572028835 ps
CPU time 19.66 seconds
Started Aug 07 05:29:57 PM PDT 24
Finished Aug 07 05:30:17 PM PDT 24
Peak memory 196052 kb
Host smart-cfa67add-0f55-46fc-84d4-3a153bf5fe0f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826211898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1826211898
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3383438610
Short name T476
Test name
Test status
Simulation time 75435598 ps
CPU time 0.99 seconds
Started Aug 07 05:29:55 PM PDT 24
Finished Aug 07 05:29:56 PM PDT 24
Peak memory 198416 kb
Host smart-b574e79b-c795-4f67-92f8-1384e518ed4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383438610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3383438610
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.958853341
Short name T599
Test name
Test status
Simulation time 27719664 ps
CPU time 0.87 seconds
Started Aug 07 05:29:54 PM PDT 24
Finished Aug 07 05:29:55 PM PDT 24
Peak memory 197268 kb
Host smart-471c8060-33cb-4535-82ac-90ad90927e5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958853341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.958853341
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3055921403
Short name T539
Test name
Test status
Simulation time 106692788 ps
CPU time 2.79 seconds
Started Aug 07 05:29:54 PM PDT 24
Finished Aug 07 05:29:57 PM PDT 24
Peak memory 198652 kb
Host smart-2f869af3-977b-4ebb-bb12-4d65d4812312
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055921403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3055921403
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.2749480522
Short name T127
Test name
Test status
Simulation time 74857514 ps
CPU time 1.46 seconds
Started Aug 07 05:29:57 PM PDT 24
Finished Aug 07 05:29:58 PM PDT 24
Peak memory 196620 kb
Host smart-0543123e-2f01-4b7b-bd3c-f869d0afb6b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749480522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.2749480522
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.108430973
Short name T517
Test name
Test status
Simulation time 154860906 ps
CPU time 0.63 seconds
Started Aug 07 05:29:52 PM PDT 24
Finished Aug 07 05:29:53 PM PDT 24
Peak memory 194780 kb
Host smart-a47f6c85-3658-4175-a4ad-9fbd04551b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108430973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.108430973
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.429139922
Short name T374
Test name
Test status
Simulation time 26462344 ps
CPU time 0.97 seconds
Started Aug 07 05:29:54 PM PDT 24
Finished Aug 07 05:29:55 PM PDT 24
Peak memory 197288 kb
Host smart-be529906-2a5d-41a4-ab5a-9632ee5e9297
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429139922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.429139922
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3807569350
Short name T148
Test name
Test status
Simulation time 63815511 ps
CPU time 1.49 seconds
Started Aug 07 05:29:57 PM PDT 24
Finished Aug 07 05:29:58 PM PDT 24
Peak memory 198500 kb
Host smart-f035d4b4-e3bd-49fd-9de0-1520a6f7bff1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807569350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3807569350
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.344448453
Short name T429
Test name
Test status
Simulation time 258616155 ps
CPU time 1.21 seconds
Started Aug 07 05:29:51 PM PDT 24
Finished Aug 07 05:29:52 PM PDT 24
Peak memory 197268 kb
Host smart-40366c40-982b-487e-8868-dc86ee640acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344448453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.344448453
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2367750916
Short name T184
Test name
Test status
Simulation time 216027281 ps
CPU time 1.12 seconds
Started Aug 07 05:29:52 PM PDT 24
Finished Aug 07 05:29:53 PM PDT 24
Peak memory 196448 kb
Host smart-c97de4c5-eb50-48b4-bcc6-a9af895661b7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367750916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2367750916
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3704876486
Short name T178
Test name
Test status
Simulation time 4025046045 ps
CPU time 28.37 seconds
Started Aug 07 05:29:56 PM PDT 24
Finished Aug 07 05:30:25 PM PDT 24
Peak memory 198764 kb
Host smart-3feadb47-fb04-4bab-a7e5-2845c706eb0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704876486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3704876486
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.916266678
Short name T571
Test name
Test status
Simulation time 344315545684 ps
CPU time 1846.86 seconds
Started Aug 07 05:29:56 PM PDT 24
Finished Aug 07 06:00:43 PM PDT 24
Peak memory 198892 kb
Host smart-a55abf7d-9158-45b7-862c-a4f9b6070989
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=916266678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.916266678
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2267642884
Short name T640
Test name
Test status
Simulation time 12156171 ps
CPU time 0.61 seconds
Started Aug 07 05:30:03 PM PDT 24
Finished Aug 07 05:30:03 PM PDT 24
Peak memory 194428 kb
Host smart-edbc28ef-bf80-44d6-828d-668f7965df12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267642884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2267642884
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3882140787
Short name T265
Test name
Test status
Simulation time 59999524 ps
CPU time 0.92 seconds
Started Aug 07 05:29:56 PM PDT 24
Finished Aug 07 05:29:57 PM PDT 24
Peak memory 196428 kb
Host smart-abd85fe2-530f-4b6f-8f05-25d36090cc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882140787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3882140787
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2757253375
Short name T468
Test name
Test status
Simulation time 1414417075 ps
CPU time 20.26 seconds
Started Aug 07 05:30:03 PM PDT 24
Finished Aug 07 05:30:23 PM PDT 24
Peak memory 197544 kb
Host smart-12ab8be3-1a11-421c-9ae4-f03df226e982
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757253375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2757253375
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3934245888
Short name T451
Test name
Test status
Simulation time 26479661 ps
CPU time 0.71 seconds
Started Aug 07 05:30:02 PM PDT 24
Finished Aug 07 05:30:03 PM PDT 24
Peak memory 195940 kb
Host smart-006d3e0c-dc90-4b42-b4e8-8a64609ebe9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934245888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3934245888
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2704128365
Short name T128
Test name
Test status
Simulation time 38370869 ps
CPU time 0.73 seconds
Started Aug 07 05:29:58 PM PDT 24
Finished Aug 07 05:29:59 PM PDT 24
Peak memory 196528 kb
Host smart-41097962-f441-4a94-89bf-507767cab5ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704128365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2704128365
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1689438073
Short name T592
Test name
Test status
Simulation time 53165742 ps
CPU time 2.13 seconds
Started Aug 07 05:29:59 PM PDT 24
Finished Aug 07 05:30:02 PM PDT 24
Peak memory 196780 kb
Host smart-817ad1c5-6ad8-4bc0-b9e8-efccb57d8638
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689438073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1689438073
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1499046533
Short name T612
Test name
Test status
Simulation time 309413862 ps
CPU time 2.4 seconds
Started Aug 07 05:29:58 PM PDT 24
Finished Aug 07 05:30:01 PM PDT 24
Peak memory 197776 kb
Host smart-ea4eb3c2-51fb-432f-a004-225c2640758d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499046533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1499046533
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1597864584
Short name T174
Test name
Test status
Simulation time 25741631 ps
CPU time 0.79 seconds
Started Aug 07 05:29:54 PM PDT 24
Finished Aug 07 05:29:55 PM PDT 24
Peak memory 196008 kb
Host smart-394e1d91-65ff-4790-be15-21ed265b8480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597864584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1597864584
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3077169234
Short name T58
Test name
Test status
Simulation time 38606365 ps
CPU time 0.81 seconds
Started Aug 07 05:29:58 PM PDT 24
Finished Aug 07 05:29:59 PM PDT 24
Peak memory 195976 kb
Host smart-d4877c08-6d84-40aa-99db-4cda3be42dc1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077169234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3077169234
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2076551863
Short name T453
Test name
Test status
Simulation time 279712735 ps
CPU time 3.47 seconds
Started Aug 07 05:30:02 PM PDT 24
Finished Aug 07 05:30:06 PM PDT 24
Peak memory 198460 kb
Host smart-6e56c432-997c-49e2-a927-b85d39cee555
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076551863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2076551863
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.700646995
Short name T60
Test name
Test status
Simulation time 124702686 ps
CPU time 1.21 seconds
Started Aug 07 05:29:57 PM PDT 24
Finished Aug 07 05:29:59 PM PDT 24
Peak memory 196964 kb
Host smart-5a35420f-428f-42cb-a17c-b98baec6e449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700646995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.700646995
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.164687240
Short name T610
Test name
Test status
Simulation time 148380870 ps
CPU time 1.27 seconds
Started Aug 07 05:29:56 PM PDT 24
Finished Aug 07 05:29:57 PM PDT 24
Peak memory 197496 kb
Host smart-00183263-cb11-4ea4-b31a-d41772a67207
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164687240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.164687240
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1786005448
Short name T4
Test name
Test status
Simulation time 18651248227 ps
CPU time 213.18 seconds
Started Aug 07 05:30:05 PM PDT 24
Finished Aug 07 05:33:38 PM PDT 24
Peak memory 198708 kb
Host smart-e3c0d758-2c05-43c8-b922-ee1532f551fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786005448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1786005448
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.106446817
Short name T605
Test name
Test status
Simulation time 64514896 ps
CPU time 0.61 seconds
Started Aug 07 05:30:09 PM PDT 24
Finished Aug 07 05:30:10 PM PDT 24
Peak memory 195432 kb
Host smart-f561e4ba-6006-458b-aed8-21db38a7d4bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106446817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.106446817
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1614923313
Short name T572
Test name
Test status
Simulation time 55624750 ps
CPU time 1.02 seconds
Started Aug 07 05:30:02 PM PDT 24
Finished Aug 07 05:30:04 PM PDT 24
Peak memory 196564 kb
Host smart-a062c5ec-5f0e-49fa-84b8-71e6d53bd901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614923313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1614923313
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3216212106
Short name T253
Test name
Test status
Simulation time 655395354 ps
CPU time 21.66 seconds
Started Aug 07 05:30:03 PM PDT 24
Finished Aug 07 05:30:25 PM PDT 24
Peak memory 197012 kb
Host smart-198c8962-ebb3-4b49-8e32-54ee025aed91
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216212106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3216212106
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2099074807
Short name T191
Test name
Test status
Simulation time 347237910 ps
CPU time 0.96 seconds
Started Aug 07 05:30:09 PM PDT 24
Finished Aug 07 05:30:10 PM PDT 24
Peak memory 197204 kb
Host smart-7e68efc4-a5ca-4319-a988-3c735ecf94c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099074807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2099074807
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3344972017
Short name T241
Test name
Test status
Simulation time 119245676 ps
CPU time 0.83 seconds
Started Aug 07 05:30:00 PM PDT 24
Finished Aug 07 05:30:01 PM PDT 24
Peak memory 196008 kb
Host smart-fd1d621f-9f2b-4101-921b-62303757fef7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344972017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3344972017
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2260693384
Short name T335
Test name
Test status
Simulation time 382008165 ps
CPU time 2.13 seconds
Started Aug 07 05:30:03 PM PDT 24
Finished Aug 07 05:30:05 PM PDT 24
Peak memory 198696 kb
Host smart-54065bae-02f9-4f3e-822c-04fff283a1a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260693384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2260693384
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2331819335
Short name T402
Test name
Test status
Simulation time 493248315 ps
CPU time 2.94 seconds
Started Aug 07 05:30:09 PM PDT 24
Finished Aug 07 05:30:13 PM PDT 24
Peak memory 197544 kb
Host smart-ee0d5b0b-f8e1-4dd9-9f42-7c8994230eac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331819335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2331819335
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.2702499697
Short name T307
Test name
Test status
Simulation time 53896731 ps
CPU time 1.17 seconds
Started Aug 07 05:30:07 PM PDT 24
Finished Aug 07 05:30:08 PM PDT 24
Peak memory 197660 kb
Host smart-e80d8fa5-7050-42dc-8ad4-86d8426a33c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702499697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2702499697
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.4174900242
Short name T459
Test name
Test status
Simulation time 19436891 ps
CPU time 0.77 seconds
Started Aug 07 05:30:03 PM PDT 24
Finished Aug 07 05:30:04 PM PDT 24
Peak memory 196000 kb
Host smart-19db73d5-3692-4c5a-ac63-cfcdd80537fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174900242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.4174900242
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2850404959
Short name T196
Test name
Test status
Simulation time 140041186 ps
CPU time 2.46 seconds
Started Aug 07 05:30:04 PM PDT 24
Finished Aug 07 05:30:06 PM PDT 24
Peak memory 198572 kb
Host smart-bfcb7948-eebc-4d95-ac63-35d8e170551d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850404959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2850404959
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3081607596
Short name T705
Test name
Test status
Simulation time 74902882 ps
CPU time 1.28 seconds
Started Aug 07 05:30:05 PM PDT 24
Finished Aug 07 05:30:07 PM PDT 24
Peak memory 196084 kb
Host smart-631b2ae3-e13e-4f31-b22a-8aa6010ea7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081607596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3081607596
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.4078328601
Short name T584
Test name
Test status
Simulation time 52789606 ps
CPU time 0.96 seconds
Started Aug 07 05:29:59 PM PDT 24
Finished Aug 07 05:30:00 PM PDT 24
Peak memory 196396 kb
Host smart-3eb06297-3319-4734-944a-8d617f26de8f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078328601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.4078328601
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1522755477
Short name T633
Test name
Test status
Simulation time 39612189938 ps
CPU time 175.63 seconds
Started Aug 07 05:30:06 PM PDT 24
Finished Aug 07 05:33:02 PM PDT 24
Peak memory 198776 kb
Host smart-a6d5fa8e-764b-4a5d-ba20-9a340b7cc832
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522755477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1522755477
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.1480486021
Short name T522
Test name
Test status
Simulation time 62815204456 ps
CPU time 441.09 seconds
Started Aug 07 05:30:05 PM PDT 24
Finished Aug 07 05:37:26 PM PDT 24
Peak memory 198876 kb
Host smart-2e69896f-f51c-42ad-bddd-01d7376793b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1480486021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.1480486021
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2243796303
Short name T177
Test name
Test status
Simulation time 44242072 ps
CPU time 0.57 seconds
Started Aug 07 05:30:06 PM PDT 24
Finished Aug 07 05:30:07 PM PDT 24
Peak memory 194636 kb
Host smart-0832f94b-3878-43ab-9718-aad3a83ea1de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243796303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2243796303
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1634370029
Short name T309
Test name
Test status
Simulation time 68715090 ps
CPU time 0.67 seconds
Started Aug 07 05:30:09 PM PDT 24
Finished Aug 07 05:30:10 PM PDT 24
Peak memory 194576 kb
Host smart-fb5786a1-b2de-446f-8ba4-2f6eb96b4531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634370029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1634370029
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.727841685
Short name T546
Test name
Test status
Simulation time 149281061 ps
CPU time 5.06 seconds
Started Aug 07 05:30:08 PM PDT 24
Finished Aug 07 05:30:13 PM PDT 24
Peak memory 197776 kb
Host smart-6bad72bc-6abe-4dd4-927f-079b530d8d59
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727841685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.727841685
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1135030918
Short name T228
Test name
Test status
Simulation time 33843391 ps
CPU time 0.68 seconds
Started Aug 07 05:30:08 PM PDT 24
Finished Aug 07 05:30:08 PM PDT 24
Peak memory 195240 kb
Host smart-83176495-4dd8-41c1-abbb-7b03809910a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135030918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1135030918
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3652576801
Short name T615
Test name
Test status
Simulation time 33849087 ps
CPU time 0.97 seconds
Started Aug 07 05:30:08 PM PDT 24
Finished Aug 07 05:30:09 PM PDT 24
Peak memory 196668 kb
Host smart-4813fac9-1cde-4a44-9921-b2956ddd2610
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652576801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3652576801
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.802087305
Short name T699
Test name
Test status
Simulation time 200064170 ps
CPU time 2.17 seconds
Started Aug 07 05:30:05 PM PDT 24
Finished Aug 07 05:30:08 PM PDT 24
Peak memory 198592 kb
Host smart-2877c278-669d-49b7-963e-3736b83b1393
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802087305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.802087305
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.87609079
Short name T281
Test name
Test status
Simulation time 127397914 ps
CPU time 2.74 seconds
Started Aug 07 05:30:10 PM PDT 24
Finished Aug 07 05:30:13 PM PDT 24
Peak memory 197528 kb
Host smart-c52d98bb-027e-4537-98e9-508da6115ee9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87609079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.87609079
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.268312531
Short name T441
Test name
Test status
Simulation time 20621266 ps
CPU time 0.8 seconds
Started Aug 07 05:30:06 PM PDT 24
Finished Aug 07 05:30:07 PM PDT 24
Peak memory 196020 kb
Host smart-ac185432-6d41-4dac-910b-da936af58de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268312531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.268312531
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.158576479
Short name T274
Test name
Test status
Simulation time 268950216 ps
CPU time 1.26 seconds
Started Aug 07 05:30:08 PM PDT 24
Finished Aug 07 05:30:10 PM PDT 24
Peak memory 196424 kb
Host smart-26241da9-7e44-48f3-8456-6240dbb091d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158576479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.158576479
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1252250976
Short name T125
Test name
Test status
Simulation time 460472359 ps
CPU time 4.93 seconds
Started Aug 07 05:30:08 PM PDT 24
Finished Aug 07 05:30:13 PM PDT 24
Peak memory 198400 kb
Host smart-1e50af97-20e7-4307-91a6-7ab47a56c1fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252250976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1252250976
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1507601603
Short name T399
Test name
Test status
Simulation time 81928691 ps
CPU time 1.38 seconds
Started Aug 07 05:30:02 PM PDT 24
Finished Aug 07 05:30:04 PM PDT 24
Peak memory 196812 kb
Host smart-b1dc73f3-bd84-4edf-9854-168d2a3ea432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507601603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1507601603
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3407884937
Short name T676
Test name
Test status
Simulation time 60770695 ps
CPU time 1.29 seconds
Started Aug 07 05:30:03 PM PDT 24
Finished Aug 07 05:30:04 PM PDT 24
Peak memory 197120 kb
Host smart-82230b6a-7c5e-46a4-ab6b-c6c3a59dd5fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407884937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3407884937
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1162209043
Short name T462
Test name
Test status
Simulation time 22666701818 ps
CPU time 144.67 seconds
Started Aug 07 05:30:08 PM PDT 24
Finished Aug 07 05:32:33 PM PDT 24
Peak memory 198688 kb
Host smart-4e6266f5-bdee-4c69-8c19-a034686d1278
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162209043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1162209043
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.2092544833
Short name T55
Test name
Test status
Simulation time 416832813587 ps
CPU time 1674.81 seconds
Started Aug 07 05:30:10 PM PDT 24
Finished Aug 07 05:58:05 PM PDT 24
Peak memory 198796 kb
Host smart-743949ad-a1cd-4a15-8d47-9e2d9bad01b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2092544833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.2092544833
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2474724868
Short name T511
Test name
Test status
Simulation time 38747746 ps
CPU time 0.56 seconds
Started Aug 07 05:30:15 PM PDT 24
Finished Aug 07 05:30:16 PM PDT 24
Peak memory 194660 kb
Host smart-583c163b-5a76-4be6-9c8c-85f5e43755af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474724868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2474724868
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1209379523
Short name T556
Test name
Test status
Simulation time 64555123 ps
CPU time 0.65 seconds
Started Aug 07 05:30:15 PM PDT 24
Finished Aug 07 05:30:15 PM PDT 24
Peak memory 194436 kb
Host smart-2dfb8568-387e-4ccb-aabc-500cf285d7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209379523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1209379523
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.4176710035
Short name T409
Test name
Test status
Simulation time 975200927 ps
CPU time 4.87 seconds
Started Aug 07 05:30:15 PM PDT 24
Finished Aug 07 05:30:20 PM PDT 24
Peak memory 196792 kb
Host smart-e3c1049e-12c8-4642-8260-d956c842a52a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176710035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.4176710035
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2082171795
Short name T137
Test name
Test status
Simulation time 65022252 ps
CPU time 0.96 seconds
Started Aug 07 05:30:13 PM PDT 24
Finished Aug 07 05:30:14 PM PDT 24
Peak memory 197476 kb
Host smart-45f91329-d74b-4976-ad34-15b9f13cd358
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082171795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2082171795
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3690209971
Short name T176
Test name
Test status
Simulation time 93928344 ps
CPU time 0.82 seconds
Started Aug 07 05:30:13 PM PDT 24
Finished Aug 07 05:30:14 PM PDT 24
Peak memory 196200 kb
Host smart-8b6e6d6b-f1fd-4c13-a022-e81fdccbe7e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690209971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3690209971
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.262093355
Short name T417
Test name
Test status
Simulation time 607256627 ps
CPU time 3.07 seconds
Started Aug 07 05:30:14 PM PDT 24
Finished Aug 07 05:30:17 PM PDT 24
Peak memory 198552 kb
Host smart-bc5a5753-3d84-4ee0-a604-cc61d8101430
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262093355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.262093355
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3214728825
Short name T683
Test name
Test status
Simulation time 165406591 ps
CPU time 3.52 seconds
Started Aug 07 05:30:14 PM PDT 24
Finished Aug 07 05:30:17 PM PDT 24
Peak memory 196332 kb
Host smart-ac5b4bac-5c86-4a7a-bb33-97f71d867f3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214728825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3214728825
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.343775878
Short name T61
Test name
Test status
Simulation time 45063449 ps
CPU time 0.88 seconds
Started Aug 07 05:30:12 PM PDT 24
Finished Aug 07 05:30:13 PM PDT 24
Peak memory 196384 kb
Host smart-754e781d-2ecc-4cf4-8f95-beed93e5bdd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343775878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.343775878
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2668419995
Short name T458
Test name
Test status
Simulation time 51851662 ps
CPU time 0.84 seconds
Started Aug 07 05:30:12 PM PDT 24
Finished Aug 07 05:30:13 PM PDT 24
Peak memory 197020 kb
Host smart-d6cbdf45-dabe-45e9-ae2a-6bae6e0cfe71
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668419995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2668419995
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.522326071
Short name T292
Test name
Test status
Simulation time 496677715 ps
CPU time 5.75 seconds
Started Aug 07 05:30:13 PM PDT 24
Finished Aug 07 05:30:19 PM PDT 24
Peak memory 196924 kb
Host smart-685c3a20-4526-4215-b169-1ddb801166e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522326071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.522326071
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.536767691
Short name T484
Test name
Test status
Simulation time 134987861 ps
CPU time 1.13 seconds
Started Aug 07 05:30:05 PM PDT 24
Finished Aug 07 05:30:06 PM PDT 24
Peak memory 197044 kb
Host smart-de570e41-9fbc-4edb-96ea-09b5118e59d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536767691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.536767691
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2076547131
Short name T631
Test name
Test status
Simulation time 55977718 ps
CPU time 1.16 seconds
Started Aug 07 05:30:07 PM PDT 24
Finished Aug 07 05:30:08 PM PDT 24
Peak memory 197004 kb
Host smart-f9c6f29d-5502-4a54-82e6-133fa02babc8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076547131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2076547131
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2364085587
Short name T561
Test name
Test status
Simulation time 19788840680 ps
CPU time 233.33 seconds
Started Aug 07 05:30:13 PM PDT 24
Finished Aug 07 05:34:07 PM PDT 24
Peak memory 198752 kb
Host smart-f07bd2eb-de32-45af-ba5c-19e874aa00fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364085587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2364085587
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.2562209488
Short name T50
Test name
Test status
Simulation time 253921389635 ps
CPU time 760.02 seconds
Started Aug 07 05:30:18 PM PDT 24
Finished Aug 07 05:42:58 PM PDT 24
Peak memory 198876 kb
Host smart-c840595a-2e06-4581-adcf-2114f138a0cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2562209488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.2562209488
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1144460191
Short name T15
Test name
Test status
Simulation time 21240634 ps
CPU time 0.56 seconds
Started Aug 07 05:30:17 PM PDT 24
Finished Aug 07 05:30:18 PM PDT 24
Peak memory 194540 kb
Host smart-5a61d419-a53d-4381-a52a-2ddf22083def
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144460191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1144460191
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2086986244
Short name T136
Test name
Test status
Simulation time 58023231 ps
CPU time 0.77 seconds
Started Aug 07 05:30:12 PM PDT 24
Finished Aug 07 05:30:13 PM PDT 24
Peak memory 195956 kb
Host smart-a1b64733-2073-4923-a5b2-b6c8fed9feb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086986244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2086986244
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3532078586
Short name T285
Test name
Test status
Simulation time 95452194 ps
CPU time 4.84 seconds
Started Aug 07 05:30:12 PM PDT 24
Finished Aug 07 05:30:17 PM PDT 24
Peak memory 197628 kb
Host smart-479ff5fe-3833-42e4-b45b-d771f0225f28
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532078586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3532078586
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.4264515388
Short name T443
Test name
Test status
Simulation time 103645477 ps
CPU time 0.7 seconds
Started Aug 07 05:30:15 PM PDT 24
Finished Aug 07 05:30:15 PM PDT 24
Peak memory 195212 kb
Host smart-f73a279d-571a-4143-ae45-7d2c99be633a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264515388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.4264515388
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.4123373822
Short name T427
Test name
Test status
Simulation time 170371202 ps
CPU time 1.19 seconds
Started Aug 07 05:30:15 PM PDT 24
Finished Aug 07 05:30:17 PM PDT 24
Peak memory 196636 kb
Host smart-d211cb5d-1d47-4a80-914d-4b3d315f80dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123373822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.4123373822
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3587645147
Short name T223
Test name
Test status
Simulation time 165104328 ps
CPU time 2.81 seconds
Started Aug 07 05:30:17 PM PDT 24
Finished Aug 07 05:30:20 PM PDT 24
Peak memory 198604 kb
Host smart-44de4770-8fed-4ebc-b87b-b3ecd4d59cda
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587645147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3587645147
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3012373565
Short name T582
Test name
Test status
Simulation time 183874300 ps
CPU time 2.73 seconds
Started Aug 07 05:30:18 PM PDT 24
Finished Aug 07 05:30:21 PM PDT 24
Peak memory 197704 kb
Host smart-0e4eaaaf-2d80-4d72-b4f6-6b2e83b519fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012373565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3012373565
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.928731394
Short name T662
Test name
Test status
Simulation time 52857108 ps
CPU time 1.11 seconds
Started Aug 07 05:30:13 PM PDT 24
Finished Aug 07 05:30:14 PM PDT 24
Peak memory 197120 kb
Host smart-bdedece3-4e3c-4780-a051-e39f939d57c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928731394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.928731394
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3207618705
Short name T541
Test name
Test status
Simulation time 64205410 ps
CPU time 1.32 seconds
Started Aug 07 05:30:14 PM PDT 24
Finished Aug 07 05:30:15 PM PDT 24
Peak memory 197532 kb
Host smart-cf0c3021-bd54-4134-ad60-9ca76a86cbe1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207618705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3207618705
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.236099662
Short name T315
Test name
Test status
Simulation time 1342581581 ps
CPU time 5.83 seconds
Started Aug 07 05:30:18 PM PDT 24
Finished Aug 07 05:30:24 PM PDT 24
Peak memory 198560 kb
Host smart-186d8c0a-ead0-4bf2-bf6a-01d6e2a75900
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236099662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.236099662
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.2633656120
Short name T19
Test name
Test status
Simulation time 40805104 ps
CPU time 1.05 seconds
Started Aug 07 05:30:09 PM PDT 24
Finished Aug 07 05:30:10 PM PDT 24
Peak memory 195984 kb
Host smart-be6ad676-7e44-4636-af93-a3e62bec7ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633656120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.2633656120
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3092577360
Short name T619
Test name
Test status
Simulation time 61398984 ps
CPU time 0.78 seconds
Started Aug 07 05:30:12 PM PDT 24
Finished Aug 07 05:30:13 PM PDT 24
Peak memory 195836 kb
Host smart-8823c03c-092e-4bd1-a2c2-8e38a84be8b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092577360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3092577360
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.302750968
Short name T47
Test name
Test status
Simulation time 15023470625 ps
CPU time 183.53 seconds
Started Aug 07 05:30:14 PM PDT 24
Finished Aug 07 05:33:18 PM PDT 24
Peak memory 198712 kb
Host smart-f52e1245-1793-4074-8bd3-d2d62f861816
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302750968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.g
pio_stress_all.302750968
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.1527987716
Short name T397
Test name
Test status
Simulation time 88169693257 ps
CPU time 928.18 seconds
Started Aug 07 05:30:13 PM PDT 24
Finished Aug 07 05:45:41 PM PDT 24
Peak memory 198860 kb
Host smart-54c00da3-944f-4eb7-93b3-617031be7188
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1527987716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.1527987716
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3913437151
Short name T537
Test name
Test status
Simulation time 32719199 ps
CPU time 0.55 seconds
Started Aug 07 05:27:01 PM PDT 24
Finished Aug 07 05:27:01 PM PDT 24
Peak memory 195148 kb
Host smart-c46161ba-91d0-45c1-bd10-5247f87a4f7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913437151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3913437151
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3424137154
Short name T532
Test name
Test status
Simulation time 158096892 ps
CPU time 0.89 seconds
Started Aug 07 05:27:03 PM PDT 24
Finished Aug 07 05:27:04 PM PDT 24
Peak memory 196972 kb
Host smart-49d0096a-9344-4fb7-8a8b-dec839960145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424137154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3424137154
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1159385941
Short name T407
Test name
Test status
Simulation time 191002278 ps
CPU time 4.69 seconds
Started Aug 07 05:27:11 PM PDT 24
Finished Aug 07 05:27:16 PM PDT 24
Peak memory 197216 kb
Host smart-24581cff-1292-4b00-92d3-220802dace34
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159385941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1159385941
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3237269017
Short name T21
Test name
Test status
Simulation time 79376364 ps
CPU time 1.01 seconds
Started Aug 07 05:27:04 PM PDT 24
Finished Aug 07 05:27:06 PM PDT 24
Peak memory 198456 kb
Host smart-90d273e3-ffb0-49b7-9238-0f023245b22f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237269017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3237269017
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.2168141214
Short name T216
Test name
Test status
Simulation time 115032074 ps
CPU time 0.84 seconds
Started Aug 07 05:27:06 PM PDT 24
Finished Aug 07 05:27:07 PM PDT 24
Peak memory 197808 kb
Host smart-3efac6f7-38a5-49df-aa27-759723ec7d18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168141214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2168141214
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.931656434
Short name T421
Test name
Test status
Simulation time 75855197 ps
CPU time 0.97 seconds
Started Aug 07 05:27:01 PM PDT 24
Finished Aug 07 05:27:02 PM PDT 24
Peak memory 196808 kb
Host smart-ce032c2a-91e7-4056-b5d1-ae03fa14d8d4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931656434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.931656434
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2054485867
Short name T363
Test name
Test status
Simulation time 128614675 ps
CPU time 0.93 seconds
Started Aug 07 05:27:03 PM PDT 24
Finished Aug 07 05:27:04 PM PDT 24
Peak memory 196148 kb
Host smart-a1840e4f-d78d-437c-afa7-c65546b9d2c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054485867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2054485867
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3695100975
Short name T22
Test name
Test status
Simulation time 45977544 ps
CPU time 0.95 seconds
Started Aug 07 05:27:12 PM PDT 24
Finished Aug 07 05:27:13 PM PDT 24
Peak memory 197256 kb
Host smart-f35c719e-e00b-4150-b728-b911c1a89819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695100975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3695100975
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.396890890
Short name T212
Test name
Test status
Simulation time 102750764 ps
CPU time 0.8 seconds
Started Aug 07 05:27:10 PM PDT 24
Finished Aug 07 05:27:11 PM PDT 24
Peak memory 197904 kb
Host smart-04510091-a068-4907-8909-ac707bf2559e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396890890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.396890890
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.241047854
Short name T609
Test name
Test status
Simulation time 157445622 ps
CPU time 2.85 seconds
Started Aug 07 05:27:03 PM PDT 24
Finished Aug 07 05:27:06 PM PDT 24
Peak memory 198520 kb
Host smart-3db7ac15-0825-4923-885d-b1a25c32c231
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241047854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.241047854
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3298945803
Short name T560
Test name
Test status
Simulation time 41523172 ps
CPU time 1.06 seconds
Started Aug 07 05:27:01 PM PDT 24
Finished Aug 07 05:27:02 PM PDT 24
Peak memory 196160 kb
Host smart-b372e79b-b6e9-4ceb-a0c0-1806e9f5a766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298945803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3298945803
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1277599334
Short name T210
Test name
Test status
Simulation time 117203637 ps
CPU time 0.87 seconds
Started Aug 07 05:27:01 PM PDT 24
Finished Aug 07 05:27:02 PM PDT 24
Peak memory 195872 kb
Host smart-39b46457-2c8e-47a0-ac11-f434e3108dda
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277599334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1277599334
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1978065262
Short name T578
Test name
Test status
Simulation time 6982318133 ps
CPU time 70.55 seconds
Started Aug 07 05:27:03 PM PDT 24
Finished Aug 07 05:28:13 PM PDT 24
Peak memory 192280 kb
Host smart-cd87db8f-c9ab-4a4a-8205-51422fc0919e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978065262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1978065262
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.672943396
Short name T118
Test name
Test status
Simulation time 14122922 ps
CPU time 0.6 seconds
Started Aug 07 05:27:17 PM PDT 24
Finished Aug 07 05:27:17 PM PDT 24
Peak memory 194504 kb
Host smart-a452d128-7872-40fa-8343-0ea9e74e5f15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672943396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.672943396
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2761326654
Short name T154
Test name
Test status
Simulation time 48100105 ps
CPU time 0.85 seconds
Started Aug 07 05:27:04 PM PDT 24
Finished Aug 07 05:27:05 PM PDT 24
Peak memory 197296 kb
Host smart-a0e22464-852d-4905-b6ef-35998cba0c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761326654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2761326654
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.4048812045
Short name T518
Test name
Test status
Simulation time 1552787820 ps
CPU time 22.98 seconds
Started Aug 07 05:27:11 PM PDT 24
Finished Aug 07 05:27:34 PM PDT 24
Peak memory 198512 kb
Host smart-e9b4a79b-b808-4724-a44c-7d21ac891fd1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048812045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.4048812045
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2798593776
Short name T707
Test name
Test status
Simulation time 199654746 ps
CPU time 0.78 seconds
Started Aug 07 05:27:09 PM PDT 24
Finished Aug 07 05:27:10 PM PDT 24
Peak memory 196448 kb
Host smart-14104af9-363f-403f-b771-5e743a4fe12c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798593776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2798593776
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2818106380
Short name T709
Test name
Test status
Simulation time 86687152 ps
CPU time 0.92 seconds
Started Aug 07 05:27:17 PM PDT 24
Finished Aug 07 05:27:18 PM PDT 24
Peak memory 196428 kb
Host smart-489679f5-f402-42ef-b904-90d2c87a92de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818106380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2818106380
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3552187072
Short name T151
Test name
Test status
Simulation time 68185744 ps
CPU time 2.61 seconds
Started Aug 07 05:27:10 PM PDT 24
Finished Aug 07 05:27:13 PM PDT 24
Peak memory 198656 kb
Host smart-a54b01e8-d0f3-41e3-b901-8080dfb04cf8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552187072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3552187072
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.2984564250
Short name T474
Test name
Test status
Simulation time 562721678 ps
CPU time 3.08 seconds
Started Aug 07 05:27:16 PM PDT 24
Finished Aug 07 05:27:20 PM PDT 24
Peak memory 198648 kb
Host smart-0f944f27-e41a-476e-8a5e-cd2f873b2ee5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984564250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
2984564250
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1683944569
Short name T406
Test name
Test status
Simulation time 278074089 ps
CPU time 0.95 seconds
Started Aug 07 05:27:04 PM PDT 24
Finished Aug 07 05:27:05 PM PDT 24
Peak memory 197364 kb
Host smart-5a76f4b4-0c58-42bd-ae44-6b2634359261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683944569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1683944569
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.1255240210
Short name T380
Test name
Test status
Simulation time 130659148 ps
CPU time 1.06 seconds
Started Aug 07 05:27:06 PM PDT 24
Finished Aug 07 05:27:07 PM PDT 24
Peak memory 197332 kb
Host smart-195ec168-83b9-4613-ad41-5a2eba782711
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255240210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.1255240210
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2677945558
Short name T383
Test name
Test status
Simulation time 368869201 ps
CPU time 2.42 seconds
Started Aug 07 05:27:08 PM PDT 24
Finished Aug 07 05:27:11 PM PDT 24
Peak memory 198464 kb
Host smart-f1d1e4f0-c26a-406b-a180-e8fcfb67f82d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677945558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2677945558
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1295016673
Short name T25
Test name
Test status
Simulation time 87767944 ps
CPU time 0.97 seconds
Started Aug 07 05:27:07 PM PDT 24
Finished Aug 07 05:27:08 PM PDT 24
Peak memory 196364 kb
Host smart-1e7be524-2fb0-4a36-bc39-7499c080591e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295016673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1295016673
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.842788010
Short name T194
Test name
Test status
Simulation time 374251404 ps
CPU time 1.24 seconds
Started Aug 07 05:27:11 PM PDT 24
Finished Aug 07 05:27:12 PM PDT 24
Peak memory 197256 kb
Host smart-d59299b5-a6cc-4f95-add5-d4735d4837cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842788010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.842788010
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2095653304
Short name T346
Test name
Test status
Simulation time 6948246849 ps
CPU time 46.58 seconds
Started Aug 07 05:27:10 PM PDT 24
Finished Aug 07 05:27:56 PM PDT 24
Peak memory 198752 kb
Host smart-9b954ec0-4a88-4180-bd3e-7b9dabbcf3f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095653304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2095653304
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.4016213991
Short name T294
Test name
Test status
Simulation time 14974661 ps
CPU time 0.58 seconds
Started Aug 07 05:27:17 PM PDT 24
Finished Aug 07 05:27:18 PM PDT 24
Peak memory 194436 kb
Host smart-3a6636ea-c350-485b-90c3-29d130e11d1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016213991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.4016213991
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3986817886
Short name T348
Test name
Test status
Simulation time 75969453 ps
CPU time 0.68 seconds
Started Aug 07 05:27:09 PM PDT 24
Finished Aug 07 05:27:10 PM PDT 24
Peak memory 194700 kb
Host smart-331570bf-0db7-4a74-8c16-61be3a329d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986817886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3986817886
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.271004375
Short name T134
Test name
Test status
Simulation time 3763296009 ps
CPU time 23.66 seconds
Started Aug 07 05:27:09 PM PDT 24
Finished Aug 07 05:27:33 PM PDT 24
Peak memory 197628 kb
Host smart-6269ea43-b94d-41fb-abdc-5fea541605b6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271004375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress
.271004375
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.788649275
Short name T450
Test name
Test status
Simulation time 68426670 ps
CPU time 0.86 seconds
Started Aug 07 05:27:10 PM PDT 24
Finished Aug 07 05:27:11 PM PDT 24
Peak memory 196428 kb
Host smart-7e3f716b-f155-498c-894f-1eacd0a64ba2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788649275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.788649275
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.4104530573
Short name T452
Test name
Test status
Simulation time 107409611 ps
CPU time 1.47 seconds
Started Aug 07 05:27:09 PM PDT 24
Finished Aug 07 05:27:10 PM PDT 24
Peak memory 197092 kb
Host smart-797e1eb1-50f7-4957-bd7d-0ca1f41341f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104530573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.4104530573
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1725278506
Short name T322
Test name
Test status
Simulation time 55837342 ps
CPU time 2.19 seconds
Started Aug 07 05:27:08 PM PDT 24
Finished Aug 07 05:27:11 PM PDT 24
Peak memory 198656 kb
Host smart-e5c63691-c6ce-44a8-bdc7-8aa56f48db49
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725278506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1725278506
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1059888684
Short name T491
Test name
Test status
Simulation time 170162809 ps
CPU time 3.19 seconds
Started Aug 07 05:27:08 PM PDT 24
Finished Aug 07 05:27:11 PM PDT 24
Peak memory 197572 kb
Host smart-743098d6-28d0-4c5d-8e4c-6b0229c7843a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059888684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1059888684
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.592061154
Short name T62
Test name
Test status
Simulation time 90954580 ps
CPU time 0.98 seconds
Started Aug 07 05:27:13 PM PDT 24
Finished Aug 07 05:27:14 PM PDT 24
Peak memory 196500 kb
Host smart-589eab5b-1988-419d-b521-48a2953371cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592061154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.592061154
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.616729300
Short name T651
Test name
Test status
Simulation time 44483278 ps
CPU time 1.06 seconds
Started Aug 07 05:27:09 PM PDT 24
Finished Aug 07 05:27:11 PM PDT 24
Peak memory 196656 kb
Host smart-4cac7b7f-ad46-4295-860c-4de6075df31a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616729300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.616729300
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3176167681
Short name T438
Test name
Test status
Simulation time 79544501 ps
CPU time 3.24 seconds
Started Aug 07 05:27:13 PM PDT 24
Finished Aug 07 05:27:17 PM PDT 24
Peak memory 198576 kb
Host smart-fbf2d062-4391-4167-ad89-8853517f72e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176167681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3176167681
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.602307023
Short name T147
Test name
Test status
Simulation time 101926955 ps
CPU time 0.91 seconds
Started Aug 07 05:27:10 PM PDT 24
Finished Aug 07 05:27:11 PM PDT 24
Peak memory 196152 kb
Host smart-ed2d4ed8-c345-4c17-b8fa-aa1b9eb98085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602307023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.602307023
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.190029231
Short name T153
Test name
Test status
Simulation time 83560458 ps
CPU time 0.82 seconds
Started Aug 07 05:27:11 PM PDT 24
Finished Aug 07 05:27:12 PM PDT 24
Peak memory 195848 kb
Host smart-a379c875-9a41-4214-99fc-f029084d80d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190029231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.190029231
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1557208984
Short name T226
Test name
Test status
Simulation time 1736938489 ps
CPU time 49.7 seconds
Started Aug 07 05:27:10 PM PDT 24
Finished Aug 07 05:28:00 PM PDT 24
Peak memory 198520 kb
Host smart-61fc76e3-ad8a-4402-85cc-3f9a71cccd66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557208984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1557208984
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.58390854
Short name T34
Test name
Test status
Simulation time 21011116627 ps
CPU time 402.17 seconds
Started Aug 07 05:27:16 PM PDT 24
Finished Aug 07 05:33:59 PM PDT 24
Peak memory 198800 kb
Host smart-520abeed-e68e-4db5-86bd-845f202a1534
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=58390854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.58390854
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2105078079
Short name T27
Test name
Test status
Simulation time 12773077 ps
CPU time 0.57 seconds
Started Aug 07 05:27:18 PM PDT 24
Finished Aug 07 05:27:19 PM PDT 24
Peak memory 194692 kb
Host smart-d853c609-0bc6-4686-83f1-c07cb5dbae05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105078079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2105078079
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.3969762098
Short name T697
Test name
Test status
Simulation time 27169747 ps
CPU time 0.73 seconds
Started Aug 07 05:27:20 PM PDT 24
Finished Aug 07 05:27:20 PM PDT 24
Peak memory 195760 kb
Host smart-cb4ba8ea-c8bd-4516-a638-0c57a0a53479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969762098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.3969762098
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2715397016
Short name T344
Test name
Test status
Simulation time 183158827 ps
CPU time 4.81 seconds
Started Aug 07 05:27:19 PM PDT 24
Finished Aug 07 05:27:24 PM PDT 24
Peak memory 197084 kb
Host smart-9bccb190-32e6-4376-a4e9-0c057a561a83
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715397016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2715397016
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3398414474
Short name T318
Test name
Test status
Simulation time 277704488 ps
CPU time 0.85 seconds
Started Aug 07 05:27:17 PM PDT 24
Finished Aug 07 05:27:18 PM PDT 24
Peak memory 196572 kb
Host smart-561cf971-c8d9-4908-9b53-f5f7ca2e82bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398414474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3398414474
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.3233494755
Short name T621
Test name
Test status
Simulation time 380360960 ps
CPU time 1.28 seconds
Started Aug 07 05:27:21 PM PDT 24
Finished Aug 07 05:27:22 PM PDT 24
Peak memory 197512 kb
Host smart-45ea6f98-36c0-45db-ac49-29f214347199
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233494755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3233494755
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1811502823
Short name T277
Test name
Test status
Simulation time 175066360 ps
CPU time 3.44 seconds
Started Aug 07 05:27:21 PM PDT 24
Finished Aug 07 05:27:24 PM PDT 24
Peak memory 198352 kb
Host smart-2ca99d5e-01a5-42b7-a21a-b9a20d261c0f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811502823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1811502823
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3985695887
Short name T554
Test name
Test status
Simulation time 105078276 ps
CPU time 1.77 seconds
Started Aug 07 05:27:17 PM PDT 24
Finished Aug 07 05:27:19 PM PDT 24
Peak memory 196596 kb
Host smart-c6c2b9ab-c6a7-40a4-91d9-cc1620aef108
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985695887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3985695887
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2061940127
Short name T564
Test name
Test status
Simulation time 36262148 ps
CPU time 0.87 seconds
Started Aug 07 05:27:18 PM PDT 24
Finished Aug 07 05:27:19 PM PDT 24
Peak memory 197140 kb
Host smart-3f5adf8e-96ab-4a33-be61-0219024cea7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061940127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2061940127
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3945390304
Short name T549
Test name
Test status
Simulation time 349676673 ps
CPU time 0.79 seconds
Started Aug 07 05:27:19 PM PDT 24
Finished Aug 07 05:27:19 PM PDT 24
Peak memory 196912 kb
Host smart-2924e277-a62f-45a5-9ba0-5cd81c3d4025
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945390304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3945390304
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3251246984
Short name T433
Test name
Test status
Simulation time 137963341 ps
CPU time 3.05 seconds
Started Aug 07 05:27:18 PM PDT 24
Finished Aug 07 05:27:22 PM PDT 24
Peak memory 198340 kb
Host smart-213f874d-1213-4da6-8193-7236c5984abd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251246984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3251246984
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2278857057
Short name T692
Test name
Test status
Simulation time 355900321 ps
CPU time 0.94 seconds
Started Aug 07 05:27:17 PM PDT 24
Finished Aug 07 05:27:18 PM PDT 24
Peak memory 196196 kb
Host smart-410915d6-547e-4483-b095-45b7e1248c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278857057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2278857057
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.734162226
Short name T665
Test name
Test status
Simulation time 74620598 ps
CPU time 1.17 seconds
Started Aug 07 05:27:18 PM PDT 24
Finished Aug 07 05:27:19 PM PDT 24
Peak memory 196424 kb
Host smart-87d3d5c2-86ca-43e1-9854-9da544e30576
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734162226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.734162226
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2955866702
Short name T523
Test name
Test status
Simulation time 66069079113 ps
CPU time 139.39 seconds
Started Aug 07 05:27:18 PM PDT 24
Finished Aug 07 05:29:37 PM PDT 24
Peak memory 198764 kb
Host smart-e107756a-9548-4cfb-882c-cabe5e3b15a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955866702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2955866702
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.2368394816
Short name T373
Test name
Test status
Simulation time 197638549846 ps
CPU time 399.55 seconds
Started Aug 07 05:27:17 PM PDT 24
Finished Aug 07 05:33:57 PM PDT 24
Peak memory 198892 kb
Host smart-70609b0b-a620-4982-b464-53e389375a60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2368394816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.2368394816
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.4189213254
Short name T628
Test name
Test status
Simulation time 30231380 ps
CPU time 0.58 seconds
Started Aug 07 05:27:26 PM PDT 24
Finished Aug 07 05:27:26 PM PDT 24
Peak memory 194452 kb
Host smart-3ce20acf-8af0-467c-947c-8082fd7b0173
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189213254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.4189213254
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2196099957
Short name T371
Test name
Test status
Simulation time 54105176 ps
CPU time 0.74 seconds
Started Aug 07 05:27:24 PM PDT 24
Finished Aug 07 05:27:25 PM PDT 24
Peak memory 195632 kb
Host smart-32a14ce0-4a9e-4a29-aa52-5d91251a026b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196099957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2196099957
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2435076397
Short name T367
Test name
Test status
Simulation time 1555633753 ps
CPU time 21.37 seconds
Started Aug 07 05:27:23 PM PDT 24
Finished Aug 07 05:27:45 PM PDT 24
Peak memory 197348 kb
Host smart-3e648cbe-8126-4f62-81c0-eb2bd5924568
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435076397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2435076397
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2388338013
Short name T456
Test name
Test status
Simulation time 61433680 ps
CPU time 0.91 seconds
Started Aug 07 05:27:22 PM PDT 24
Finished Aug 07 05:27:23 PM PDT 24
Peak memory 198288 kb
Host smart-195fda4c-6e19-4b74-8016-f44447964cf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388338013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2388338013
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3163461853
Short name T604
Test name
Test status
Simulation time 24895508 ps
CPU time 0.81 seconds
Started Aug 07 05:27:25 PM PDT 24
Finished Aug 07 05:27:26 PM PDT 24
Peak memory 196224 kb
Host smart-f1f7e194-3e33-4869-b727-eab26f5b8c07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163461853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3163461853
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.974671494
Short name T333
Test name
Test status
Simulation time 107570326 ps
CPU time 2.12 seconds
Started Aug 07 05:27:23 PM PDT 24
Finished Aug 07 05:27:25 PM PDT 24
Peak memory 198696 kb
Host smart-ad8c8b25-5f61-479d-a193-f47ce0e1c4e3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974671494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.974671494
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2128612861
Short name T290
Test name
Test status
Simulation time 578149105 ps
CPU time 3.03 seconds
Started Aug 07 05:27:23 PM PDT 24
Finished Aug 07 05:27:26 PM PDT 24
Peak memory 197548 kb
Host smart-f57accc1-ee14-413c-ba56-64d6a28032d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128612861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2128612861
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.4109375458
Short name T29
Test name
Test status
Simulation time 52775259 ps
CPU time 1.05 seconds
Started Aug 07 05:27:24 PM PDT 24
Finished Aug 07 05:27:25 PM PDT 24
Peak memory 197208 kb
Host smart-a79d5a35-fbf5-4cbf-9315-abfaa0cdc341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109375458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.4109375458
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1397285724
Short name T703
Test name
Test status
Simulation time 37636383 ps
CPU time 0.9 seconds
Started Aug 07 05:27:27 PM PDT 24
Finished Aug 07 05:27:28 PM PDT 24
Peak memory 197176 kb
Host smart-5341bf62-64d4-4bfe-b866-8301284281dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397285724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1397285724
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.327226148
Short name T629
Test name
Test status
Simulation time 141127782 ps
CPU time 2.36 seconds
Started Aug 07 05:27:23 PM PDT 24
Finished Aug 07 05:27:26 PM PDT 24
Peak memory 198572 kb
Host smart-4fae76bd-1a06-4573-a382-990689f3284a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327226148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.327226148
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2600547184
Short name T403
Test name
Test status
Simulation time 271500945 ps
CPU time 0.83 seconds
Started Aug 07 05:27:15 PM PDT 24
Finished Aug 07 05:27:16 PM PDT 24
Peak memory 196508 kb
Host smart-e99b851a-7943-47b7-829b-b10fe30ff7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600547184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2600547184
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.887278445
Short name T146
Test name
Test status
Simulation time 135979302 ps
CPU time 1.07 seconds
Started Aug 07 05:27:17 PM PDT 24
Finished Aug 07 05:27:19 PM PDT 24
Peak memory 196108 kb
Host smart-52d2d084-deef-4892-a9d0-55b0a9cf33b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887278445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.887278445
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2918783202
Short name T5
Test name
Test status
Simulation time 16676863019 ps
CPU time 43.98 seconds
Started Aug 07 05:27:26 PM PDT 24
Finished Aug 07 05:28:10 PM PDT 24
Peak memory 198716 kb
Host smart-ef4e0ddd-7e53-4858-80ce-140f87f6a870
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918783202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2918783202
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3237579300
Short name T930
Test name
Test status
Simulation time 40953541 ps
CPU time 0.85 seconds
Started Aug 07 05:25:07 PM PDT 24
Finished Aug 07 05:25:08 PM PDT 24
Peak memory 195292 kb
Host smart-fac30d6f-fb15-4f29-8e9a-8010b744b40a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3237579300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3237579300
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.606092204
Short name T910
Test name
Test status
Simulation time 90224094 ps
CPU time 0.75 seconds
Started Aug 07 05:25:04 PM PDT 24
Finished Aug 07 05:25:05 PM PDT 24
Peak memory 195276 kb
Host smart-419a6a36-fbe3-46cc-92bd-42abb3e6b1ce
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606092204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.606092204
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2410864480
Short name T859
Test name
Test status
Simulation time 133679264 ps
CPU time 1 seconds
Started Aug 07 05:25:06 PM PDT 24
Finished Aug 07 05:25:08 PM PDT 24
Peak memory 197912 kb
Host smart-46fe4aa8-e433-4b06-be4c-dc145b9e62ba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2410864480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2410864480
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3551098621
Short name T862
Test name
Test status
Simulation time 119664105 ps
CPU time 0.89 seconds
Started Aug 07 05:25:08 PM PDT 24
Finished Aug 07 05:25:09 PM PDT 24
Peak memory 196604 kb
Host smart-c24cc7b7-6fcc-44e0-8ce4-bf5895c95ad0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551098621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3551098621
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.75962578
Short name T916
Test name
Test status
Simulation time 79274524 ps
CPU time 1.16 seconds
Started Aug 07 05:25:29 PM PDT 24
Finished Aug 07 05:25:30 PM PDT 24
Peak memory 198020 kb
Host smart-812608c7-9fd6-4915-9a53-16bce0281c0b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=75962578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.75962578
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3946237278
Short name T868
Test name
Test status
Simulation time 48432023 ps
CPU time 0.92 seconds
Started Aug 07 05:25:29 PM PDT 24
Finished Aug 07 05:25:30 PM PDT 24
Peak memory 196640 kb
Host smart-4a34e2e8-c6bd-4510-b4a1-deae80c116a8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946237278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3946237278
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3404492834
Short name T856
Test name
Test status
Simulation time 62093808 ps
CPU time 1.08 seconds
Started Aug 07 05:25:26 PM PDT 24
Finished Aug 07 05:25:28 PM PDT 24
Peak memory 196624 kb
Host smart-cc8120c5-9416-492c-b452-75a46a9b8dbc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3404492834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3404492834
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1154109307
Short name T898
Test name
Test status
Simulation time 109941515 ps
CPU time 1.1 seconds
Started Aug 07 05:25:29 PM PDT 24
Finished Aug 07 05:25:30 PM PDT 24
Peak memory 196604 kb
Host smart-eb3a6c64-e88d-4f14-acb4-bdc92937b087
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154109307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1154109307
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3406374634
Short name T855
Test name
Test status
Simulation time 77795374 ps
CPU time 1.39 seconds
Started Aug 07 05:25:35 PM PDT 24
Finished Aug 07 05:25:37 PM PDT 24
Peak memory 196804 kb
Host smart-f2650220-049b-457a-8f8a-90f63a7ec43c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3406374634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3406374634
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.151503234
Short name T924
Test name
Test status
Simulation time 110764153 ps
CPU time 1.05 seconds
Started Aug 07 05:25:35 PM PDT 24
Finished Aug 07 05:25:36 PM PDT 24
Peak memory 195856 kb
Host smart-d03ee207-2fb1-4d97-9ac3-ca082a2c8b9f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151503234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.151503234
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1324766549
Short name T908
Test name
Test status
Simulation time 38822159 ps
CPU time 1.16 seconds
Started Aug 07 05:25:42 PM PDT 24
Finished Aug 07 05:25:43 PM PDT 24
Peak memory 198104 kb
Host smart-90281ac6-cb49-4c40-a00a-3db9c137eff3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1324766549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1324766549
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2041011708
Short name T914
Test name
Test status
Simulation time 287050398 ps
CPU time 1.02 seconds
Started Aug 07 05:25:40 PM PDT 24
Finished Aug 07 05:25:41 PM PDT 24
Peak memory 196552 kb
Host smart-c81e93d6-50f8-4cb9-860b-39718cc33f63
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041011708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2041011708
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.664497625
Short name T903
Test name
Test status
Simulation time 44585416 ps
CPU time 1.16 seconds
Started Aug 07 05:25:41 PM PDT 24
Finished Aug 07 05:25:42 PM PDT 24
Peak memory 195720 kb
Host smart-704a8de4-3592-4d0e-813e-9cf76b6bc993
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=664497625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.664497625
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.402969157
Short name T888
Test name
Test status
Simulation time 174562648 ps
CPU time 1.21 seconds
Started Aug 07 05:25:41 PM PDT 24
Finished Aug 07 05:25:42 PM PDT 24
Peak memory 196876 kb
Host smart-b5246c13-d308-4973-be06-941b82440565
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402969157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.402969157
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3388059662
Short name T890
Test name
Test status
Simulation time 195882567 ps
CPU time 1.08 seconds
Started Aug 07 05:25:40 PM PDT 24
Finished Aug 07 05:25:41 PM PDT 24
Peak memory 196504 kb
Host smart-d7196b0f-264c-4942-ac60-bb104c7a620d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3388059662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3388059662
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4070965589
Short name T927
Test name
Test status
Simulation time 36050509 ps
CPU time 0.97 seconds
Started Aug 07 05:25:48 PM PDT 24
Finished Aug 07 05:25:49 PM PDT 24
Peak memory 195892 kb
Host smart-7d1e177a-1832-4df7-8db3-ab340c61fa8e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070965589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4070965589
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3624092642
Short name T882
Test name
Test status
Simulation time 224270479 ps
CPU time 1.14 seconds
Started Aug 07 05:25:45 PM PDT 24
Finished Aug 07 05:25:46 PM PDT 24
Peak memory 196624 kb
Host smart-4976bbec-fe1a-4af7-bed6-07d7b4f61729
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3624092642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3624092642
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2124085219
Short name T915
Test name
Test status
Simulation time 163294253 ps
CPU time 1.14 seconds
Started Aug 07 05:25:44 PM PDT 24
Finished Aug 07 05:25:45 PM PDT 24
Peak memory 196452 kb
Host smart-de2f9e0a-c234-4180-a3a5-99444dc72824
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124085219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2124085219
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1870907656
Short name T875
Test name
Test status
Simulation time 128223526 ps
CPU time 1.23 seconds
Started Aug 07 05:25:49 PM PDT 24
Finished Aug 07 05:25:50 PM PDT 24
Peak memory 196728 kb
Host smart-7aa1fb92-a931-42f0-afe4-0c0ca0da7a28
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1870907656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1870907656
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3858795050
Short name T886
Test name
Test status
Simulation time 28837779 ps
CPU time 0.87 seconds
Started Aug 07 05:25:47 PM PDT 24
Finished Aug 07 05:25:48 PM PDT 24
Peak memory 196648 kb
Host smart-7de9cd76-2ac3-438e-9420-ec772f7267af
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858795050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3858795050
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3595817425
Short name T891
Test name
Test status
Simulation time 351731102 ps
CPU time 1.19 seconds
Started Aug 07 05:25:44 PM PDT 24
Finished Aug 07 05:25:45 PM PDT 24
Peak memory 198040 kb
Host smart-c24afd6e-37de-4afe-98db-d2828d047574
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3595817425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3595817425
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3850107917
Short name T852
Test name
Test status
Simulation time 48316496 ps
CPU time 0.91 seconds
Started Aug 07 05:25:46 PM PDT 24
Finished Aug 07 05:25:48 PM PDT 24
Peak memory 195464 kb
Host smart-a4436515-1eac-4167-8e8b-6f4b4c8ce0a6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850107917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3850107917
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3026153004
Short name T925
Test name
Test status
Simulation time 199500309 ps
CPU time 1.02 seconds
Started Aug 07 05:25:47 PM PDT 24
Finished Aug 07 05:25:48 PM PDT 24
Peak memory 195712 kb
Host smart-a34d46a6-0088-4e4a-b112-c3346935ad58
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3026153004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3026153004
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3274585507
Short name T879
Test name
Test status
Simulation time 45560003 ps
CPU time 0.89 seconds
Started Aug 07 05:25:47 PM PDT 24
Finished Aug 07 05:25:48 PM PDT 24
Peak memory 196048 kb
Host smart-0b72981b-55e3-4169-8bbd-6e9307dfc55b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274585507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3274585507
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3980939269
Short name T900
Test name
Test status
Simulation time 223068878 ps
CPU time 0.93 seconds
Started Aug 07 05:25:10 PM PDT 24
Finished Aug 07 05:25:11 PM PDT 24
Peak memory 196672 kb
Host smart-fba129d0-af5e-453f-880d-40156a3ba557
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3980939269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3980939269
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2807594789
Short name T912
Test name
Test status
Simulation time 38615768 ps
CPU time 0.86 seconds
Started Aug 07 05:25:09 PM PDT 24
Finished Aug 07 05:25:10 PM PDT 24
Peak memory 196464 kb
Host smart-715e4f2e-474e-4cf6-a9d1-9174d5e74996
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807594789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2807594789
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.362123268
Short name T867
Test name
Test status
Simulation time 161813526 ps
CPU time 1.2 seconds
Started Aug 07 05:25:53 PM PDT 24
Finished Aug 07 05:25:54 PM PDT 24
Peak memory 195900 kb
Host smart-cf4e70d1-4c59-4cdd-9a41-3400c4a7351a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=362123268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.362123268
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.509745073
Short name T869
Test name
Test status
Simulation time 117116786 ps
CPU time 1.18 seconds
Started Aug 07 05:25:53 PM PDT 24
Finished Aug 07 05:25:54 PM PDT 24
Peak memory 196548 kb
Host smart-da6d231f-d8f4-4cdc-9a3d-ef444b676ec7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509745073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.509745073
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1956846068
Short name T945
Test name
Test status
Simulation time 78037751 ps
CPU time 1.11 seconds
Started Aug 07 05:25:53 PM PDT 24
Finished Aug 07 05:25:54 PM PDT 24
Peak memory 197964 kb
Host smart-4fa51525-fb8b-41ab-aaea-1d6080869559
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1956846068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1956846068
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2906401711
Short name T892
Test name
Test status
Simulation time 54967606 ps
CPU time 1.34 seconds
Started Aug 07 05:25:54 PM PDT 24
Finished Aug 07 05:25:55 PM PDT 24
Peak memory 196804 kb
Host smart-6ed0cbc4-1ac3-4a1c-a4d6-1d005408ef4a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906401711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2906401711
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3527630754
Short name T905
Test name
Test status
Simulation time 125180259 ps
CPU time 1.25 seconds
Started Aug 07 05:25:50 PM PDT 24
Finished Aug 07 05:25:51 PM PDT 24
Peak memory 195924 kb
Host smart-d9aaaeb0-445f-40c0-94cc-8ef299e67125
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3527630754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3527630754
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.598598543
Short name T883
Test name
Test status
Simulation time 326980207 ps
CPU time 1.4 seconds
Started Aug 07 05:25:52 PM PDT 24
Finished Aug 07 05:25:54 PM PDT 24
Peak memory 196392 kb
Host smart-efeb1ffa-d69c-45ea-b0e9-125a6164d0cc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598598543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.598598543
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3127517273
Short name T923
Test name
Test status
Simulation time 204640693 ps
CPU time 1.23 seconds
Started Aug 07 05:25:51 PM PDT 24
Finished Aug 07 05:25:53 PM PDT 24
Peak memory 197108 kb
Host smart-64efa104-6148-4d55-aecc-57dff530d22a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3127517273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3127517273
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1361412896
Short name T926
Test name
Test status
Simulation time 753467351 ps
CPU time 0.91 seconds
Started Aug 07 05:25:54 PM PDT 24
Finished Aug 07 05:25:55 PM PDT 24
Peak memory 195524 kb
Host smart-200dfd7c-d04e-4022-b16c-b2cf55c82d4a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361412896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1361412896
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2363705562
Short name T866
Test name
Test status
Simulation time 47448038 ps
CPU time 1.09 seconds
Started Aug 07 05:26:00 PM PDT 24
Finished Aug 07 05:26:01 PM PDT 24
Peak memory 196548 kb
Host smart-fca84296-a151-47aa-a662-dc46439ab4d2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2363705562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2363705562
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3979650394
Short name T876
Test name
Test status
Simulation time 88715054 ps
CPU time 1.5 seconds
Started Aug 07 05:25:56 PM PDT 24
Finished Aug 07 05:25:58 PM PDT 24
Peak memory 198032 kb
Host smart-a1f1bf7b-7bc9-413c-ab43-9da4b42d0b0e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979650394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3979650394
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2155239560
Short name T940
Test name
Test status
Simulation time 32029714 ps
CPU time 0.92 seconds
Started Aug 07 05:25:58 PM PDT 24
Finished Aug 07 05:25:59 PM PDT 24
Peak memory 196552 kb
Host smart-45eb3885-ae35-4ad9-b89d-5b0145f6eaa2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2155239560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2155239560
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3315309425
Short name T933
Test name
Test status
Simulation time 35700960 ps
CPU time 0.88 seconds
Started Aug 07 05:25:56 PM PDT 24
Finished Aug 07 05:25:57 PM PDT 24
Peak memory 196624 kb
Host smart-0a3e5c4a-de2d-4948-8572-0f565ed12e4d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315309425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3315309425
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.851035218
Short name T942
Test name
Test status
Simulation time 174076782 ps
CPU time 1.42 seconds
Started Aug 07 05:25:55 PM PDT 24
Finished Aug 07 05:25:57 PM PDT 24
Peak memory 196584 kb
Host smart-83f2b489-8fa5-4969-9618-49879a80466e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=851035218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.851035218
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4196103465
Short name T936
Test name
Test status
Simulation time 100553765 ps
CPU time 1.1 seconds
Started Aug 07 05:25:58 PM PDT 24
Finished Aug 07 05:25:59 PM PDT 24
Peak memory 196440 kb
Host smart-7c0c06b4-11ba-404d-a2b9-b4c3a2c074ff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196103465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4196103465
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.908045050
Short name T946
Test name
Test status
Simulation time 30633207 ps
CPU time 0.87 seconds
Started Aug 07 05:25:57 PM PDT 24
Finished Aug 07 05:25:58 PM PDT 24
Peak memory 195492 kb
Host smart-ccd0f19f-32c5-4aba-b62b-97f791cc29f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=908045050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.908045050
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1876362035
Short name T943
Test name
Test status
Simulation time 168596714 ps
CPU time 1.04 seconds
Started Aug 07 05:25:58 PM PDT 24
Finished Aug 07 05:25:59 PM PDT 24
Peak memory 198072 kb
Host smart-dce71cd6-c479-4d88-b696-b43d3aae788a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876362035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1876362035
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3790610939
Short name T874
Test name
Test status
Simulation time 49124107 ps
CPU time 1.28 seconds
Started Aug 07 05:26:04 PM PDT 24
Finished Aug 07 05:26:05 PM PDT 24
Peak memory 198028 kb
Host smart-93ee17e9-3f5e-4d9a-abb7-f43ecaf58684
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3790610939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3790610939
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.53791646
Short name T854
Test name
Test status
Simulation time 79255735 ps
CPU time 0.71 seconds
Started Aug 07 05:26:01 PM PDT 24
Finished Aug 07 05:26:01 PM PDT 24
Peak memory 194368 kb
Host smart-5fd7a3aa-2f41-46bc-a139-46429a3e9bf7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53791646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.53791646
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1604500469
Short name T881
Test name
Test status
Simulation time 28252979 ps
CPU time 0.94 seconds
Started Aug 07 05:26:02 PM PDT 24
Finished Aug 07 05:26:03 PM PDT 24
Peak memory 197868 kb
Host smart-1f60293e-4119-4b4a-9568-cd377b7bb666
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1604500469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1604500469
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2127581687
Short name T909
Test name
Test status
Simulation time 45288404 ps
CPU time 1.15 seconds
Started Aug 07 05:26:02 PM PDT 24
Finished Aug 07 05:26:03 PM PDT 24
Peak memory 197996 kb
Host smart-e7609441-71c1-4374-a1e5-0709aea16867
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127581687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2127581687
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3072080760
Short name T884
Test name
Test status
Simulation time 206629674 ps
CPU time 1.17 seconds
Started Aug 07 05:25:11 PM PDT 24
Finished Aug 07 05:25:12 PM PDT 24
Peak memory 196672 kb
Host smart-28b040d8-eaf9-4ead-bceb-2d13f6c93c30
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3072080760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.3072080760
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1925866464
Short name T919
Test name
Test status
Simulation time 132986606 ps
CPU time 1.43 seconds
Started Aug 07 05:25:09 PM PDT 24
Finished Aug 07 05:25:10 PM PDT 24
Peak memory 197400 kb
Host smart-cbf2c997-1ad0-4b24-b784-96c7733bc07c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925866464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1925866464
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3264253529
Short name T921
Test name
Test status
Simulation time 73305696 ps
CPU time 0.87 seconds
Started Aug 07 05:26:03 PM PDT 24
Finished Aug 07 05:26:04 PM PDT 24
Peak memory 196172 kb
Host smart-c7c9e3db-bc3b-4038-9fdf-bf0294cd6dba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3264253529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3264253529
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.265091157
Short name T928
Test name
Test status
Simulation time 210444136 ps
CPU time 1.59 seconds
Started Aug 07 05:26:02 PM PDT 24
Finished Aug 07 05:26:03 PM PDT 24
Peak memory 198064 kb
Host smart-b5fc461e-1cb0-4343-81d0-235b2304116d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265091157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.265091157
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.878024632
Short name T889
Test name
Test status
Simulation time 227754168 ps
CPU time 1.1 seconds
Started Aug 07 05:26:09 PM PDT 24
Finished Aug 07 05:26:10 PM PDT 24
Peak memory 196544 kb
Host smart-f6931972-9e02-44c9-87ae-036d9601ebd2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=878024632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.878024632
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2221908616
Short name T895
Test name
Test status
Simulation time 46177016 ps
CPU time 1.21 seconds
Started Aug 07 05:26:11 PM PDT 24
Finished Aug 07 05:26:13 PM PDT 24
Peak memory 196520 kb
Host smart-1b367b37-f58c-42cd-a42b-d3ccb48ed57b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221908616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2221908616
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.232037302
Short name T931
Test name
Test status
Simulation time 298956100 ps
CPU time 1.42 seconds
Started Aug 07 05:26:11 PM PDT 24
Finished Aug 07 05:26:13 PM PDT 24
Peak memory 196576 kb
Host smart-4fd383e4-a194-41e5-bb36-4316eb5d3a88
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=232037302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.232037302
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1693704513
Short name T871
Test name
Test status
Simulation time 38065429 ps
CPU time 0.82 seconds
Started Aug 07 05:26:09 PM PDT 24
Finished Aug 07 05:26:10 PM PDT 24
Peak memory 195520 kb
Host smart-d5556a42-ff16-42c1-a6cd-bec34283726b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693704513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1693704513
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3734009453
Short name T858
Test name
Test status
Simulation time 144348981 ps
CPU time 0.87 seconds
Started Aug 07 05:26:09 PM PDT 24
Finished Aug 07 05:26:10 PM PDT 24
Peak memory 195440 kb
Host smart-bb05033d-3275-4d08-9848-e028b2f166be
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3734009453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3734009453
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2292775584
Short name T851
Test name
Test status
Simulation time 53267198 ps
CPU time 1.15 seconds
Started Aug 07 05:26:09 PM PDT 24
Finished Aug 07 05:26:11 PM PDT 24
Peak memory 196440 kb
Host smart-d4e40fa3-43a6-435c-9b83-749333c5907f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292775584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2292775584
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1969803572
Short name T893
Test name
Test status
Simulation time 35927476 ps
CPU time 0.99 seconds
Started Aug 07 05:26:10 PM PDT 24
Finished Aug 07 05:26:11 PM PDT 24
Peak memory 195680 kb
Host smart-b77158d0-c1ab-4877-8287-f2c02875b0e9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1969803572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1969803572
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3775058590
Short name T904
Test name
Test status
Simulation time 242798103 ps
CPU time 1.12 seconds
Started Aug 07 05:26:09 PM PDT 24
Finished Aug 07 05:26:11 PM PDT 24
Peak memory 195588 kb
Host smart-03e54029-818a-4756-8e3a-16e6dae7704f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775058590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3775058590
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.264561338
Short name T864
Test name
Test status
Simulation time 371976452 ps
CPU time 1.4 seconds
Started Aug 07 05:26:09 PM PDT 24
Finished Aug 07 05:26:11 PM PDT 24
Peak memory 196712 kb
Host smart-457a725c-962f-429c-8090-65a664f27872
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=264561338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.264561338
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1226590293
Short name T870
Test name
Test status
Simulation time 66824405 ps
CPU time 1.22 seconds
Started Aug 07 05:26:09 PM PDT 24
Finished Aug 07 05:26:11 PM PDT 24
Peak memory 196948 kb
Host smart-45834a6f-007c-4ad4-bdf1-89e05a35793e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226590293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1226590293
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3033267484
Short name T922
Test name
Test status
Simulation time 112410646 ps
CPU time 1.12 seconds
Started Aug 07 05:26:16 PM PDT 24
Finished Aug 07 05:26:17 PM PDT 24
Peak memory 196676 kb
Host smart-fd7d40c6-bbbf-4cb0-bf4a-aa64d7cddff0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3033267484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3033267484
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2460627853
Short name T860
Test name
Test status
Simulation time 192597163 ps
CPU time 1.44 seconds
Started Aug 07 05:26:17 PM PDT 24
Finished Aug 07 05:26:19 PM PDT 24
Peak memory 196904 kb
Host smart-fc2e0f4a-c667-474a-a93b-e4a9c6bf5aef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460627853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2460627853
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3359736140
Short name T863
Test name
Test status
Simulation time 117013852 ps
CPU time 1.21 seconds
Started Aug 07 05:26:17 PM PDT 24
Finished Aug 07 05:26:18 PM PDT 24
Peak memory 196616 kb
Host smart-3837adbe-d3d3-4aef-80a6-97c72e08e7fd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3359736140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3359736140
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2070501409
Short name T938
Test name
Test status
Simulation time 91257199 ps
CPU time 0.85 seconds
Started Aug 07 05:26:15 PM PDT 24
Finished Aug 07 05:26:16 PM PDT 24
Peak memory 197724 kb
Host smart-c7a2f5b3-16ff-4d91-a357-cf98c6203ac5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070501409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2070501409
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.152310500
Short name T932
Test name
Test status
Simulation time 67374127 ps
CPU time 1.29 seconds
Started Aug 07 05:26:17 PM PDT 24
Finished Aug 07 05:26:18 PM PDT 24
Peak memory 197312 kb
Host smart-e6b5a4b8-f652-4b4c-b12f-bad062a6cc11
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=152310500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.152310500
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2436450062
Short name T896
Test name
Test status
Simulation time 70542028 ps
CPU time 1.12 seconds
Started Aug 07 05:26:17 PM PDT 24
Finished Aug 07 05:26:19 PM PDT 24
Peak memory 198104 kb
Host smart-abdeb723-12a2-409a-b62a-fcad074314ac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436450062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2436450062
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1791111775
Short name T894
Test name
Test status
Simulation time 159460017 ps
CPU time 0.81 seconds
Started Aug 07 05:26:14 PM PDT 24
Finished Aug 07 05:26:15 PM PDT 24
Peak memory 195280 kb
Host smart-99cffb6b-32d4-4359-b0b6-9da3fc395557
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1791111775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1791111775
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3276554412
Short name T907
Test name
Test status
Simulation time 70377099 ps
CPU time 0.97 seconds
Started Aug 07 05:26:20 PM PDT 24
Finished Aug 07 05:26:21 PM PDT 24
Peak memory 198060 kb
Host smart-0e116220-c4eb-4959-b5f1-71eae4b7425d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276554412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3276554412
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2060290769
Short name T897
Test name
Test status
Simulation time 34046794 ps
CPU time 1.11 seconds
Started Aug 07 05:25:21 PM PDT 24
Finished Aug 07 05:25:22 PM PDT 24
Peak memory 196548 kb
Host smart-4b66a090-0e50-4c49-94f9-720d34fed757
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2060290769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2060290769
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.916085327
Short name T941
Test name
Test status
Simulation time 267202392 ps
CPU time 1.15 seconds
Started Aug 07 05:25:21 PM PDT 24
Finished Aug 07 05:25:22 PM PDT 24
Peak memory 196536 kb
Host smart-bd139184-1a07-4161-a18e-08a3eafe39be
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916085327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.916085327
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1867406099
Short name T906
Test name
Test status
Simulation time 55679210 ps
CPU time 0.79 seconds
Started Aug 07 05:26:21 PM PDT 24
Finished Aug 07 05:26:22 PM PDT 24
Peak memory 196060 kb
Host smart-74402876-afd0-4fb9-9599-0ff696edb006
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1867406099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1867406099
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.524721197
Short name T913
Test name
Test status
Simulation time 475989689 ps
CPU time 1.22 seconds
Started Aug 07 05:26:16 PM PDT 24
Finished Aug 07 05:26:18 PM PDT 24
Peak memory 196812 kb
Host smart-e30d468a-59ec-4573-b7c6-4408b4ab18dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524721197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.524721197
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3029313092
Short name T937
Test name
Test status
Simulation time 30082797 ps
CPU time 0.85 seconds
Started Aug 07 05:26:18 PM PDT 24
Finished Aug 07 05:26:19 PM PDT 24
Peak memory 196504 kb
Host smart-646d70e0-da22-4283-868a-22f113541dda
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3029313092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3029313092
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.620115386
Short name T878
Test name
Test status
Simulation time 207333423 ps
CPU time 0.98 seconds
Started Aug 07 05:26:22 PM PDT 24
Finished Aug 07 05:26:23 PM PDT 24
Peak memory 196648 kb
Host smart-bb2d6e53-1fb0-410a-af7b-f453f4bbbe68
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620115386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.620115386
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1628503131
Short name T911
Test name
Test status
Simulation time 90073187 ps
CPU time 1.36 seconds
Started Aug 07 05:26:19 PM PDT 24
Finished Aug 07 05:26:21 PM PDT 24
Peak memory 196704 kb
Host smart-d1419fb7-d6df-4b1c-8ed4-16c1f24ed288
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1628503131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1628503131
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1208078845
Short name T877
Test name
Test status
Simulation time 800563027 ps
CPU time 1.2 seconds
Started Aug 07 05:26:16 PM PDT 24
Finished Aug 07 05:26:17 PM PDT 24
Peak memory 196816 kb
Host smart-5b49d965-163e-49db-8e96-1788d086a0c6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208078845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1208078845
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1423023236
Short name T918
Test name
Test status
Simulation time 83678307 ps
CPU time 1.13 seconds
Started Aug 07 05:26:23 PM PDT 24
Finished Aug 07 05:26:25 PM PDT 24
Peak memory 196768 kb
Host smart-465223d3-4126-4971-bc78-16e3adc8d8f7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1423023236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1423023236
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1836333702
Short name T920
Test name
Test status
Simulation time 84998329 ps
CPU time 0.91 seconds
Started Aug 07 05:26:18 PM PDT 24
Finished Aug 07 05:26:19 PM PDT 24
Peak memory 198036 kb
Host smart-9512ccc8-667e-40ce-81d8-ce51b986917e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836333702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1836333702
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1399439085
Short name T861
Test name
Test status
Simulation time 218594858 ps
CPU time 1.04 seconds
Started Aug 07 05:26:20 PM PDT 24
Finished Aug 07 05:26:21 PM PDT 24
Peak memory 195688 kb
Host smart-c9f2d1ff-e775-42ad-a6f3-b7db54f4d216
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1399439085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1399439085
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4287436341
Short name T850
Test name
Test status
Simulation time 125017589 ps
CPU time 1.01 seconds
Started Aug 07 05:26:19 PM PDT 24
Finished Aug 07 05:26:20 PM PDT 24
Peak memory 195744 kb
Host smart-9faec9b4-25d1-4c6a-9026-09d528e2d9b8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287436341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4287436341
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.22662994
Short name T872
Test name
Test status
Simulation time 178559283 ps
CPU time 0.84 seconds
Started Aug 07 05:26:20 PM PDT 24
Finished Aug 07 05:26:21 PM PDT 24
Peak memory 195508 kb
Host smart-c1ed8f2f-a2c4-4777-a85b-83e03748c577
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=22662994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.22662994
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1944292832
Short name T880
Test name
Test status
Simulation time 106278703 ps
CPU time 0.89 seconds
Started Aug 07 05:26:20 PM PDT 24
Finished Aug 07 05:26:21 PM PDT 24
Peak memory 196596 kb
Host smart-ccf3e6dc-0ed4-47ed-a860-7802888a552d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944292832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1944292832
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2292265608
Short name T934
Test name
Test status
Simulation time 41342325 ps
CPU time 0.87 seconds
Started Aug 07 05:26:24 PM PDT 24
Finished Aug 07 05:26:25 PM PDT 24
Peak memory 195516 kb
Host smart-84f922b2-e568-432f-9dab-a48fa5718b55
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2292265608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2292265608
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2927499237
Short name T901
Test name
Test status
Simulation time 114906137 ps
CPU time 0.89 seconds
Started Aug 07 05:26:26 PM PDT 24
Finished Aug 07 05:26:27 PM PDT 24
Peak memory 196592 kb
Host smart-0beb8e00-4670-455f-87eb-8315805cd4da
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927499237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2927499237
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3826365697
Short name T885
Test name
Test status
Simulation time 206331046 ps
CPU time 1.01 seconds
Started Aug 07 05:26:26 PM PDT 24
Finished Aug 07 05:26:27 PM PDT 24
Peak memory 195788 kb
Host smart-35d2a365-dfd7-41e7-9bdb-470f1353ec22
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3826365697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3826365697
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.509239906
Short name T865
Test name
Test status
Simulation time 89029639 ps
CPU time 1.18 seconds
Started Aug 07 05:26:25 PM PDT 24
Finished Aug 07 05:26:26 PM PDT 24
Peak memory 196624 kb
Host smart-0951da49-73e9-4d72-ac85-aa9c8f5c2310
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509239906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.509239906
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.407562044
Short name T873
Test name
Test status
Simulation time 39963656 ps
CPU time 0.85 seconds
Started Aug 07 05:26:23 PM PDT 24
Finished Aug 07 05:26:24 PM PDT 24
Peak memory 195316 kb
Host smart-3d35bcb6-ffe1-4675-839d-8c4889979d59
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=407562044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.407562044
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1459934140
Short name T853
Test name
Test status
Simulation time 41667577 ps
CPU time 0.86 seconds
Started Aug 07 05:26:28 PM PDT 24
Finished Aug 07 05:26:29 PM PDT 24
Peak memory 196500 kb
Host smart-01cd4227-7ab1-469b-a4e2-2a9d774fd6dd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459934140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1459934140
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2597614925
Short name T947
Test name
Test status
Simulation time 134968863 ps
CPU time 1.05 seconds
Started Aug 07 05:26:24 PM PDT 24
Finished Aug 07 05:26:25 PM PDT 24
Peak memory 195888 kb
Host smart-8a30f040-d2f2-4f29-abd5-be0a21ff131c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2597614925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2597614925
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3940183432
Short name T902
Test name
Test status
Simulation time 61499830 ps
CPU time 0.9 seconds
Started Aug 07 05:26:28 PM PDT 24
Finished Aug 07 05:26:29 PM PDT 24
Peak memory 196628 kb
Host smart-2e982d21-d6c5-41d8-bf48-17b38cb7ee0c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940183432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3940183432
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.485570076
Short name T899
Test name
Test status
Simulation time 65110681 ps
CPU time 1.11 seconds
Started Aug 07 05:25:29 PM PDT 24
Finished Aug 07 05:25:30 PM PDT 24
Peak memory 195932 kb
Host smart-38f5ebe1-6138-4810-a6f8-14642cc265d0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=485570076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.485570076
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2761770610
Short name T949
Test name
Test status
Simulation time 381429341 ps
CPU time 1.38 seconds
Started Aug 07 05:25:29 PM PDT 24
Finished Aug 07 05:25:31 PM PDT 24
Peak memory 196496 kb
Host smart-c152c332-53db-43c9-bb90-c0ee2aedb3fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761770610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2761770610
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.679905073
Short name T948
Test name
Test status
Simulation time 196440645 ps
CPU time 1.11 seconds
Started Aug 07 05:25:29 PM PDT 24
Finished Aug 07 05:25:30 PM PDT 24
Peak memory 196396 kb
Host smart-82a32fa7-e7bd-4303-ad34-8d362db033de
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=679905073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.679905073
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1587210773
Short name T929
Test name
Test status
Simulation time 495350798 ps
CPU time 1.11 seconds
Started Aug 07 05:25:24 PM PDT 24
Finished Aug 07 05:25:26 PM PDT 24
Peak memory 196724 kb
Host smart-0c0d5d26-d8fc-4772-8939-3420f7e39d1c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587210773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1587210773
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1856251227
Short name T935
Test name
Test status
Simulation time 140048335 ps
CPU time 1.32 seconds
Started Aug 07 05:25:30 PM PDT 24
Finished Aug 07 05:25:32 PM PDT 24
Peak memory 196824 kb
Host smart-65884124-10f4-4011-ba93-ec0ce4e5a7b2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1856251227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1856251227
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2138387130
Short name T939
Test name
Test status
Simulation time 244295328 ps
CPU time 1 seconds
Started Aug 07 05:25:21 PM PDT 24
Finished Aug 07 05:25:23 PM PDT 24
Peak memory 196676 kb
Host smart-3b60a99d-f52f-4b23-8699-eb51880bb7cf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138387130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2138387130
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2172286417
Short name T857
Test name
Test status
Simulation time 127888522 ps
CPU time 1.17 seconds
Started Aug 07 05:25:28 PM PDT 24
Finished Aug 07 05:25:29 PM PDT 24
Peak memory 196536 kb
Host smart-586ea6ce-f2f9-40d1-af09-3074e26701c5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2172286417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.2172286417
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2674251667
Short name T944
Test name
Test status
Simulation time 198271345 ps
CPU time 1.1 seconds
Started Aug 07 05:25:26 PM PDT 24
Finished Aug 07 05:25:27 PM PDT 24
Peak memory 196528 kb
Host smart-424ae625-6e30-4c63-896d-5b51e8664c98
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674251667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2674251667
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3380523861
Short name T917
Test name
Test status
Simulation time 59414208 ps
CPU time 1.21 seconds
Started Aug 07 05:25:28 PM PDT 24
Finished Aug 07 05:25:29 PM PDT 24
Peak memory 197968 kb
Host smart-418ed42d-473b-4ecb-9337-11a70e040e85
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3380523861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3380523861
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2045673368
Short name T887
Test name
Test status
Simulation time 87837754 ps
CPU time 1.19 seconds
Started Aug 07 05:25:29 PM PDT 24
Finished Aug 07 05:25:31 PM PDT 24
Peak memory 196728 kb
Host smart-b97c3da8-6ff2-41e8-a970-aefb6deb5540
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045673368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2045673368
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%