Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3697519	1			T18	1		T19	1		T20	83
all_pins[1]	3697519	1			T18	1		T19	1		T20	83
all_pins[2]	3697519	1			T18	1		T19	1		T20	83
all_pins[3]	3697519	1			T18	1		T19	1		T20	83
all_pins[4]	3697519	1			T18	1		T19	1		T20	83
all_pins[5]	3697519	1			T18	1		T19	1		T20	83
all_pins[6]	3697519	1			T18	1		T19	1		T20	83
all_pins[7]	3697519	1			T18	1		T19	1		T20	83
all_pins[8]	3697519	1			T18	1		T19	1		T20	83
all_pins[9]	3697519	1			T18	1		T19	1		T20	83
all_pins[10]	3697519	1			T18	1		T19	1		T20	83
all_pins[11]	3697519	1			T18	1		T19	1		T20	83
all_pins[12]	3697519	1			T18	1		T19	1		T20	83
all_pins[13]	3697519	1			T18	1		T19	1		T20	83
all_pins[14]	3697519	1			T18	1		T19	1		T20	83
all_pins[15]	3697519	1			T18	1		T19	1		T20	83
all_pins[16]	3697519	1			T18	1		T19	1		T20	83
all_pins[17]	3697519	1			T18	1		T19	1		T20	83
all_pins[18]	3697519	1			T18	1		T19	1		T20	83
all_pins[19]	3697519	1			T18	1		T19	1		T20	83
all_pins[20]	3697519	1			T18	1		T19	1		T20	83
all_pins[21]	3697519	1			T18	1		T19	1		T20	83
all_pins[22]	3697519	1			T18	1		T19	1		T20	83
all_pins[23]	3697519	1			T18	1		T19	1		T20	83
all_pins[24]	3697519	1			T18	1		T19	1		T20	83
all_pins[25]	3697519	1			T18	1		T19	1		T20	83
all_pins[26]	3697519	1			T18	1		T19	1		T20	83
all_pins[27]	3697519	1			T18	1		T19	1		T20	83
all_pins[28]	3697519	1			T18	1		T19	1		T20	83
all_pins[29]	3697519	1			T18	1		T19	1		T20	83
all_pins[30]	3697519	1			T18	1		T19	1		T20	83
all_pins[31]	3697519	1			T18	1		T19	1		T20	83

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	73513880	1			T18	32		T19	32		T20	1329
values[0x1]	44806728	1			T20	1327		T23	1082		T1	2021
transitions[0x0=>0x1]	26849934	1			T20	658		T23	558		T1	1197
transitions[0x1=>0x0]	26849776	1			T20	657		T23	557		T1	1197

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2299725	1			T18	1		T19	1		T20	46
all_pins[0]	values[0x1]	1397794	1			T20	37		T23	34		T1	63
all_pins[0]	transitions[0x0=>0x1]	865567	1			T20	16		T23	19		T1	35
all_pins[0]	transitions[0x1=>0x0]	866796	1			T20	25		T23	14		T1	15
all_pins[1]	values[0x0]	2294596	1			T18	1		T19	1		T20	42
all_pins[1]	values[0x1]	1402923	1			T20	41		T23	37		T1	51
all_pins[1]	transitions[0x0=>0x1]	841097	1			T20	26		T23	21		T1	33
all_pins[1]	transitions[0x1=>0x0]	835968	1			T20	22		T23	18		T1	45
all_pins[2]	values[0x0]	2300459	1			T18	1		T19	1		T20	38
all_pins[2]	values[0x1]	1397060	1			T20	45		T23	38		T1	78
all_pins[2]	transitions[0x0=>0x1]	833773	1			T20	21		T23	16		T1	45
all_pins[2]	transitions[0x1=>0x0]	839636	1			T20	17		T23	15		T1	18
all_pins[3]	values[0x0]	2298710	1			T18	1		T19	1		T20	37
all_pins[3]	values[0x1]	1398809	1			T20	46		T23	33		T1	71
all_pins[3]	transitions[0x0=>0x1]	837952	1			T20	20		T23	19		T1	31
all_pins[3]	transitions[0x1=>0x0]	836203	1			T20	19		T23	24		T1	38
all_pins[4]	values[0x0]	2293770	1			T18	1		T19	1		T20	36
all_pins[4]	values[0x1]	1403749	1			T20	47		T23	37		T1	85
all_pins[4]	transitions[0x0=>0x1]	842142	1			T20	17		T23	23		T1	49
all_pins[4]	transitions[0x1=>0x0]	837202	1			T20	16		T23	19		T1	35
all_pins[5]	values[0x0]	2300144	1			T18	1		T19	1		T20	41
all_pins[5]	values[0x1]	1397375	1			T20	42		T23	34		T1	56
all_pins[5]	transitions[0x0=>0x1]	832832	1			T20	14		T23	17		T1	17
all_pins[5]	transitions[0x1=>0x0]	839206	1			T20	19		T23	20		T1	46
all_pins[6]	values[0x0]	2294005	1			T18	1		T19	1		T20	35
all_pins[6]	values[0x1]	1403514	1			T20	48		T23	35		T1	69
all_pins[6]	transitions[0x0=>0x1]	841191	1			T20	24		T23	16		T1	31
all_pins[6]	transitions[0x1=>0x0]	835052	1			T20	18		T23	15		T1	18
all_pins[7]	values[0x0]	2296401	1			T18	1		T19	1		T20	35
all_pins[7]	values[0x1]	1401118	1			T20	48		T23	31		T1	80
all_pins[7]	transitions[0x0=>0x1]	837056	1			T20	23		T23	13		T1	55
all_pins[7]	transitions[0x1=>0x0]	839452	1			T20	23		T23	17		T1	44
all_pins[8]	values[0x0]	2296148	1			T18	1		T19	1		T20	44
all_pins[8]	values[0x1]	1401371	1			T20	39		T23	39		T1	70
all_pins[8]	transitions[0x0=>0x1]	837957	1			T20	16		T23	20		T1	48
all_pins[8]	transitions[0x1=>0x0]	837704	1			T20	25		T23	12		T1	58
all_pins[9]	values[0x0]	2295122	1			T18	1		T19	1		T20	40
all_pins[9]	values[0x1]	1402397	1			T20	43		T23	37		T1	52
all_pins[9]	transitions[0x0=>0x1]	839188	1			T20	19		T23	19		T1	28
all_pins[9]	transitions[0x1=>0x0]	838162	1			T20	15		T23	21		T1	46
all_pins[10]	values[0x0]	2298784	1			T18	1		T19	1		T20	40
all_pins[10]	values[0x1]	1398735	1			T20	43		T23	32		T1	82
all_pins[10]	transitions[0x0=>0x1]	837090	1			T20	20		T23	13		T1	56
all_pins[10]	transitions[0x1=>0x0]	840752	1			T20	20		T23	18		T1	26
all_pins[11]	values[0x0]	2297984	1			T18	1		T19	1		T20	41
all_pins[11]	values[0x1]	1399535	1			T20	42		T23	38		T1	50
all_pins[11]	transitions[0x0=>0x1]	840192	1			T20	19		T23	22		T1	29
all_pins[11]	transitions[0x1=>0x0]	839392	1			T20	20		T23	16		T1	61
all_pins[12]	values[0x0]	2298805	1			T18	1		T19	1		T20	46
all_pins[12]	values[0x1]	1398714	1			T20	37		T23	33		T1	47
all_pins[12]	transitions[0x0=>0x1]	837302	1			T20	20		T23	15		T1	29
all_pins[12]	transitions[0x1=>0x0]	838123	1			T20	25		T23	20		T1	32
all_pins[13]	values[0x0]	2299591	1			T18	1		T19	1		T20	45
all_pins[13]	values[0x1]	1397928	1			T20	38		T23	31		T1	77
all_pins[13]	transitions[0x0=>0x1]	838462	1			T20	21		T23	12		T1	63
all_pins[13]	transitions[0x1=>0x0]	839248	1			T20	20		T23	14		T1	33
all_pins[14]	values[0x0]	2294667	1			T18	1		T19	1		T20	47
all_pins[14]	values[0x1]	1402852	1			T20	36		T23	34		T1	65
all_pins[14]	transitions[0x0=>0x1]	843503	1			T20	17		T23	18		T1	27
all_pins[14]	transitions[0x1=>0x0]	838579	1			T20	19		T23	15		T1	39
all_pins[15]	values[0x0]	2290684	1			T18	1		T19	1		T20	42
all_pins[15]	values[0x1]	1406835	1			T20	41		T23	34		T1	74
all_pins[15]	transitions[0x0=>0x1]	838556	1			T20	26		T23	21		T1	40
all_pins[15]	transitions[0x1=>0x0]	834573	1			T20	21		T23	21		T1	31
all_pins[16]	values[0x0]	2296929	1			T18	1		T19	1		T20	40
all_pins[16]	values[0x1]	1400590	1			T20	43		T23	42		T1	40
all_pins[16]	transitions[0x0=>0x1]	838148	1			T20	21		T23	20		T1	18
all_pins[16]	transitions[0x1=>0x0]	844393	1			T20	19		T23	12		T1	52
all_pins[17]	values[0x0]	2299293	1			T18	1		T19	1		T20	45
all_pins[17]	values[0x1]	1398226	1			T20	38		T23	35		T1	68
all_pins[17]	transitions[0x0=>0x1]	833449	1			T20	21		T23	13		T1	42
all_pins[17]	transitions[0x1=>0x0]	835813	1			T20	26		T23	20		T1	14
all_pins[18]	values[0x0]	2298982	1			T18	1		T19	1		T20	34
all_pins[18]	values[0x1]	1398537	1			T20	49		T23	31		T1	78
all_pins[18]	transitions[0x0=>0x1]	838731	1			T20	24		T23	14		T1	56
all_pins[18]	transitions[0x1=>0x0]	838420	1			T20	13		T23	18		T1	46
all_pins[19]	values[0x0]	2296665	1			T18	1		T19	1		T20	43
all_pins[19]	values[0x1]	1400854	1			T20	40		T23	33		T1	52
all_pins[19]	transitions[0x0=>0x1]	839515	1			T20	14		T23	19		T1	29
all_pins[19]	transitions[0x1=>0x0]	837198	1			T20	23		T23	17		T1	55
all_pins[20]	values[0x0]	2298137	1			T18	1		T19	1		T20	39
all_pins[20]	values[0x1]	1399382	1			T20	44		T23	26		T1	64
all_pins[20]	transitions[0x0=>0x1]	836322	1			T20	21		T23	12		T1	38
all_pins[20]	transitions[0x1=>0x0]	837794	1			T20	17		T23	19		T1	26
all_pins[21]	values[0x0]	2298420	1			T18	1		T19	1		T20	49
all_pins[21]	values[0x1]	1399099	1			T20	34		T23	33		T1	58
all_pins[21]	transitions[0x0=>0x1]	837677	1			T20	20		T23	20		T1	41
all_pins[21]	transitions[0x1=>0x0]	837960	1			T20	30		T23	13		T1	47
all_pins[22]	values[0x0]	2294058	1			T18	1		T19	1		T20	47
all_pins[22]	values[0x1]	1403461	1			T20	36		T23	33		T1	59
all_pins[22]	transitions[0x0=>0x1]	843120	1			T20	20		T23	17		T1	47
all_pins[22]	transitions[0x1=>0x0]	838758	1			T20	18		T23	17		T1	46
all_pins[23]	values[0x0]	2298829	1			T18	1		T19	1		T20	41
all_pins[23]	values[0x1]	1398690	1			T20	42		T23	32		T1	76
all_pins[23]	transitions[0x0=>0x1]	835559	1			T20	24		T23	17		T1	47
all_pins[23]	transitions[0x1=>0x0]	840330	1			T20	18		T23	18		T1	30
all_pins[24]	values[0x0]	2296325	1			T18	1		T19	1		T20	42
all_pins[24]	values[0x1]	1401194	1			T20	41		T23	36		T1	64
all_pins[24]	transitions[0x0=>0x1]	837310	1			T20	21		T23	23		T1	38
all_pins[24]	transitions[0x1=>0x0]	834806	1			T20	22		T23	19		T1	50
all_pins[25]	values[0x0]	2300082	1			T18	1		T19	1		T20	43
all_pins[25]	values[0x1]	1397437	1			T20	40		T23	34		T1	34
all_pins[25]	transitions[0x0=>0x1]	837093	1			T20	22		T23	16		T1	17
all_pins[25]	transitions[0x1=>0x0]	840850	1			T20	23		T23	18		T1	47
all_pins[26]	values[0x0]	2297132	1			T18	1		T19	1		T20	38
all_pins[26]	values[0x1]	1400387	1			T20	45		T23	36		T1	27
all_pins[26]	transitions[0x0=>0x1]	838875	1			T20	24		T23	19		T1	20
all_pins[26]	transitions[0x1=>0x0]	835925	1			T20	19		T23	17		T1	27
all_pins[27]	values[0x0]	2292567	1			T18	1		T19	1		T20	51
all_pins[27]	values[0x1]	1404952	1			T20	32		T23	36		T1	84
all_pins[27]	transitions[0x0=>0x1]	841940	1			T20	14		T23	20		T1	68
all_pins[27]	transitions[0x1=>0x0]	837375	1			T20	27		T23	20		T1	11
all_pins[28]	values[0x0]	2296769	1			T18	1		T19	1		T20	48
all_pins[28]	values[0x1]	1400750	1			T20	35		T23	30		T1	72
all_pins[28]	transitions[0x0=>0x1]	837140	1			T20	23		T23	11		T1	29
all_pins[28]	transitions[0x1=>0x0]	841342	1			T20	20		T23	17		T1	41
all_pins[29]	values[0x0]	2302527	1			T18	1		T19	1		T20	40
all_pins[29]	values[0x1]	1394992	1			T20	43		T23	26		T1	62
all_pins[29]	transitions[0x0=>0x1]	834010	1			T20	22		T23	14		T1	27
all_pins[29]	transitions[0x1=>0x0]	839768	1			T20	14		T23	18		T1	37
all_pins[30]	values[0x0]	2299232	1			T18	1		T19	1		T20	38
all_pins[30]	values[0x1]	1398287	1			T20	45		T23	32		T1	70
all_pins[30]	transitions[0x0=>0x1]	837552	1			T20	26		T23	24		T1	47
all_pins[30]	transitions[0x1=>0x0]	834257	1			T20	24		T23	18		T1	39
all_pins[31]	values[0x0]	2298338	1			T18	1		T19	1		T20	36
all_pins[31]	values[0x1]	1399181	1			T20	47		T23	30		T1	43
all_pins[31]	transitions[0x0=>0x1]	839633	1			T20	22		T23	15		T1	17
all_pins[31]	transitions[0x1=>0x0]	838739	1			T20	20		T23	17		T1	44