Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[1]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[2]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[3]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[4]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[5]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[6]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[7]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[8]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[9]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[10]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[11]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[12]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[13]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[14]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[15]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[16]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[17]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[18]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[19]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[20]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[21]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[22]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[23]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[24]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[25]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[26]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[27]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[28]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[29]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[30]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[31]	12183460	1			T18	150		T19	191		T20	1542

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229534420

1

T18

3556

T19

4912

T20

25223

auto[1]

160336300

1

T18

1244

T19

1200

T20

24121

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

312342503

1

T18

3704

T19

4606

T20

49344

auto[1]

77528217

1

T18

1096

T19

1506

T22

3502

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

289597544

1

T18

2347

T19

3377

T20

49344

auto[1]

100273176

1

T18

2453

T19

2735

T22

8007

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4459870	1			T18	83		T19	74		T20	751
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3371769	1			T18	2		T19	2		T20	791
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1221191	1			T18	13		T19	13		T22	81
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1489412	1			T18	29		T19	62		T22	119
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	436312	1			T18	8		T19	9		T22	15
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1204906	1			T18	15		T19	31		T22	26
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4459144	1			T18	34		T19	84		T20	739
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3366313	1			T18	7		T19	8		T20	803
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1217206	1			T18	18		T19	27		T22	52
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1492934	1			T18	57		T19	45		T22	180
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	434573	1			T18	16		T19	10		T22	30
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1213290	1			T18	18		T19	17		T22	56
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4461085	1			T18	46		T19	51		T20	730
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3370979	1			T18	9		T19	13		T20	812
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1219903	1			T18	12		T19	32		T22	68
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1487924	1			T18	29		T19	48		T22	173
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	434882	1			T18	14		T19	7		T22	21
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1208687	1			T18	40		T19	40		T22	46
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4460524	1			T18	25		T19	95		T20	873
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3375624	1			T18	12		T19	11		T20	669
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1218923	1			T18	20		T19	43		T22	45
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1487411	1			T18	34		T19	23		T22	162
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	435504	1			T18	14		T19	4		T22	39
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1205474	1			T18	45		T19	15		T22	65
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4454794	1			T18	62		T19	59		T20	784
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3380691	1			T18	11		T19	13		T20	758
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1219630	1			T18	18		T19	41		T22	31
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1486647	1			T18	38		T19	65		T22	160
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	434056	1			T18	9		T19	6		T22	25
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1207642	1			T18	12		T19	7		T22	94
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4457288	1			T18	27		T19	34		T20	723
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3370297	1			T18	8		T19	5		T20	819
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1220572	1			T18	23		T19	27		T22	101
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1493355	1			T18	37		T19	98		T22	76
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	434203	1			T18	13		T19	13		T22	8
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1207745	1			T18	42		T19	14		T22	43
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4457820	1			T18	52		T19	57		T20	829
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3371088	1			T18	9		T19	4		T20	713
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1216274	1			T18	6		T19	26		T22	29
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1498554	1			T18	64		T19	74		T22	235
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	432331	1			T18	9		T19	8		T22	39
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1207393	1			T18	10		T19	22		T22	54
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4462990	1			T18	72		T19	66		T20	935
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3368390	1			T18	14		T19	8		T20	607
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1220014	1			T18	33		T19	43		T22	36
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1487215	1			T18	22		T19	45		T22	170
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	433243	1			T18	3		T19	13		T22	30
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1211608	1			T18	6		T19	16		T22	96
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4455187	1			T18	55		T19	69		T20	794
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3374944	1			T18	13		T19	15		T20	748
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1220194	1			T18	12		T19	11		T22	69
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1488229	1			T18	37		T19	38		T22	142
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	433430	1			T18	5		T19	11		T22	15
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1211476	1			T18	28		T19	47		T22	60
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4454352	1			T18	39		T19	72		T20	741
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3370794	1			T18	11		T19	12		T20	801
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1218938	1			T18	5		T19	19		T22	68
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1495106	1			T18	70		T19	46		T22	185
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	433285	1			T18	7		T19	6		T22	36
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1210985	1			T18	18		T19	36		T22	16
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4468496	1			T18	72		T19	85		T20	803
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3367504	1			T18	25		T19	6		T20	739
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1218561	1			T18	18		T22	74		T1	59
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1486360	1			T18	28		T19	71		T22	115
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	432833	1			T19	9		T22	31		T1	3
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1209706	1			T18	7		T19	20		T22	25
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4454643	1			T18	12		T19	27		T20	864
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3373562	1			T18	1		T19	3		T20	678
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1216679	1			T18	10		T19	12		T22	54
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1489263	1			T18	95		T19	106		T22	195
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	437133	1			T18	14		T19	13		T22	45
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1212180	1			T18	18		T19	30		T22	58
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4459447	1			T18	40		T19	86		T20	771
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3371017	1			T18	5		T19	7		T20	771
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1218140	1			T18	4		T19	25		T22	41
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1489669	1			T18	74		T19	43		T22	166
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	433960	1			T18	16		T19	11		T22	27
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1211227	1			T18	11		T19	19		T22	76
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4462946	1			T18	42		T19	73		T20	733
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3369945	1			T18	11		T19	9		T20	809
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1222970	1			T18	11		T19	49		T22	45
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1490785	1			T18	63		T19	44		T22	160
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	433374	1			T18	7		T19	6		T22	45
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1203440	1			T18	16		T19	10		T22	53
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4475312	1			T18	30		T19	63		T20	810
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3363055	1			T18	14		T19	13		T20	732
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1213604	1			T18	50		T19	47		T22	65
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1491210	1			T18	28		T19	53		T22	151
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	432716	1			T18	9		T22	22		T1	9
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1207563	1			T18	19		T19	15		T22	55
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4457443	1			T18	67		T19	91		T20	748
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3367929	1			T18	18		T19	6		T20	794
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1218651	1			T18	26		T19	13		T22	20
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1495794	1			T18	28		T19	62		T22	241
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	432503	1			T18	5		T19	9		T22	42
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1211140	1			T18	6		T19	10		T22	37
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4468680	1			T18	67		T19	76		T20	798
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3374477	1			T18	6		T19	18		T20	744
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1217179	1			T18	17		T19	35		T22	94
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1490989	1			T18	38		T19	32		T22	160
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	433659	1			T18	6		T19	3		T22	32
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1198476	1			T18	16		T19	27		T22	41
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4461540	1			T18	56		T19	55		T20	700
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3376257	1			T18	11		T19	12		T20	842
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1214919	1			T18	13		T19	33		T22	78
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1497880	1			T18	40		T19	56		T22	112
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	432083	1			T18	14		T19	10		T22	25
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1200781	1			T18	16		T19	25		T22	41
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4452225	1			T18	72		T19	77		T20	768
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3383397	1			T18	6		T19	6		T20	774
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1221941	1			T18	2		T19	15		T22	42
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1491670	1			T18	55		T19	59		T22	167
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	432339	1			T18	13		T19	11		T22	33
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1201888	1			T18	2		T19	23		T22	75
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4467171	1			T18	81		T19	112		T20	751
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3365819	1			T18	16		T19	14		T20	791
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1214270	1			T18	22		T19	18		T22	38
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1496935	1			T18	18		T19	39		T22	143
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	436834	1			T18	5		T19	6		T22	28
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1202431	1			T18	8		T19	2		T22	64
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4465704	1			T18	53		T19	68		T20	863
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3372326	1			T18	22		T19	4		T20	679
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1221240	1			T18	38		T19	31		T22	88
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1490422	1			T18	20		T19	69		T22	143
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	433899	1			T18	3		T19	15		T22	27
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1199869	1			T18	14		T19	4		T22	43
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4464103	1			T18	67		T19	70		T20	784
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3366615	1			T18	17		T19	5		T20	758
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1214884	1			T18	1		T19	29		T22	66
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1494409	1			T18	37		T19	60		T22	150
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	437385	1			T18	8		T19	4		T22	46
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1206064	1			T18	20		T19	23		T22	43
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4463766	1			T18	66		T19	67		T20	839
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3369917	1			T18	13		T19	2		T20	703
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1212987	1			T18	8		T19	20		T22	35
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1496919	1			T18	46		T19	58		T22	172
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	438470	1			T18	5		T19	13		T22	26
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1201401	1			T18	12		T19	31		T22	49
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4470998	1			T18	34		T19	55		T20	829
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3365872	1			T18	7		T19	13		T20	713
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1211654	1			T18	23		T19	47		T22	20
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1497212	1			T18	58		T19	50		T22	219
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	437530	1			T18	12		T19	8		T22	33
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1200194	1			T18	16		T19	18		T22	64
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4471367	1			T18	39		T19	72		T20	839
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3365792	1			T18	13		T19	9		T20	703
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1215242	1			T18	6		T19	16		T22	34
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1492311	1			T18	61		T19	78		T22	187
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	435416	1			T18	12		T19	14		T22	29
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1203332	1			T18	19		T19	2		T22	43
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4469306	1			T18	44		T19	79		T20	774
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3368883	1			T18	5		T19	12		T20	768
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1213194	1			T18	16		T19	29		T22	72
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1493424	1			T18	54		T19	40		T22	181
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	435954	1			T18	10		T19	7		T22	34
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1202699	1			T18	21		T19	24		T22	57
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4469659	1			T18	20		T19	78		T20	793
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3360025	1			T18	1		T19	14		T20	749
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1215015	1			T18	11		T19	27		T22	87
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1495054	1			T18	65		T19	47		T22	173
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	435953	1			T18	30		T19	6		T22	45
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1207754	1			T18	23		T19	19		T22	50
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4466135	1			T18	31		T19	46		T20	723
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3369728	1			T18	5		T19	7		T20	819
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1208316	1			T18	8		T19	18		T22	61
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1499712	1			T18	66		T19	91		T22	190
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	433949	1			T18	18		T19	15		T22	29
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1205620	1			T18	22		T19	14		T22	70
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4468530	1			T18	46		T19	52		T20	817
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3366496	1			T18	18		T19	6		T20	725
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1209696	1			T18	35		T19	35		T22	59
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1496918	1			T18	28		T19	56		T22	142
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	433815	1			T18	4		T19	15		T22	24
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1208005	1			T18	19		T19	27		T22	59
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4469211	1			T18	36		T19	53		T20	650
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3365741	1			T18	5		T19	8		T20	892
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1215017	1			T18	10		T19	31		T22	31
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1497203	1			T18	56		T19	57		T22	201
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	434198	1			T18	14		T19	5		T22	33
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1202090	1			T18	29		T19	37		T22	50
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4471442	1			T18	15		T19	98		T20	795
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3368544	1			T18	2		T19	12		T20	747
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1212847	1			T18	8		T19	19		T22	59
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1495690	1			T18	84		T19	47		T22	143
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	432687	1			T18	13		T19	5		T22	24
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1202250	1			T18	28		T19	10		T22	66
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4465286	1			T18	30		T19	83		T20	872
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3363703	1			T18	7		T19	4		T20	670
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1213736	1			T18	11		T19	38		T22	43
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1497753	1			T18	74		T19	54		T22	209
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	435668	1			T18	16		T19	10		T22	31
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1207314	1			T18	12		T19	2		T22	41

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal