Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[1]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[2]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[3]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[4]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[5]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[6]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[7]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[8]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[9]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[10]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[11]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[12]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[13]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[14]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[15]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[16]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[17]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[18]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[19]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[20]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[21]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[22]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[23]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[24]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[25]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[26]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[27]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[28]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[29]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[30]	12183460	1			T18	150		T19	191		T20	1542
bins_for_gpio_bits[31]	12183460	1			T18	150		T19	191		T20	1542

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229534420

1

T18

3556

T19

4912

T20

25223

auto[1]

160336300

1

T18

1244

T19

1200

T20

24121

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229526284

1

T18

3546

T19

4908

T20

25223

auto[1]

160344436

1

T18

1254

T19

1204

T20

24121

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6954786	1			T18	121		T19	144		T20	751
bins_for_gpio_bits[0]	auto[0]	auto[1]	215445	1			T18	3		T19	5		T22	5
bins_for_gpio_bits[0]	auto[1]	auto[0]	215687	1			T18	4		T19	5		T22	5
bins_for_gpio_bits[0]	auto[1]	auto[1]	4797542	1			T18	22		T19	37		T20	791
bins_for_gpio_bits[1]	auto[0]	auto[0]	6952859	1			T18	105		T19	153		T20	739
bins_for_gpio_bits[1]	auto[0]	auto[1]	216168	1			T18	4		T19	3		T22	11
bins_for_gpio_bits[1]	auto[1]	auto[0]	216425	1			T18	4		T19	3		T22	12
bins_for_gpio_bits[1]	auto[1]	auto[1]	4798008	1			T18	37		T19	32		T20	803
bins_for_gpio_bits[2]	auto[0]	auto[0]	6952942	1			T18	80		T19	124		T20	730
bins_for_gpio_bits[2]	auto[0]	auto[1]	215760	1			T18	6		T19	6		T22	9
bins_for_gpio_bits[2]	auto[1]	auto[0]	215970	1			T18	7		T19	7		T22	9
bins_for_gpio_bits[2]	auto[1]	auto[1]	4798788	1			T18	57		T19	54		T20	812
bins_for_gpio_bits[3]	auto[0]	auto[0]	6951151	1			T18	70		T19	158		T20	873
bins_for_gpio_bits[3]	auto[0]	auto[1]	215418	1			T18	8		T19	2		T22	13
bins_for_gpio_bits[3]	auto[1]	auto[0]	215707	1			T18	9		T19	3		T22	13
bins_for_gpio_bits[3]	auto[1]	auto[1]	4801184	1			T18	63		T19	28		T20	669
bins_for_gpio_bits[4]	auto[0]	auto[0]	6944662	1			T18	115		T19	163		T20	784
bins_for_gpio_bits[4]	auto[0]	auto[1]	216124	1			T18	3		T19	2		T22	15
bins_for_gpio_bits[4]	auto[1]	auto[0]	216409	1			T18	3		T19	2		T22	15
bins_for_gpio_bits[4]	auto[1]	auto[1]	4806265	1			T18	29		T19	24		T20	758
bins_for_gpio_bits[5]	auto[0]	auto[0]	6955497	1			T18	83		T19	156		T20	723
bins_for_gpio_bits[5]	auto[0]	auto[1]	215478	1			T18	4		T19	3		T22	8
bins_for_gpio_bits[5]	auto[1]	auto[0]	215718	1			T18	4		T19	3		T22	8
bins_for_gpio_bits[5]	auto[1]	auto[1]	4796767	1			T18	59		T19	29		T20	819
bins_for_gpio_bits[6]	auto[0]	auto[0]	6956447	1			T18	119		T19	150		T20	829
bins_for_gpio_bits[6]	auto[0]	auto[1]	215975	1			T18	3		T19	7		T22	9
bins_for_gpio_bits[6]	auto[1]	auto[0]	216201	1			T18	3		T19	7		T22	9
bins_for_gpio_bits[6]	auto[1]	auto[1]	4794837	1			T18	25		T19	27		T20	713
bins_for_gpio_bits[7]	auto[0]	auto[0]	6953973	1			T18	126		T19	151		T20	935
bins_for_gpio_bits[7]	auto[0]	auto[1]	215978	1			T18	1		T19	2		T22	14
bins_for_gpio_bits[7]	auto[1]	auto[0]	216246	1			T18	1		T19	3		T22	14
bins_for_gpio_bits[7]	auto[1]	auto[1]	4797263	1			T18	22		T19	35		T20	607
bins_for_gpio_bits[8]	auto[0]	auto[0]	6947522	1			T18	99		T19	112		T20	794
bins_for_gpio_bits[8]	auto[0]	auto[1]	215837	1			T18	4		T19	6		T22	10
bins_for_gpio_bits[8]	auto[1]	auto[0]	216088	1			T18	5		T19	6		T22	10
bins_for_gpio_bits[8]	auto[1]	auto[1]	4804013	1			T18	42		T19	67		T20	748
bins_for_gpio_bits[9]	auto[0]	auto[0]	6951755	1			T18	110		T19	134		T20	741
bins_for_gpio_bits[9]	auto[0]	auto[1]	216387	1			T18	4		T19	3		T22	3
bins_for_gpio_bits[9]	auto[1]	auto[0]	216641	1			T18	4		T19	3		T22	3
bins_for_gpio_bits[9]	auto[1]	auto[1]	4798677	1			T18	32		T19	51		T20	801
bins_for_gpio_bits[10]	auto[0]	auto[0]	6957428	1			T18	116		T19	153		T20	803
bins_for_gpio_bits[10]	auto[0]	auto[1]	215680	1			T18	1		T19	3		T22	4
bins_for_gpio_bits[10]	auto[1]	auto[0]	215989	1			T18	2		T19	3		T22	4
bins_for_gpio_bits[10]	auto[1]	auto[1]	4794363	1			T18	31		T19	32		T20	739
bins_for_gpio_bits[11]	auto[0]	auto[0]	6944310	1			T18	111		T19	139		T20	864
bins_for_gpio_bits[11]	auto[0]	auto[1]	216010	1			T18	6		T19	6		T22	14
bins_for_gpio_bits[11]	auto[1]	auto[0]	216275	1			T18	6		T19	6		T22	15
bins_for_gpio_bits[11]	auto[1]	auto[1]	4806865	1			T18	27		T19	40		T20	678
bins_for_gpio_bits[12]	auto[0]	auto[0]	6951065	1			T18	114		T19	151		T20	771
bins_for_gpio_bits[12]	auto[0]	auto[1]	215948	1			T18	4		T19	3		T22	10
bins_for_gpio_bits[12]	auto[1]	auto[0]	216191	1			T18	4		T19	3		T22	10
bins_for_gpio_bits[12]	auto[1]	auto[1]	4800256	1			T18	28		T19	34		T20	771
bins_for_gpio_bits[13]	auto[0]	auto[0]	6960855	1			T18	113		T19	164		T20	733
bins_for_gpio_bits[13]	auto[0]	auto[1]	215566	1			T18	3		T19	2		T22	11
bins_for_gpio_bits[13]	auto[1]	auto[0]	215846	1			T18	3		T19	2		T22	11
bins_for_gpio_bits[13]	auto[1]	auto[1]	4791193	1			T18	31		T19	23		T20	809
bins_for_gpio_bits[14]	auto[0]	auto[0]	6964416	1			T18	103		T19	159		T20	810
bins_for_gpio_bits[14]	auto[0]	auto[1]	215489	1			T18	4		T19	4		T22	13
bins_for_gpio_bits[14]	auto[1]	auto[0]	215710	1			T18	5		T19	4		T22	13
bins_for_gpio_bits[14]	auto[1]	auto[1]	4787845	1			T18	38		T19	24		T20	732
bins_for_gpio_bits[15]	auto[0]	auto[0]	6955407	1			T18	120		T19	163		T20	748
bins_for_gpio_bits[15]	auto[0]	auto[1]	216241	1			T18	1		T19	3		T22	9
bins_for_gpio_bits[15]	auto[1]	auto[0]	216481	1			T18	1		T19	3		T22	9
bins_for_gpio_bits[15]	auto[1]	auto[1]	4795331	1			T18	28		T19	22		T20	794
bins_for_gpio_bits[16]	auto[0]	auto[0]	6961046	1			T18	118		T19	140		T20	798
bins_for_gpio_bits[16]	auto[0]	auto[1]	215533	1			T18	4		T19	3		T22	10
bins_for_gpio_bits[16]	auto[1]	auto[0]	215802	1			T18	4		T19	3		T22	10
bins_for_gpio_bits[16]	auto[1]	auto[1]	4791079	1			T18	24		T19	45		T20	744
bins_for_gpio_bits[17]	auto[0]	auto[0]	6958612	1			T18	104		T19	140		T20	700
bins_for_gpio_bits[17]	auto[0]	auto[1]	215492	1			T18	5		T19	3		T22	9
bins_for_gpio_bits[17]	auto[1]	auto[0]	215727	1			T18	5		T19	4		T22	9
bins_for_gpio_bits[17]	auto[1]	auto[1]	4793629	1			T18	36		T19	44		T20	842
bins_for_gpio_bits[18]	auto[0]	auto[0]	6950031	1			T18	128		T19	147		T20	768
bins_for_gpio_bits[18]	auto[0]	auto[1]	215567	1			T18	1		T19	4		T22	14
bins_for_gpio_bits[18]	auto[1]	auto[0]	215805	1			T18	1		T19	4		T22	14
bins_for_gpio_bits[18]	auto[1]	auto[1]	4802057	1			T18	20		T19	36		T20	774
bins_for_gpio_bits[19]	auto[0]	auto[0]	6962605	1			T18	119		T19	168		T20	751
bins_for_gpio_bits[19]	auto[0]	auto[1]	215552	1			T18	2		T19	1		T22	11
bins_for_gpio_bits[19]	auto[1]	auto[0]	215771	1			T18	2		T19	1		T22	11
bins_for_gpio_bits[19]	auto[1]	auto[1]	4789532	1			T18	27		T19	21		T20	791
bins_for_gpio_bits[20]	auto[0]	auto[0]	6961785	1			T18	107		T19	166		T20	863
bins_for_gpio_bits[20]	auto[0]	auto[1]	215343	1			T18	4		T19	2		T22	9
bins_for_gpio_bits[20]	auto[1]	auto[0]	215581	1			T18	4		T19	2		T22	9
bins_for_gpio_bits[20]	auto[1]	auto[1]	4790751	1			T18	35		T19	21		T20	679
bins_for_gpio_bits[21]	auto[0]	auto[0]	6957531	1			T18	101		T19	154		T20	784
bins_for_gpio_bits[21]	auto[0]	auto[1]	215623	1			T18	4		T19	5		T22	9
bins_for_gpio_bits[21]	auto[1]	auto[0]	215865	1			T18	4		T19	5		T22	9
bins_for_gpio_bits[21]	auto[1]	auto[1]	4794441	1			T18	41		T19	27		T20	758
bins_for_gpio_bits[22]	auto[0]	auto[0]	6957572	1			T18	118		T19	141		T20	839
bins_for_gpio_bits[22]	auto[0]	auto[1]	215825	1			T18	1		T19	4		T22	10
bins_for_gpio_bits[22]	auto[1]	auto[0]	216100	1			T18	2		T19	4		T22	10
bins_for_gpio_bits[22]	auto[1]	auto[1]	4793963	1			T18	29		T19	42		T20	703
bins_for_gpio_bits[23]	auto[0]	auto[0]	6964329	1			T18	111		T19	150		T20	829
bins_for_gpio_bits[23]	auto[0]	auto[1]	215335	1			T18	4		T19	2		T22	11
bins_for_gpio_bits[23]	auto[1]	auto[0]	215535	1			T18	4		T19	2		T22	11
bins_for_gpio_bits[23]	auto[1]	auto[1]	4788261	1			T18	31		T19	37		T20	713
bins_for_gpio_bits[24]	auto[0]	auto[0]	6962986	1			T18	103		T19	165		T20	839
bins_for_gpio_bits[24]	auto[0]	auto[1]	215645	1			T18	3		T19	1		T22	12
bins_for_gpio_bits[24]	auto[1]	auto[0]	215934	1			T18	3		T19	1		T22	12
bins_for_gpio_bits[24]	auto[1]	auto[1]	4788895	1			T18	41		T19	24		T20	703
bins_for_gpio_bits[25]	auto[0]	auto[0]	6960099	1			T18	111		T19	145		T20	774
bins_for_gpio_bits[25]	auto[0]	auto[1]	215585	1			T18	3		T19	3		T22	13
bins_for_gpio_bits[25]	auto[1]	auto[0]	215825	1			T18	3		T19	3		T22	13
bins_for_gpio_bits[25]	auto[1]	auto[1]	4791951	1			T18	33		T19	40		T20	768
bins_for_gpio_bits[26]	auto[0]	auto[0]	6963371	1			T18	91		T19	149		T20	793
bins_for_gpio_bits[26]	auto[0]	auto[1]	216099	1			T18	4		T19	3		T22	10
bins_for_gpio_bits[26]	auto[1]	auto[0]	216357	1			T18	5		T19	3		T22	10
bins_for_gpio_bits[26]	auto[1]	auto[1]	4787633	1			T18	50		T19	36		T20	749
bins_for_gpio_bits[27]	auto[0]	auto[0]	6958490	1			T18	100		T19	151		T20	723
bins_for_gpio_bits[27]	auto[0]	auto[1]	215430	1			T18	5		T19	4		T22	16
bins_for_gpio_bits[27]	auto[1]	auto[0]	215673	1			T18	5		T19	4		T22	16
bins_for_gpio_bits[27]	auto[1]	auto[1]	4793867	1			T18	40		T19	32		T20	819
bins_for_gpio_bits[28]	auto[0]	auto[0]	6959418	1			T18	105		T19	136		T20	817
bins_for_gpio_bits[28]	auto[0]	auto[1]	215482	1			T18	4		T19	7		T22	11
bins_for_gpio_bits[28]	auto[1]	auto[0]	215726	1			T18	4		T19	7		T22	11
bins_for_gpio_bits[28]	auto[1]	auto[1]	4792834	1			T18	37		T19	41		T20	725
bins_for_gpio_bits[29]	auto[0]	auto[0]	6965221	1			T18	97		T19	136		T20	650
bins_for_gpio_bits[29]	auto[0]	auto[1]	215930	1			T18	4		T19	5		T22	9
bins_for_gpio_bits[29]	auto[1]	auto[0]	216210	1			T18	5		T19	5		T22	9
bins_for_gpio_bits[29]	auto[1]	auto[1]	4786099	1			T18	44		T19	45		T20	892
bins_for_gpio_bits[30]	auto[0]	auto[0]	6964037	1			T18	102		T19	161		T20	795
bins_for_gpio_bits[30]	auto[0]	auto[1]	215660	1			T18	4		T19	3		T22	15
bins_for_gpio_bits[30]	auto[1]	auto[0]	215942	1			T18	5		T19	3		T22	15
bins_for_gpio_bits[30]	auto[1]	auto[1]	4787821	1			T18	39		T19	24		T20	747
bins_for_gpio_bits[31]	auto[0]	auto[0]	6960548	1			T18	113		T19	174		T20	872
bins_for_gpio_bits[31]	auto[0]	auto[1]	215923	1			T18	2		T19	1		T22	9
bins_for_gpio_bits[31]	auto[1]	auto[0]	216227	1			T18	2		T19	1		T22	9
bins_for_gpio_bits[31]	auto[1]	auto[1]	4790762	1			T18	33		T19	15		T20	670