Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7150483 |
1 |
|
|
T18 |
79 |
|
T19 |
95 |
|
T20 |
1542 |
| auto[1] |
5210699 |
1 |
|
|
T1 |
162 |
|
T2 |
20286 |
|
T11 |
1216 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10194391 |
1 |
|
|
T18 |
79 |
|
T19 |
95 |
|
T20 |
1542 |
| auto[1] |
2166791 |
1 |
|
|
T1 |
33 |
|
T2 |
5605 |
|
T11 |
956 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7180175 |
1 |
|
|
T18 |
79 |
|
T19 |
95 |
|
T20 |
1542 |
| auto[1] |
5181007 |
1 |
|
|
T1 |
200 |
|
T2 |
20288 |
|
T11 |
1169 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1500290 |
1 |
|
|
T1 |
130 |
|
T2 |
7808 |
|
T11 |
105 |
| auto[1] |
auto[0] |
auto[1] |
1082594 |
1 |
|
|
T1 |
22 |
|
T2 |
2858 |
|
T11 |
424 |
| auto[1] |
auto[1] |
auto[0] |
1513926 |
1 |
|
|
T1 |
37 |
|
T2 |
6875 |
|
T11 |
108 |
| auto[1] |
auto[1] |
auto[1] |
1084197 |
1 |
|
|
T1 |
11 |
|
T2 |
2747 |
|
T11 |
532 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |