Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7152963 |
1 |
|
|
T18 |
79 |
|
T19 |
95 |
|
T20 |
1542 |
| auto[1] |
5208219 |
1 |
|
|
T1 |
149 |
|
T2 |
20732 |
|
T11 |
974 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10195077 |
1 |
|
|
T18 |
79 |
|
T19 |
95 |
|
T20 |
1542 |
| auto[1] |
2166105 |
1 |
|
|
T1 |
72 |
|
T2 |
5635 |
|
T11 |
762 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7163564 |
1 |
|
|
T18 |
79 |
|
T19 |
95 |
|
T20 |
1542 |
| auto[1] |
5197618 |
1 |
|
|
T1 |
201 |
|
T2 |
20537 |
|
T11 |
1055 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1523989 |
1 |
|
|
T1 |
98 |
|
T2 |
7571 |
|
T11 |
155 |
| auto[1] |
auto[0] |
auto[1] |
1083524 |
1 |
|
|
T1 |
62 |
|
T2 |
2881 |
|
T11 |
353 |
| auto[1] |
auto[1] |
auto[0] |
1507524 |
1 |
|
|
T1 |
31 |
|
T2 |
7331 |
|
T11 |
138 |
| auto[1] |
auto[1] |
auto[1] |
1082581 |
1 |
|
|
T1 |
10 |
|
T2 |
2754 |
|
T11 |
409 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |