Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7151120 |
1 |
|
|
T18 |
79 |
|
T19 |
95 |
|
T20 |
1542 |
| auto[1] |
5210062 |
1 |
|
|
T1 |
200 |
|
T2 |
20612 |
|
T11 |
1176 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10188374 |
1 |
|
|
T18 |
79 |
|
T19 |
95 |
|
T20 |
1542 |
| auto[1] |
2172808 |
1 |
|
|
T1 |
85 |
|
T2 |
5868 |
|
T11 |
741 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7164482 |
1 |
|
|
T18 |
79 |
|
T19 |
95 |
|
T20 |
1542 |
| auto[1] |
5196700 |
1 |
|
|
T1 |
328 |
|
T2 |
20703 |
|
T11 |
926 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1514601 |
1 |
|
|
T1 |
130 |
|
T2 |
7414 |
|
T11 |
79 |
| auto[1] |
auto[0] |
auto[1] |
1088249 |
1 |
|
|
T1 |
57 |
|
T2 |
2971 |
|
T11 |
344 |
| auto[1] |
auto[1] |
auto[0] |
1509291 |
1 |
|
|
T1 |
113 |
|
T2 |
7421 |
|
T11 |
106 |
| auto[1] |
auto[1] |
auto[1] |
1084559 |
1 |
|
|
T1 |
28 |
|
T2 |
2897 |
|
T11 |
397 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |