Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7176878 |
1 |
|
|
T18 |
79 |
|
T19 |
95 |
|
T20 |
1542 |
| auto[1] |
5184304 |
1 |
|
|
T1 |
233 |
|
T2 |
21397 |
|
T11 |
1027 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11701842 |
1 |
|
|
T18 |
79 |
|
T19 |
95 |
|
T20 |
1542 |
| auto[1] |
659340 |
1 |
|
|
T1 |
9 |
|
T2 |
1378 |
|
T11 |
36 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7178857 |
1 |
|
|
T18 |
79 |
|
T19 |
95 |
|
T20 |
1542 |
| auto[1] |
5182325 |
1 |
|
|
T1 |
216 |
|
T2 |
20355 |
|
T11 |
939 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2266559 |
1 |
|
|
T1 |
88 |
|
T2 |
9609 |
|
T11 |
554 |
| auto[1] |
auto[0] |
auto[1] |
330695 |
1 |
|
|
T1 |
3 |
|
T2 |
718 |
|
T11 |
24 |
| auto[1] |
auto[1] |
auto[0] |
2256426 |
1 |
|
|
T1 |
119 |
|
T2 |
9368 |
|
T11 |
349 |
| auto[1] |
auto[1] |
auto[1] |
328645 |
1 |
|
|
T1 |
6 |
|
T2 |
660 |
|
T11 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |