Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 939
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T762 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3462207411 Aug 08 05:11:44 PM PDT 24 Aug 08 05:11:45 PM PDT 24 234813476 ps
T95 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1891882992 Aug 08 05:11:31 PM PDT 24 Aug 08 05:11:32 PM PDT 24 41439571 ps
T763 /workspace/coverage/cover_reg_top/21.gpio_intr_test.3452633354 Aug 08 05:11:47 PM PDT 24 Aug 08 05:11:48 PM PDT 24 10635282 ps
T764 /workspace/coverage/cover_reg_top/35.gpio_intr_test.3868695035 Aug 08 05:11:43 PM PDT 24 Aug 08 05:11:44 PM PDT 24 15516922 ps
T765 /workspace/coverage/cover_reg_top/33.gpio_intr_test.1723408470 Aug 08 05:11:46 PM PDT 24 Aug 08 05:11:47 PM PDT 24 13697382 ps
T766 /workspace/coverage/cover_reg_top/3.gpio_intr_test.1556179831 Aug 08 05:11:27 PM PDT 24 Aug 08 05:11:28 PM PDT 24 11407504 ps
T767 /workspace/coverage/cover_reg_top/7.gpio_intr_test.683648533 Aug 08 05:11:33 PM PDT 24 Aug 08 05:11:34 PM PDT 24 16050146 ps
T768 /workspace/coverage/cover_reg_top/25.gpio_intr_test.2356629686 Aug 08 05:11:36 PM PDT 24 Aug 08 05:11:37 PM PDT 24 19636322 ps
T769 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3080559262 Aug 08 05:11:26 PM PDT 24 Aug 08 05:11:29 PM PDT 24 69704421 ps
T770 /workspace/coverage/cover_reg_top/27.gpio_intr_test.2738368052 Aug 08 05:11:41 PM PDT 24 Aug 08 05:11:41 PM PDT 24 15311624 ps
T82 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3610219692 Aug 08 05:11:47 PM PDT 24 Aug 08 05:11:48 PM PDT 24 13545757 ps
T771 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.4011597935 Aug 08 05:11:27 PM PDT 24 Aug 08 05:11:28 PM PDT 24 76352352 ps
T772 /workspace/coverage/cover_reg_top/38.gpio_intr_test.3221367066 Aug 08 05:11:45 PM PDT 24 Aug 08 05:11:46 PM PDT 24 13931775 ps
T773 /workspace/coverage/cover_reg_top/4.gpio_intr_test.4208801903 Aug 08 05:11:35 PM PDT 24 Aug 08 05:11:36 PM PDT 24 14533302 ps
T774 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.428276464 Aug 08 05:11:39 PM PDT 24 Aug 08 05:11:41 PM PDT 24 52405284 ps
T775 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3273745810 Aug 08 05:11:27 PM PDT 24 Aug 08 05:11:28 PM PDT 24 39742107 ps
T776 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2852392200 Aug 08 05:11:32 PM PDT 24 Aug 08 05:11:34 PM PDT 24 64410144 ps
T777 /workspace/coverage/cover_reg_top/0.gpio_intr_test.2628437265 Aug 08 05:11:35 PM PDT 24 Aug 08 05:11:36 PM PDT 24 80892211 ps
T778 /workspace/coverage/cover_reg_top/13.gpio_intr_test.2080115817 Aug 08 05:11:37 PM PDT 24 Aug 08 05:11:37 PM PDT 24 37737859 ps
T779 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1678220872 Aug 08 05:11:41 PM PDT 24 Aug 08 05:11:42 PM PDT 24 157079706 ps
T780 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3394768523 Aug 08 05:11:38 PM PDT 24 Aug 08 05:11:41 PM PDT 24 268796671 ps
T781 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2866888141 Aug 08 05:11:32 PM PDT 24 Aug 08 05:11:34 PM PDT 24 172238196 ps
T782 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1837160287 Aug 08 05:11:29 PM PDT 24 Aug 08 05:11:29 PM PDT 24 17177928 ps
T783 /workspace/coverage/cover_reg_top/39.gpio_intr_test.2357141928 Aug 08 05:11:49 PM PDT 24 Aug 08 05:11:55 PM PDT 24 66248450 ps
T784 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1451714427 Aug 08 05:11:45 PM PDT 24 Aug 08 05:11:47 PM PDT 24 326242788 ps
T35 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2662723323 Aug 08 05:11:40 PM PDT 24 Aug 08 05:11:41 PM PDT 24 219084843 ps
T785 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3538493261 Aug 08 05:11:34 PM PDT 24 Aug 08 05:11:35 PM PDT 24 36663122 ps
T786 /workspace/coverage/cover_reg_top/36.gpio_intr_test.2295384037 Aug 08 05:11:47 PM PDT 24 Aug 08 05:11:48 PM PDT 24 13218662 ps
T83 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.836747621 Aug 08 05:11:34 PM PDT 24 Aug 08 05:11:35 PM PDT 24 101223840 ps
T787 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1332130144 Aug 08 05:11:38 PM PDT 24 Aug 08 05:11:40 PM PDT 24 50083885 ps
T788 /workspace/coverage/cover_reg_top/17.gpio_intr_test.2929937521 Aug 08 05:11:39 PM PDT 24 Aug 08 05:11:40 PM PDT 24 13833117 ps
T84 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2772962787 Aug 08 05:11:40 PM PDT 24 Aug 08 05:11:41 PM PDT 24 11731333 ps
T85 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3132650458 Aug 08 05:11:35 PM PDT 24 Aug 08 05:11:36 PM PDT 24 16364446 ps
T789 /workspace/coverage/cover_reg_top/18.gpio_intr_test.1682787429 Aug 08 05:11:52 PM PDT 24 Aug 08 05:11:53 PM PDT 24 46768917 ps
T790 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.429426195 Aug 08 05:11:38 PM PDT 24 Aug 08 05:11:40 PM PDT 24 65305124 ps
T791 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3492976680 Aug 08 05:11:21 PM PDT 24 Aug 08 05:11:21 PM PDT 24 47853524 ps
T792 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3352242562 Aug 08 05:11:26 PM PDT 24 Aug 08 05:11:27 PM PDT 24 52569200 ps
T793 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2953613933 Aug 08 05:11:45 PM PDT 24 Aug 08 05:11:47 PM PDT 24 275838386 ps
T794 /workspace/coverage/cover_reg_top/28.gpio_intr_test.128797962 Aug 08 05:11:35 PM PDT 24 Aug 08 05:11:35 PM PDT 24 12845328 ps
T795 /workspace/coverage/cover_reg_top/46.gpio_intr_test.4086011985 Aug 08 05:11:51 PM PDT 24 Aug 08 05:11:52 PM PDT 24 40780220 ps
T796 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3261363679 Aug 08 05:11:35 PM PDT 24 Aug 08 05:11:37 PM PDT 24 180848381 ps
T797 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.736270941 Aug 08 05:11:46 PM PDT 24 Aug 08 05:11:46 PM PDT 24 15915768 ps
T798 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3752832184 Aug 08 05:11:38 PM PDT 24 Aug 08 05:11:40 PM PDT 24 62179335 ps
T799 /workspace/coverage/cover_reg_top/24.gpio_intr_test.180736127 Aug 08 05:11:38 PM PDT 24 Aug 08 05:11:39 PM PDT 24 41596274 ps
T86 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.4092735422 Aug 08 05:11:32 PM PDT 24 Aug 08 05:11:33 PM PDT 24 16310396 ps
T800 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1444835043 Aug 08 05:11:33 PM PDT 24 Aug 08 05:11:34 PM PDT 24 60264323 ps
T801 /workspace/coverage/cover_reg_top/30.gpio_intr_test.1742349126 Aug 08 05:11:47 PM PDT 24 Aug 08 05:11:48 PM PDT 24 42943299 ps
T802 /workspace/coverage/cover_reg_top/15.gpio_intr_test.1877473403 Aug 08 05:11:34 PM PDT 24 Aug 08 05:11:35 PM PDT 24 26528588 ps
T803 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3202712779 Aug 08 05:11:47 PM PDT 24 Aug 08 05:11:48 PM PDT 24 49483097 ps
T87 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2048997930 Aug 08 05:11:33 PM PDT 24 Aug 08 05:11:33 PM PDT 24 72566119 ps
T804 /workspace/coverage/cover_reg_top/6.gpio_intr_test.3665054984 Aug 08 05:11:36 PM PDT 24 Aug 08 05:11:37 PM PDT 24 31855256 ps
T805 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.226060978 Aug 08 05:11:39 PM PDT 24 Aug 08 05:11:42 PM PDT 24 86048632 ps
T806 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2975039125 Aug 08 05:11:41 PM PDT 24 Aug 08 05:11:42 PM PDT 24 31411002 ps
T807 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.4121106640 Aug 08 05:11:42 PM PDT 24 Aug 08 05:11:42 PM PDT 24 66368734 ps
T808 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.595448279 Aug 08 05:11:31 PM PDT 24 Aug 08 05:11:32 PM PDT 24 33974858 ps
T809 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3276589630 Aug 08 05:11:22 PM PDT 24 Aug 08 05:11:25 PM PDT 24 313947587 ps
T810 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.4205481381 Aug 08 05:11:39 PM PDT 24 Aug 08 05:11:40 PM PDT 24 72597433 ps
T811 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3103349547 Aug 08 05:11:30 PM PDT 24 Aug 08 05:11:32 PM PDT 24 149864294 ps
T812 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3593198265 Aug 08 05:11:36 PM PDT 24 Aug 08 05:11:37 PM PDT 24 73598191 ps
T813 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2654133926 Aug 08 05:11:23 PM PDT 24 Aug 08 05:11:24 PM PDT 24 66503316 ps
T814 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3121970159 Aug 08 05:11:30 PM PDT 24 Aug 08 05:11:32 PM PDT 24 427751758 ps
T815 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3496032932 Aug 08 05:11:39 PM PDT 24 Aug 08 05:11:40 PM PDT 24 18058432 ps
T816 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1686417346 Aug 08 05:11:33 PM PDT 24 Aug 08 05:11:34 PM PDT 24 53082762 ps
T817 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3674605956 Aug 08 05:11:36 PM PDT 24 Aug 08 05:11:37 PM PDT 24 23596890 ps
T818 /workspace/coverage/cover_reg_top/14.gpio_intr_test.3323274205 Aug 08 05:11:41 PM PDT 24 Aug 08 05:11:41 PM PDT 24 62830630 ps
T819 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.4257445460 Aug 08 05:11:13 PM PDT 24 Aug 08 05:11:14 PM PDT 24 577842437 ps
T820 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.750749884 Aug 08 05:11:37 PM PDT 24 Aug 08 05:11:39 PM PDT 24 48099038 ps
T821 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2872486111 Aug 08 05:11:50 PM PDT 24 Aug 08 05:11:53 PM PDT 24 380647381 ps
T822 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1363872547 Aug 08 05:11:28 PM PDT 24 Aug 08 05:11:29 PM PDT 24 565989814 ps
T823 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3411210076 Aug 08 05:11:27 PM PDT 24 Aug 08 05:11:28 PM PDT 24 18339353 ps
T824 /workspace/coverage/cover_reg_top/5.gpio_intr_test.4219988634 Aug 08 05:11:38 PM PDT 24 Aug 08 05:11:39 PM PDT 24 26302204 ps
T825 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1530504322 Aug 08 05:11:35 PM PDT 24 Aug 08 05:11:37 PM PDT 24 60342007 ps
T826 /workspace/coverage/cover_reg_top/40.gpio_intr_test.231773780 Aug 08 05:11:52 PM PDT 24 Aug 08 05:11:57 PM PDT 24 17419801 ps
T88 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3010062807 Aug 08 05:11:39 PM PDT 24 Aug 08 05:11:40 PM PDT 24 39499416 ps
T827 /workspace/coverage/cover_reg_top/32.gpio_intr_test.1017620929 Aug 08 05:11:50 PM PDT 24 Aug 08 05:11:50 PM PDT 24 27829587 ps
T108 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2235943300 Aug 08 05:12:02 PM PDT 24 Aug 08 05:12:03 PM PDT 24 811267547 ps
T828 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1713624375 Aug 08 05:11:38 PM PDT 24 Aug 08 05:11:39 PM PDT 24 14270020 ps
T829 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.288688131 Aug 08 05:11:47 PM PDT 24 Aug 08 05:11:48 PM PDT 24 97362476 ps
T830 /workspace/coverage/cover_reg_top/34.gpio_intr_test.791469265 Aug 08 05:11:54 PM PDT 24 Aug 08 05:11:54 PM PDT 24 30428515 ps
T831 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.508633331 Aug 08 05:11:30 PM PDT 24 Aug 08 05:11:31 PM PDT 24 71008354 ps
T832 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1599163603 Aug 08 05:11:49 PM PDT 24 Aug 08 05:11:50 PM PDT 24 55015185 ps
T833 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1169540744 Aug 08 05:11:38 PM PDT 24 Aug 08 05:11:39 PM PDT 24 47508535 ps
T834 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3379355389 Aug 08 05:11:50 PM PDT 24 Aug 08 05:11:50 PM PDT 24 21244426 ps
T835 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.340895827 Aug 08 05:11:34 PM PDT 24 Aug 08 05:11:35 PM PDT 24 52202283 ps
T836 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.4277612041 Aug 08 05:11:41 PM PDT 24 Aug 08 05:11:43 PM PDT 24 98689774 ps
T837 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2099410598 Aug 08 05:11:41 PM PDT 24 Aug 08 05:11:41 PM PDT 24 24755554 ps
T838 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3238772005 Aug 08 05:11:43 PM PDT 24 Aug 08 05:11:44 PM PDT 24 30810224 ps
T109 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1726723628 Aug 08 05:11:38 PM PDT 24 Aug 08 05:11:40 PM PDT 24 460035940 ps
T839 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2298558996 Aug 08 05:11:28 PM PDT 24 Aug 08 05:11:31 PM PDT 24 147340061 ps
T840 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2136205776 Aug 08 05:11:48 PM PDT 24 Aug 08 05:11:49 PM PDT 24 89629221 ps
T841 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.420842193 Aug 08 05:12:10 PM PDT 24 Aug 08 05:12:12 PM PDT 24 61915768 ps
T842 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1662235758 Aug 08 05:11:46 PM PDT 24 Aug 08 05:11:57 PM PDT 24 109678861 ps
T843 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3460980151 Aug 08 05:12:07 PM PDT 24 Aug 08 05:12:08 PM PDT 24 31041248 ps
T844 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3178180491 Aug 08 05:12:04 PM PDT 24 Aug 08 05:12:05 PM PDT 24 100148795 ps
T845 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.340626056 Aug 08 05:11:46 PM PDT 24 Aug 08 05:11:47 PM PDT 24 129585003 ps
T846 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1163521971 Aug 08 05:12:16 PM PDT 24 Aug 08 05:12:17 PM PDT 24 162174417 ps
T847 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.722022956 Aug 08 05:12:05 PM PDT 24 Aug 08 05:12:06 PM PDT 24 63391419 ps
T848 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2368229383 Aug 08 05:12:17 PM PDT 24 Aug 08 05:12:18 PM PDT 24 50766443 ps
T849 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2963622402 Aug 08 05:11:54 PM PDT 24 Aug 08 05:11:55 PM PDT 24 212992392 ps
T850 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1771304321 Aug 08 05:12:02 PM PDT 24 Aug 08 05:12:03 PM PDT 24 49302858 ps
T851 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2983560051 Aug 08 05:12:01 PM PDT 24 Aug 08 05:12:02 PM PDT 24 60221094 ps
T852 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.448857719 Aug 08 05:11:50 PM PDT 24 Aug 08 05:11:51 PM PDT 24 112532842 ps
T853 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.173974112 Aug 08 05:11:47 PM PDT 24 Aug 08 05:11:48 PM PDT 24 209405798 ps
T854 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.593529654 Aug 08 05:11:52 PM PDT 24 Aug 08 05:11:53 PM PDT 24 707107246 ps
T855 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.498377001 Aug 08 05:11:57 PM PDT 24 Aug 08 05:11:58 PM PDT 24 309156127 ps
T856 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3554049766 Aug 08 05:12:06 PM PDT 24 Aug 08 05:12:07 PM PDT 24 54215399 ps
T857 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1459915526 Aug 08 05:11:49 PM PDT 24 Aug 08 05:11:50 PM PDT 24 193660701 ps
T858 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3356287967 Aug 08 05:11:49 PM PDT 24 Aug 08 05:11:50 PM PDT 24 156043388 ps
T859 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3749847769 Aug 08 05:12:04 PM PDT 24 Aug 08 05:12:05 PM PDT 24 38309863 ps
T860 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3874110818 Aug 08 05:11:51 PM PDT 24 Aug 08 05:11:52 PM PDT 24 32367517 ps
T861 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3748428487 Aug 08 05:11:48 PM PDT 24 Aug 08 05:11:49 PM PDT 24 107185651 ps
T862 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.311804690 Aug 08 05:12:05 PM PDT 24 Aug 08 05:12:06 PM PDT 24 152926592 ps
T863 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2173083469 Aug 08 05:12:17 PM PDT 24 Aug 08 05:12:18 PM PDT 24 359648759 ps
T864 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1507463150 Aug 08 05:12:02 PM PDT 24 Aug 08 05:12:03 PM PDT 24 59272861 ps
T865 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.168809053 Aug 08 05:11:50 PM PDT 24 Aug 08 05:11:51 PM PDT 24 407912776 ps
T866 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1642599081 Aug 08 05:12:21 PM PDT 24 Aug 08 05:12:22 PM PDT 24 47684160 ps
T867 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.860892617 Aug 08 05:12:13 PM PDT 24 Aug 08 05:12:14 PM PDT 24 208881957 ps
T868 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3481747451 Aug 08 05:11:48 PM PDT 24 Aug 08 05:11:49 PM PDT 24 129557623 ps
T869 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2314688934 Aug 08 05:12:14 PM PDT 24 Aug 08 05:12:15 PM PDT 24 131260117 ps
T870 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.925285761 Aug 08 05:12:08 PM PDT 24 Aug 08 05:12:09 PM PDT 24 389326389 ps
T871 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3193112247 Aug 08 05:11:49 PM PDT 24 Aug 08 05:11:50 PM PDT 24 290578288 ps
T872 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3231612673 Aug 08 05:11:58 PM PDT 24 Aug 08 05:11:59 PM PDT 24 150483135 ps
T873 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3067276807 Aug 08 05:12:26 PM PDT 24 Aug 08 05:12:27 PM PDT 24 99195816 ps
T874 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3167461279 Aug 08 05:11:50 PM PDT 24 Aug 08 05:11:51 PM PDT 24 369763971 ps
T875 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1321147789 Aug 08 05:12:01 PM PDT 24 Aug 08 05:12:03 PM PDT 24 67418569 ps
T876 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.604545823 Aug 08 05:12:01 PM PDT 24 Aug 08 05:12:02 PM PDT 24 116870698 ps
T877 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3527646893 Aug 08 05:12:12 PM PDT 24 Aug 08 05:12:14 PM PDT 24 223548948 ps
T878 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1113674675 Aug 08 05:11:55 PM PDT 24 Aug 08 05:11:56 PM PDT 24 19828646 ps
T879 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3210011611 Aug 08 05:11:47 PM PDT 24 Aug 08 05:11:48 PM PDT 24 80699651 ps
T880 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.792485252 Aug 08 05:11:58 PM PDT 24 Aug 08 05:12:00 PM PDT 24 167686733 ps
T881 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.4038127635 Aug 08 05:11:52 PM PDT 24 Aug 08 05:11:53 PM PDT 24 688821262 ps
T882 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3447943561 Aug 08 05:11:48 PM PDT 24 Aug 08 05:11:49 PM PDT 24 109489459 ps
T883 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3928560099 Aug 08 05:12:07 PM PDT 24 Aug 08 05:12:08 PM PDT 24 266891716 ps
T884 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1575060432 Aug 08 05:12:07 PM PDT 24 Aug 08 05:12:08 PM PDT 24 38782299 ps
T885 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.893613669 Aug 08 05:11:50 PM PDT 24 Aug 08 05:11:51 PM PDT 24 50002790 ps
T886 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4161932373 Aug 08 05:12:03 PM PDT 24 Aug 08 05:12:04 PM PDT 24 31632784 ps
T887 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3840614340 Aug 08 05:12:07 PM PDT 24 Aug 08 05:12:08 PM PDT 24 37153805 ps
T888 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.731303491 Aug 08 05:11:46 PM PDT 24 Aug 08 05:11:47 PM PDT 24 52162483 ps
T889 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3924278684 Aug 08 05:11:51 PM PDT 24 Aug 08 05:11:52 PM PDT 24 27917070 ps
T890 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.586143462 Aug 08 05:12:12 PM PDT 24 Aug 08 05:12:13 PM PDT 24 43450883 ps
T891 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2131449615 Aug 08 05:12:00 PM PDT 24 Aug 08 05:12:01 PM PDT 24 37518558 ps
T892 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1045576388 Aug 08 05:12:00 PM PDT 24 Aug 08 05:12:02 PM PDT 24 224063925 ps
T893 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3933681217 Aug 08 05:11:49 PM PDT 24 Aug 08 05:11:50 PM PDT 24 52502490 ps
T894 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1907405387 Aug 08 05:11:51 PM PDT 24 Aug 08 05:11:52 PM PDT 24 39693783 ps
T895 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3945488619 Aug 08 05:11:48 PM PDT 24 Aug 08 05:11:49 PM PDT 24 87411465 ps
T896 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3580696721 Aug 08 05:12:05 PM PDT 24 Aug 08 05:12:11 PM PDT 24 121332173 ps
T897 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4184751897 Aug 08 05:12:13 PM PDT 24 Aug 08 05:12:14 PM PDT 24 35902518 ps
T898 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2981536122 Aug 08 05:11:56 PM PDT 24 Aug 08 05:11:58 PM PDT 24 101264687 ps
T899 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2953369781 Aug 08 05:12:08 PM PDT 24 Aug 08 05:12:09 PM PDT 24 838995797 ps
T900 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.836262091 Aug 08 05:12:05 PM PDT 24 Aug 08 05:12:07 PM PDT 24 169553821 ps
T901 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3316602150 Aug 08 05:12:13 PM PDT 24 Aug 08 05:12:14 PM PDT 24 90226569 ps
T902 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2663002969 Aug 08 05:12:05 PM PDT 24 Aug 08 05:12:06 PM PDT 24 362235888 ps
T903 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1629555147 Aug 08 05:12:11 PM PDT 24 Aug 08 05:12:13 PM PDT 24 121997683 ps
T904 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3746315362 Aug 08 05:12:04 PM PDT 24 Aug 08 05:12:05 PM PDT 24 101923566 ps
T905 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.4217365406 Aug 08 05:11:55 PM PDT 24 Aug 08 05:11:56 PM PDT 24 301552398 ps
T906 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3765716259 Aug 08 05:11:46 PM PDT 24 Aug 08 05:11:47 PM PDT 24 93054600 ps
T907 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1974513071 Aug 08 05:11:51 PM PDT 24 Aug 08 05:11:53 PM PDT 24 192642682 ps
T908 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2220658023 Aug 08 05:12:00 PM PDT 24 Aug 08 05:12:01 PM PDT 24 461008351 ps
T909 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2194158536 Aug 08 05:11:49 PM PDT 24 Aug 08 05:11:50 PM PDT 24 95980381 ps
T910 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.471292523 Aug 08 05:11:50 PM PDT 24 Aug 08 05:11:51 PM PDT 24 31789673 ps
T911 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3729112899 Aug 08 05:12:10 PM PDT 24 Aug 08 05:12:11 PM PDT 24 82887931 ps
T912 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.4206438356 Aug 08 05:12:17 PM PDT 24 Aug 08 05:12:19 PM PDT 24 49113214 ps
T913 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2260319068 Aug 08 05:12:09 PM PDT 24 Aug 08 05:12:11 PM PDT 24 196046893 ps
T914 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3627998702 Aug 08 05:11:54 PM PDT 24 Aug 08 05:11:55 PM PDT 24 30462525 ps
T915 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2337851300 Aug 08 05:11:58 PM PDT 24 Aug 08 05:11:59 PM PDT 24 41212793 ps
T916 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3371605638 Aug 08 05:11:47 PM PDT 24 Aug 08 05:11:48 PM PDT 24 53060147 ps
T917 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.780830030 Aug 08 05:11:48 PM PDT 24 Aug 08 05:11:50 PM PDT 24 198300946 ps
T918 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1331394240 Aug 08 05:11:47 PM PDT 24 Aug 08 05:11:48 PM PDT 24 58863727 ps
T919 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1970207096 Aug 08 05:12:12 PM PDT 24 Aug 08 05:12:13 PM PDT 24 695526185 ps
T920 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1034951834 Aug 08 05:12:19 PM PDT 24 Aug 08 05:12:20 PM PDT 24 54009111 ps
T921 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3514353218 Aug 08 05:12:01 PM PDT 24 Aug 08 05:12:02 PM PDT 24 21148378 ps
T922 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3730740657 Aug 08 05:11:51 PM PDT 24 Aug 08 05:11:52 PM PDT 24 93551350 ps
T923 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.9211008 Aug 08 05:12:04 PM PDT 24 Aug 08 05:12:05 PM PDT 24 82106859 ps
T924 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1017310256 Aug 08 05:12:10 PM PDT 24 Aug 08 05:12:11 PM PDT 24 172620627 ps
T925 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3293503106 Aug 08 05:11:47 PM PDT 24 Aug 08 05:11:48 PM PDT 24 28067141 ps
T926 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1323693185 Aug 08 05:11:49 PM PDT 24 Aug 08 05:11:50 PM PDT 24 95999733 ps
T927 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1604486315 Aug 08 05:11:52 PM PDT 24 Aug 08 05:11:53 PM PDT 24 21966566 ps
T928 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3471957227 Aug 08 05:11:51 PM PDT 24 Aug 08 05:11:53 PM PDT 24 76699436 ps
T929 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.600263815 Aug 08 05:11:50 PM PDT 24 Aug 08 05:11:51 PM PDT 24 124879993 ps
T930 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1069227053 Aug 08 05:11:52 PM PDT 24 Aug 08 05:11:54 PM PDT 24 67944145 ps
T931 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.82249497 Aug 08 05:12:03 PM PDT 24 Aug 08 05:12:04 PM PDT 24 243596269 ps
T932 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4159514052 Aug 08 05:11:47 PM PDT 24 Aug 08 05:11:48 PM PDT 24 204773988 ps
T933 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1447357612 Aug 08 05:11:51 PM PDT 24 Aug 08 05:11:52 PM PDT 24 48497990 ps
T934 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.197113948 Aug 08 05:12:01 PM PDT 24 Aug 08 05:12:02 PM PDT 24 147923253 ps
T935 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3552509199 Aug 08 05:12:00 PM PDT 24 Aug 08 05:12:02 PM PDT 24 95766293 ps
T936 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.217493056 Aug 08 05:12:14 PM PDT 24 Aug 08 05:12:15 PM PDT 24 234675106 ps
T937 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.940811420 Aug 08 05:12:00 PM PDT 24 Aug 08 05:12:01 PM PDT 24 220962045 ps
T938 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.998829881 Aug 08 05:11:50 PM PDT 24 Aug 08 05:11:52 PM PDT 24 59703939 ps
T939 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2826699354 Aug 08 05:11:50 PM PDT 24 Aug 08 05:11:51 PM PDT 24 42287614 ps

Test location /workspace/coverage/default/39.gpio_stress_all.1214306928
Short name T2
Test name
Test status
Simulation time 35185493456 ps
CPU time 106.61 seconds
Started Aug 08 05:13:34 PM PDT 24
Finished Aug 08 05:15:21 PM PDT 24
Peak memory 198768 kb
Host smart-f929ad7f-a71e-4ade-a17e-46d7587d4dd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214306928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1214306928
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3317700667
Short name T20
Test name
Test status
Simulation time 323750782 ps
CPU time 3.45 seconds
Started Aug 08 05:12:35 PM PDT 24
Finished Aug 08 05:12:39 PM PDT 24
Peak memory 198508 kb
Host smart-5055685d-3e1d-44fe-8a40-1f3493003bfb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317700667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3317700667
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.701750941
Short name T25
Test name
Test status
Simulation time 300233921858 ps
CPU time 892.59 seconds
Started Aug 08 05:13:15 PM PDT 24
Finished Aug 08 05:28:08 PM PDT 24
Peak memory 198868 kb
Host smart-0d406075-f6a4-4696-ae6a-f4f2a567db3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=701750941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.701750941
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2437637175
Short name T72
Test name
Test status
Simulation time 34866748 ps
CPU time 0.81 seconds
Started Aug 08 05:11:23 PM PDT 24
Finished Aug 08 05:11:24 PM PDT 24
Peak memory 196680 kb
Host smart-2402bd9f-e9ed-4faa-9e21-e80cb9f3ee91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437637175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2437637175
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.669964011
Short name T29
Test name
Test status
Simulation time 1271711876 ps
CPU time 1.7 seconds
Started Aug 08 05:11:31 PM PDT 24
Finished Aug 08 05:11:33 PM PDT 24
Peak memory 198708 kb
Host smart-8ec98dca-e417-4835-8255-69e367da8682
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669964011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.669964011
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/16.gpio_alert_test.343245135
Short name T175
Test name
Test status
Simulation time 22995498 ps
CPU time 0.59 seconds
Started Aug 08 05:12:45 PM PDT 24
Finished Aug 08 05:12:46 PM PDT 24
Peak memory 195096 kb
Host smart-706c48f7-a69b-4d8b-94ca-bbd6a80930d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343245135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.343245135
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3042685636
Short name T31
Test name
Test status
Simulation time 132005253 ps
CPU time 0.98 seconds
Started Aug 08 05:12:09 PM PDT 24
Finished Aug 08 05:12:11 PM PDT 24
Peak memory 215108 kb
Host smart-a57d7e82-2e22-4d86-ad1b-d837ba2f1c7d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042685636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3042685636
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1891882992
Short name T95
Test name
Test status
Simulation time 41439571 ps
CPU time 0.93 seconds
Started Aug 08 05:11:31 PM PDT 24
Finished Aug 08 05:11:32 PM PDT 24
Peak memory 197012 kb
Host smart-a230eb24-c950-4780-a52c-4df66c8b27df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891882992 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1891882992
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.4257445460
Short name T819
Test name
Test status
Simulation time 577842437 ps
CPU time 1.15 seconds
Started Aug 08 05:11:13 PM PDT 24
Finished Aug 08 05:11:14 PM PDT 24
Peak memory 198728 kb
Host smart-9f7970aa-03d6-4492-ba3e-0f7d27a1f880
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257445460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.4257445460
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3613669505
Short name T38
Test name
Test status
Simulation time 146019456 ps
CPU time 1.43 seconds
Started Aug 08 05:11:32 PM PDT 24
Finished Aug 08 05:11:34 PM PDT 24
Peak memory 198660 kb
Host smart-d246f480-87c1-4575-8cc5-9f63a7d838d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613669505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3613669505
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3276589630
Short name T809
Test name
Test status
Simulation time 313947587 ps
CPU time 2.9 seconds
Started Aug 08 05:11:22 PM PDT 24
Finished Aug 08 05:11:25 PM PDT 24
Peak memory 197812 kb
Host smart-8cb51075-3fe9-442e-bfe1-36e9c013723d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276589630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3276589630
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.913392670
Short name T759
Test name
Test status
Simulation time 22664063 ps
CPU time 0.69 seconds
Started Aug 08 05:11:15 PM PDT 24
Finished Aug 08 05:11:16 PM PDT 24
Peak memory 195588 kb
Host smart-05dac470-0566-4390-b5a1-a0c0c716ec74
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913392670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.913392670
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2654133926
Short name T813
Test name
Test status
Simulation time 66503316 ps
CPU time 0.93 seconds
Started Aug 08 05:11:23 PM PDT 24
Finished Aug 08 05:11:24 PM PDT 24
Peak memory 198572 kb
Host smart-78245c09-6a84-484e-bee3-faff3f5cc9ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654133926 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2654133926
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3445359296
Short name T75
Test name
Test status
Simulation time 15386646 ps
CPU time 0.65 seconds
Started Aug 08 05:11:20 PM PDT 24
Finished Aug 08 05:11:21 PM PDT 24
Peak memory 196004 kb
Host smart-23e09c50-2815-4f2d-99d3-01c57ca3bb89
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445359296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3445359296
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2628437265
Short name T777
Test name
Test status
Simulation time 80892211 ps
CPU time 0.62 seconds
Started Aug 08 05:11:35 PM PDT 24
Finished Aug 08 05:11:36 PM PDT 24
Peak memory 194544 kb
Host smart-5cc9fb02-3346-4fd2-88d3-e5ff5835c327
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628437265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2628437265
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3492976680
Short name T791
Test name
Test status
Simulation time 47853524 ps
CPU time 0.66 seconds
Started Aug 08 05:11:21 PM PDT 24
Finished Aug 08 05:11:21 PM PDT 24
Peak memory 195516 kb
Host smart-f653326d-3a35-4d49-a138-fe2fa1f66eb3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492976680 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3492976680
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2747515197
Short name T738
Test name
Test status
Simulation time 422704135 ps
CPU time 2.45 seconds
Started Aug 08 05:11:13 PM PDT 24
Finished Aug 08 05:11:16 PM PDT 24
Peak memory 198732 kb
Host smart-6ba11b18-29dd-43c6-8496-bc88ee19ce58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747515197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2747515197
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2996645297
Short name T74
Test name
Test status
Simulation time 95548150 ps
CPU time 0.78 seconds
Started Aug 08 05:11:35 PM PDT 24
Finished Aug 08 05:11:36 PM PDT 24
Peak memory 196396 kb
Host smart-6f8d85a9-62bb-424a-8cd5-542f88a21550
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996645297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2996645297
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2866888141
Short name T781
Test name
Test status
Simulation time 172238196 ps
CPU time 2.38 seconds
Started Aug 08 05:11:32 PM PDT 24
Finished Aug 08 05:11:34 PM PDT 24
Peak memory 197664 kb
Host smart-8eeb95e5-3f7f-421c-bf25-83d318b458a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866888141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2866888141
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3843407717
Short name T73
Test name
Test status
Simulation time 22639921 ps
CPU time 0.68 seconds
Started Aug 08 05:11:39 PM PDT 24
Finished Aug 08 05:11:41 PM PDT 24
Peak memory 195252 kb
Host smart-885b5078-632a-4a43-b838-2c7bcfe4229e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843407717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3843407717
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.340895827
Short name T835
Test name
Test status
Simulation time 52202283 ps
CPU time 0.87 seconds
Started Aug 08 05:11:34 PM PDT 24
Finished Aug 08 05:11:35 PM PDT 24
Peak memory 198496 kb
Host smart-e179f2bf-aa1d-4c07-85b9-61e55aecca83
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340895827 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.340895827
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2164954074
Short name T755
Test name
Test status
Simulation time 101995878 ps
CPU time 0.61 seconds
Started Aug 08 05:11:39 PM PDT 24
Finished Aug 08 05:11:40 PM PDT 24
Peak memory 196104 kb
Host smart-6632abb0-963e-44d2-9318-8310fa875bc0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164954074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2164954074
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1647077179
Short name T716
Test name
Test status
Simulation time 79608621 ps
CPU time 0.59 seconds
Started Aug 08 05:11:34 PM PDT 24
Finished Aug 08 05:11:34 PM PDT 24
Peak memory 194976 kb
Host smart-7fc226db-493c-4c9d-bfbc-45740cfefbe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647077179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1647077179
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2951938324
Short name T750
Test name
Test status
Simulation time 261799923 ps
CPU time 1.63 seconds
Started Aug 08 05:11:33 PM PDT 24
Finished Aug 08 05:11:34 PM PDT 24
Peak memory 198728 kb
Host smart-68dd8d09-4f4c-4de4-b300-568c00a71777
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951938324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2951938324
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.4207549928
Short name T36
Test name
Test status
Simulation time 567734023 ps
CPU time 1.38 seconds
Started Aug 08 05:11:38 PM PDT 24
Finished Aug 08 05:11:39 PM PDT 24
Peak memory 198636 kb
Host smart-ad84d3ad-c26d-4638-8754-254682cb27d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207549928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.4207549928
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2772245976
Short name T742
Test name
Test status
Simulation time 18119275 ps
CPU time 0.78 seconds
Started Aug 08 05:11:40 PM PDT 24
Finished Aug 08 05:11:41 PM PDT 24
Peak memory 196876 kb
Host smart-4616ad5d-7d12-4bad-a3ba-3ff75f2f2c79
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772245976 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2772245976
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2099410598
Short name T837
Test name
Test status
Simulation time 24755554 ps
CPU time 0.63 seconds
Started Aug 08 05:11:41 PM PDT 24
Finished Aug 08 05:11:41 PM PDT 24
Peak memory 196020 kb
Host smart-0ca0351c-cabb-4aad-8dc8-d711da74b011
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099410598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2099410598
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.4254948843
Short name T726
Test name
Test status
Simulation time 62273590 ps
CPU time 0.58 seconds
Started Aug 08 05:11:40 PM PDT 24
Finished Aug 08 05:11:41 PM PDT 24
Peak memory 194364 kb
Host smart-e145967f-ad52-451f-8663-ff0bb05ffb2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254948843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.4254948843
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3252532656
Short name T91
Test name
Test status
Simulation time 23885380 ps
CPU time 0.91 seconds
Started Aug 08 05:11:36 PM PDT 24
Finished Aug 08 05:11:37 PM PDT 24
Peak memory 198464 kb
Host smart-21d9f68e-18c8-4dfe-954c-5b0e549c6ed3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252532656 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3252532656
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.351472440
Short name T760
Test name
Test status
Simulation time 150031359 ps
CPU time 1.33 seconds
Started Aug 08 05:11:38 PM PDT 24
Finished Aug 08 05:11:39 PM PDT 24
Peak memory 198792 kb
Host smart-437d3303-192d-4d67-a151-9c8265350a6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351472440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.351472440
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1726723628
Short name T109
Test name
Test status
Simulation time 460035940 ps
CPU time 1.47 seconds
Started Aug 08 05:11:38 PM PDT 24
Finished Aug 08 05:11:40 PM PDT 24
Peak memory 198752 kb
Host smart-3a9cd0a0-8c17-47d8-b6fc-71c0e612290b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726723628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1726723628
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1530504322
Short name T825
Test name
Test status
Simulation time 60342007 ps
CPU time 1.49 seconds
Started Aug 08 05:11:35 PM PDT 24
Finished Aug 08 05:11:37 PM PDT 24
Peak memory 198804 kb
Host smart-ccd8fd52-6eeb-40fd-81b9-5b15b1323cb5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530504322 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1530504322
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.736270941
Short name T797
Test name
Test status
Simulation time 15915768 ps
CPU time 0.59 seconds
Started Aug 08 05:11:46 PM PDT 24
Finished Aug 08 05:11:46 PM PDT 24
Peak memory 196036 kb
Host smart-07020c02-214d-482c-b62e-d49afbb251e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736270941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.736270941
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.4102643476
Short name T735
Test name
Test status
Simulation time 23249785 ps
CPU time 0.61 seconds
Started Aug 08 05:11:43 PM PDT 24
Finished Aug 08 05:11:44 PM PDT 24
Peak memory 195104 kb
Host smart-72395dbe-fa6a-41f0-a19d-3387486aeed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102643476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.4102643476
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2985904645
Short name T89
Test name
Test status
Simulation time 74278495 ps
CPU time 0.73 seconds
Started Aug 08 05:11:46 PM PDT 24
Finished Aug 08 05:11:46 PM PDT 24
Peak memory 196328 kb
Host smart-5e08fdf0-8d06-4bd7-b7bd-c51cef5ef9ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985904645 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2985904645
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3462207411
Short name T762
Test name
Test status
Simulation time 234813476 ps
CPU time 1.06 seconds
Started Aug 08 05:11:44 PM PDT 24
Finished Aug 08 05:11:45 PM PDT 24
Peak memory 198584 kb
Host smart-1a0033c8-18cf-4a2e-82a5-91d489cab1b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462207411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3462207411
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2953613933
Short name T793
Test name
Test status
Simulation time 275838386 ps
CPU time 1.24 seconds
Started Aug 08 05:11:45 PM PDT 24
Finished Aug 08 05:11:47 PM PDT 24
Peak memory 198712 kb
Host smart-3660f99c-7491-4276-aed5-614fa1bb88e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953613933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2953613933
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1253440033
Short name T731
Test name
Test status
Simulation time 189362340 ps
CPU time 0.92 seconds
Started Aug 08 05:11:44 PM PDT 24
Finished Aug 08 05:11:45 PM PDT 24
Peak memory 198684 kb
Host smart-22983bba-0c3a-497c-83fe-84dc5b6883c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253440033 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1253440033
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1599163603
Short name T832
Test name
Test status
Simulation time 55015185 ps
CPU time 0.6 seconds
Started Aug 08 05:11:49 PM PDT 24
Finished Aug 08 05:11:50 PM PDT 24
Peak memory 195192 kb
Host smart-c8ebb268-203d-461f-971e-948a348a7711
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599163603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1599163603
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3354495279
Short name T761
Test name
Test status
Simulation time 44976833 ps
CPU time 0.6 seconds
Started Aug 08 05:11:39 PM PDT 24
Finished Aug 08 05:11:39 PM PDT 24
Peak memory 194516 kb
Host smart-c8e6f675-7a5a-401a-9a1d-d66977dbee08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354495279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3354495279
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.4205481381
Short name T810
Test name
Test status
Simulation time 72597433 ps
CPU time 0.65 seconds
Started Aug 08 05:11:39 PM PDT 24
Finished Aug 08 05:11:40 PM PDT 24
Peak memory 196160 kb
Host smart-2dbcf19e-49c9-4dab-837b-ba70c9fe6838
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205481381 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.4205481381
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.4277612041
Short name T836
Test name
Test status
Simulation time 98689774 ps
CPU time 1.57 seconds
Started Aug 08 05:11:41 PM PDT 24
Finished Aug 08 05:11:43 PM PDT 24
Peak memory 198760 kb
Host smart-641338c2-5578-45d8-a027-d7b958e64c50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277612041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.4277612041
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.435943560
Short name T110
Test name
Test status
Simulation time 280103647 ps
CPU time 1.52 seconds
Started Aug 08 05:11:42 PM PDT 24
Finished Aug 08 05:11:44 PM PDT 24
Peak memory 198744 kb
Host smart-199e549a-8056-4db7-9b01-01837165225d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435943560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.435943560
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.4243497413
Short name T748
Test name
Test status
Simulation time 60429846 ps
CPU time 0.95 seconds
Started Aug 08 05:11:41 PM PDT 24
Finished Aug 08 05:11:43 PM PDT 24
Peak memory 198500 kb
Host smart-95d90cc8-d0d6-41cc-bcbf-66b59f4f194e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243497413 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.4243497413
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3202712779
Short name T803
Test name
Test status
Simulation time 49483097 ps
CPU time 0.58 seconds
Started Aug 08 05:11:47 PM PDT 24
Finished Aug 08 05:11:48 PM PDT 24
Peak memory 194628 kb
Host smart-b446a520-15f3-401a-af47-1ad14cd2310f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202712779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3202712779
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2080115817
Short name T778
Test name
Test status
Simulation time 37737859 ps
CPU time 0.59 seconds
Started Aug 08 05:11:37 PM PDT 24
Finished Aug 08 05:11:37 PM PDT 24
Peak memory 194420 kb
Host smart-e646ea10-b3a3-45c6-857d-4c578b0ff5d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080115817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2080115817
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.739025281
Short name T90
Test name
Test status
Simulation time 65750983 ps
CPU time 0.86 seconds
Started Aug 08 05:11:46 PM PDT 24
Finished Aug 08 05:11:47 PM PDT 24
Peak memory 196740 kb
Host smart-c28bbfde-6144-4cae-8c00-8bea49ad71a8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739025281 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.739025281
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.4206150855
Short name T739
Test name
Test status
Simulation time 32708602 ps
CPU time 1.84 seconds
Started Aug 08 05:11:47 PM PDT 24
Finished Aug 08 05:11:49 PM PDT 24
Peak memory 198804 kb
Host smart-3191173f-3f17-491d-bda0-b1c256ea2dcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206150855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.4206150855
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2094440181
Short name T41
Test name
Test status
Simulation time 433105131 ps
CPU time 1.33 seconds
Started Aug 08 05:11:48 PM PDT 24
Finished Aug 08 05:11:49 PM PDT 24
Peak memory 198624 kb
Host smart-75e9ee25-ea30-44b6-a552-48f2d3e0dc95
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094440181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2094440181
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3496032932
Short name T815
Test name
Test status
Simulation time 18058432 ps
CPU time 0.67 seconds
Started Aug 08 05:11:39 PM PDT 24
Finished Aug 08 05:11:40 PM PDT 24
Peak memory 197368 kb
Host smart-fce76899-f40c-4796-9e4b-b593c4120961
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496032932 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3496032932
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1678220872
Short name T779
Test name
Test status
Simulation time 157079706 ps
CPU time 0.63 seconds
Started Aug 08 05:11:41 PM PDT 24
Finished Aug 08 05:11:42 PM PDT 24
Peak memory 195624 kb
Host smart-8604ceae-f616-46f2-a38a-65d232ea0f58
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678220872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1678220872
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.3323274205
Short name T818
Test name
Test status
Simulation time 62830630 ps
CPU time 0.64 seconds
Started Aug 08 05:11:41 PM PDT 24
Finished Aug 08 05:11:41 PM PDT 24
Peak memory 195152 kb
Host smart-12b7b96c-40eb-4fe0-9b32-396f735ff9a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323274205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3323274205
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.429426195
Short name T790
Test name
Test status
Simulation time 65305124 ps
CPU time 0.9 seconds
Started Aug 08 05:11:38 PM PDT 24
Finished Aug 08 05:11:40 PM PDT 24
Peak memory 196968 kb
Host smart-918b3749-0fce-4c0e-bd39-57c59fd192e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429426195 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.gpio_same_csr_outstanding.429426195
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.4095884981
Short name T754
Test name
Test status
Simulation time 469174556 ps
CPU time 2.8 seconds
Started Aug 08 05:11:50 PM PDT 24
Finished Aug 08 05:11:53 PM PDT 24
Peak memory 198776 kb
Host smart-b53c1040-b014-4484-b7d7-95874d9f7fa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095884981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.4095884981
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2235943300
Short name T108
Test name
Test status
Simulation time 811267547 ps
CPU time 1.41 seconds
Started Aug 08 05:12:02 PM PDT 24
Finished Aug 08 05:12:03 PM PDT 24
Peak memory 198596 kb
Host smart-7f02fd3e-d046-4f7c-8287-762d4a5f9f50
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235943300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2235943300
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2399449963
Short name T717
Test name
Test status
Simulation time 29592358 ps
CPU time 0.67 seconds
Started Aug 08 05:11:36 PM PDT 24
Finished Aug 08 05:11:37 PM PDT 24
Peak memory 197496 kb
Host smart-76e9a6c0-558c-4e17-941c-bcd5cec9bca4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399449963 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2399449963
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2772962787
Short name T84
Test name
Test status
Simulation time 11731333 ps
CPU time 0.65 seconds
Started Aug 08 05:11:40 PM PDT 24
Finished Aug 08 05:11:41 PM PDT 24
Peak memory 195568 kb
Host smart-b47c5e52-7fcd-4995-9540-7aa13cfcec5a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772962787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2772962787
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.1877473403
Short name T802
Test name
Test status
Simulation time 26528588 ps
CPU time 0.6 seconds
Started Aug 08 05:11:34 PM PDT 24
Finished Aug 08 05:11:35 PM PDT 24
Peak memory 195116 kb
Host smart-5aa55319-569f-4dea-ab8e-e992c230bf2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877473403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1877473403
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3409815739
Short name T71
Test name
Test status
Simulation time 21513366 ps
CPU time 0.68 seconds
Started Aug 08 05:11:48 PM PDT 24
Finished Aug 08 05:11:49 PM PDT 24
Peak memory 195528 kb
Host smart-4c48604d-4eb6-42ab-a9ec-4086117bb265
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409815739 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.3409815739
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.226060978
Short name T805
Test name
Test status
Simulation time 86048632 ps
CPU time 2.39 seconds
Started Aug 08 05:11:39 PM PDT 24
Finished Aug 08 05:11:42 PM PDT 24
Peak memory 198768 kb
Host smart-8b8cb804-f80b-48c4-a5bc-130817fecf5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226060978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.226060978
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1451714427
Short name T784
Test name
Test status
Simulation time 326242788 ps
CPU time 1.2 seconds
Started Aug 08 05:11:45 PM PDT 24
Finished Aug 08 05:11:47 PM PDT 24
Peak memory 198684 kb
Host smart-a973171d-a695-4dbb-bdcc-a7297c39f5a8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451714427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1451714427
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3985557862
Short name T719
Test name
Test status
Simulation time 19517212 ps
CPU time 0.83 seconds
Started Aug 08 05:11:52 PM PDT 24
Finished Aug 08 05:11:53 PM PDT 24
Peak memory 198484 kb
Host smart-ff2359c1-6add-4fa9-bdfc-966b9e3c73e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985557862 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3985557862
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3379355389
Short name T834
Test name
Test status
Simulation time 21244426 ps
CPU time 0.61 seconds
Started Aug 08 05:11:50 PM PDT 24
Finished Aug 08 05:11:50 PM PDT 24
Peak memory 195380 kb
Host smart-9fc09092-0113-4fb0-af9d-9f26c38d432d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379355389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3379355389
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3437836085
Short name T732
Test name
Test status
Simulation time 15833242 ps
CPU time 0.58 seconds
Started Aug 08 05:11:35 PM PDT 24
Finished Aug 08 05:11:36 PM PDT 24
Peak memory 194412 kb
Host smart-e11ca6ec-0d72-4eae-b6b2-e30a7ef4fc12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437836085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3437836085
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1033199532
Short name T93
Test name
Test status
Simulation time 17330001 ps
CPU time 0.68 seconds
Started Aug 08 05:11:39 PM PDT 24
Finished Aug 08 05:11:39 PM PDT 24
Peak memory 195696 kb
Host smart-9cca2133-9ffc-426a-aa84-a06d70d229c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033199532 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1033199532
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2345975928
Short name T758
Test name
Test status
Simulation time 284758041 ps
CPU time 2.6 seconds
Started Aug 08 05:11:38 PM PDT 24
Finished Aug 08 05:11:41 PM PDT 24
Peak memory 198716 kb
Host smart-86224186-8859-4a57-8bc4-8d9e3de79b51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345975928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2345975928
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2662723323
Short name T35
Test name
Test status
Simulation time 219084843 ps
CPU time 0.86 seconds
Started Aug 08 05:11:40 PM PDT 24
Finished Aug 08 05:11:41 PM PDT 24
Peak memory 198068 kb
Host smart-38df5344-a9e2-4d51-a711-5a0236ec473e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662723323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2662723323
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3538493261
Short name T785
Test name
Test status
Simulation time 36663122 ps
CPU time 0.74 seconds
Started Aug 08 05:11:34 PM PDT 24
Finished Aug 08 05:11:35 PM PDT 24
Peak memory 198504 kb
Host smart-8d6c2ff0-5bc9-470a-b1d4-23e67ef883a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538493261 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3538493261
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3610219692
Short name T82
Test name
Test status
Simulation time 13545757 ps
CPU time 0.58 seconds
Started Aug 08 05:11:47 PM PDT 24
Finished Aug 08 05:11:48 PM PDT 24
Peak memory 194012 kb
Host smart-35cc46b2-1a96-42b8-82aa-928667851e70
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610219692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3610219692
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2929937521
Short name T788
Test name
Test status
Simulation time 13833117 ps
CPU time 0.59 seconds
Started Aug 08 05:11:39 PM PDT 24
Finished Aug 08 05:11:40 PM PDT 24
Peak memory 194444 kb
Host smart-941c1dde-01d1-4b4a-94c6-be09bee92a92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929937521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2929937521
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3443204855
Short name T77
Test name
Test status
Simulation time 98045292 ps
CPU time 0.77 seconds
Started Aug 08 05:11:40 PM PDT 24
Finished Aug 08 05:11:40 PM PDT 24
Peak memory 197496 kb
Host smart-dad37ff8-0be3-40db-ba02-1640939b0b41
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443204855 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3443204855
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.116473848
Short name T741
Test name
Test status
Simulation time 1263523701 ps
CPU time 2.73 seconds
Started Aug 08 05:11:45 PM PDT 24
Finished Aug 08 05:11:48 PM PDT 24
Peak memory 198776 kb
Host smart-5eaf1167-0319-4912-be93-aa56f86ad634
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116473848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.116473848
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3261363679
Short name T796
Test name
Test status
Simulation time 180848381 ps
CPU time 1.42 seconds
Started Aug 08 05:11:35 PM PDT 24
Finished Aug 08 05:11:37 PM PDT 24
Peak memory 198612 kb
Host smart-39c76301-b051-4a0a-93ab-871dae4068ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261363679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3261363679
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.383820948
Short name T718
Test name
Test status
Simulation time 49117467 ps
CPU time 0.67 seconds
Started Aug 08 05:11:38 PM PDT 24
Finished Aug 08 05:11:39 PM PDT 24
Peak memory 197652 kb
Host smart-36f0cc98-a774-485d-b63f-1b1aa5dc7cb6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383820948 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.383820948
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3875903835
Short name T757
Test name
Test status
Simulation time 16513453 ps
CPU time 0.64 seconds
Started Aug 08 05:11:47 PM PDT 24
Finished Aug 08 05:11:48 PM PDT 24
Peak memory 195640 kb
Host smart-f230f4d7-b221-45df-84dd-d78663907995
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875903835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3875903835
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1682787429
Short name T789
Test name
Test status
Simulation time 46768917 ps
CPU time 0.66 seconds
Started Aug 08 05:11:52 PM PDT 24
Finished Aug 08 05:11:53 PM PDT 24
Peak memory 194460 kb
Host smart-2b30c135-109b-4c15-bca1-f4b6a873d421
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682787429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1682787429
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.288688131
Short name T829
Test name
Test status
Simulation time 97362476 ps
CPU time 0.75 seconds
Started Aug 08 05:11:47 PM PDT 24
Finished Aug 08 05:11:48 PM PDT 24
Peak memory 197228 kb
Host smart-b9b19707-a210-4bb2-8b30-a1edb2ae2662
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288688131 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 18.gpio_same_csr_outstanding.288688131
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3394768523
Short name T780
Test name
Test status
Simulation time 268796671 ps
CPU time 2.57 seconds
Started Aug 08 05:11:38 PM PDT 24
Finished Aug 08 05:11:41 PM PDT 24
Peak memory 198788 kb
Host smart-a9135525-6f2f-4c6e-aa2c-aa08ee081726
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394768523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3394768523
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1658835153
Short name T28
Test name
Test status
Simulation time 277628826 ps
CPU time 1.14 seconds
Started Aug 08 05:11:45 PM PDT 24
Finished Aug 08 05:11:46 PM PDT 24
Peak memory 198760 kb
Host smart-b6229965-d62b-47fb-a1d0-e7536fc16fb6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658835153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1658835153
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1487027547
Short name T720
Test name
Test status
Simulation time 31387439 ps
CPU time 1.3 seconds
Started Aug 08 05:11:41 PM PDT 24
Finished Aug 08 05:11:42 PM PDT 24
Peak memory 198756 kb
Host smart-6b742bc7-3ed7-4c62-8c4c-28e4a3ae5a20
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487027547 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1487027547
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2883611654
Short name T749
Test name
Test status
Simulation time 43303001 ps
CPU time 0.6 seconds
Started Aug 08 05:11:47 PM PDT 24
Finished Aug 08 05:11:47 PM PDT 24
Peak memory 195440 kb
Host smart-c337c9fe-92cf-4d6c-995e-9690ebc1487d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883611654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2883611654
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3374227233
Short name T723
Test name
Test status
Simulation time 12126586 ps
CPU time 0.61 seconds
Started Aug 08 05:11:49 PM PDT 24
Finished Aug 08 05:11:50 PM PDT 24
Peak memory 194416 kb
Host smart-f54523ee-d150-49a4-85a8-4b8f9b712f7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374227233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3374227233
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1332130144
Short name T787
Test name
Test status
Simulation time 50083885 ps
CPU time 0.94 seconds
Started Aug 08 05:11:38 PM PDT 24
Finished Aug 08 05:11:40 PM PDT 24
Peak memory 197820 kb
Host smart-d336feed-ccc1-42fa-b5b4-563891803b3d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332130144 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1332130144
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2872486111
Short name T821
Test name
Test status
Simulation time 380647381 ps
CPU time 2.15 seconds
Started Aug 08 05:11:50 PM PDT 24
Finished Aug 08 05:11:53 PM PDT 24
Peak memory 198716 kb
Host smart-b9a60b79-c364-47eb-95bf-1b808a538b99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872486111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2872486111
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1030888197
Short name T27
Test name
Test status
Simulation time 322010507 ps
CPU time 1.25 seconds
Started Aug 08 05:11:37 PM PDT 24
Finished Aug 08 05:11:38 PM PDT 24
Peak memory 198712 kb
Host smart-9470abfb-ec10-44a5-b4ef-bb95ec8c13ec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030888197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.1030888197
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.836747621
Short name T83
Test name
Test status
Simulation time 101223840 ps
CPU time 0.86 seconds
Started Aug 08 05:11:34 PM PDT 24
Finished Aug 08 05:11:35 PM PDT 24
Peak memory 196696 kb
Host smart-3360e38e-69b0-4362-b1b1-cec1cbad7f60
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836747621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.836747621
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.595448279
Short name T808
Test name
Test status
Simulation time 33974858 ps
CPU time 1.4 seconds
Started Aug 08 05:11:31 PM PDT 24
Finished Aug 08 05:11:32 PM PDT 24
Peak memory 197344 kb
Host smart-28ac1278-9ca8-4ae1-b12a-3e3156fb6f4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595448279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.595448279
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3132650458
Short name T85
Test name
Test status
Simulation time 16364446 ps
CPU time 0.67 seconds
Started Aug 08 05:11:35 PM PDT 24
Finished Aug 08 05:11:36 PM PDT 24
Peak memory 195692 kb
Host smart-3b524600-b23c-40c0-a0d8-3d351d1803f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132650458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.3132650458
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3647727247
Short name T724
Test name
Test status
Simulation time 16045267 ps
CPU time 0.7 seconds
Started Aug 08 05:11:32 PM PDT 24
Finished Aug 08 05:11:33 PM PDT 24
Peak memory 197960 kb
Host smart-1b0837b7-b4d4-4ed3-bffa-3c5444e0b6c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647727247 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3647727247
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3010062807
Short name T88
Test name
Test status
Simulation time 39499416 ps
CPU time 0.6 seconds
Started Aug 08 05:11:39 PM PDT 24
Finished Aug 08 05:11:40 PM PDT 24
Peak memory 195384 kb
Host smart-cc8ff96f-a300-4820-a2c7-2d131d198d5d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010062807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3010062807
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.4239111935
Short name T751
Test name
Test status
Simulation time 58573726 ps
CPU time 0.63 seconds
Started Aug 08 05:11:37 PM PDT 24
Finished Aug 08 05:11:38 PM PDT 24
Peak memory 194600 kb
Host smart-8b4856f8-f281-4643-aeae-31742dc157eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239111935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.4239111935
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.4011597935
Short name T771
Test name
Test status
Simulation time 76352352 ps
CPU time 0.74 seconds
Started Aug 08 05:11:27 PM PDT 24
Finished Aug 08 05:11:28 PM PDT 24
Peak memory 195640 kb
Host smart-84967e63-827f-4cdc-b426-5b11960ed566
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011597935 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.4011597935
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3080559262
Short name T769
Test name
Test status
Simulation time 69704421 ps
CPU time 2.04 seconds
Started Aug 08 05:11:26 PM PDT 24
Finished Aug 08 05:11:29 PM PDT 24
Peak memory 198732 kb
Host smart-85a33568-2955-4373-b758-430f5927c6d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080559262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.3080559262
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.4110942172
Short name T39
Test name
Test status
Simulation time 117778293 ps
CPU time 1.59 seconds
Started Aug 08 05:11:32 PM PDT 24
Finished Aug 08 05:11:33 PM PDT 24
Peak memory 198656 kb
Host smart-6f5fa5f3-92b6-49dc-a82c-6885b706d404
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110942172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.4110942172
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3070124013
Short name T727
Test name
Test status
Simulation time 42433712 ps
CPU time 0.63 seconds
Started Aug 08 05:11:47 PM PDT 24
Finished Aug 08 05:11:48 PM PDT 24
Peak memory 194520 kb
Host smart-45829c9b-d2e2-4f7f-9949-2d5730a2d02e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070124013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3070124013
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3452633354
Short name T763
Test name
Test status
Simulation time 10635282 ps
CPU time 0.57 seconds
Started Aug 08 05:11:47 PM PDT 24
Finished Aug 08 05:11:48 PM PDT 24
Peak memory 194376 kb
Host smart-87e44480-5f7f-45e5-9bce-28eb70e9ddba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452633354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3452633354
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2945861104
Short name T734
Test name
Test status
Simulation time 14304009 ps
CPU time 0.6 seconds
Started Aug 08 05:11:44 PM PDT 24
Finished Aug 08 05:11:45 PM PDT 24
Peak memory 195148 kb
Host smart-4381dfbb-c41c-4ad3-ac45-7f5689d849f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945861104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2945861104
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1713624375
Short name T828
Test name
Test status
Simulation time 14270020 ps
CPU time 0.61 seconds
Started Aug 08 05:11:38 PM PDT 24
Finished Aug 08 05:11:39 PM PDT 24
Peak memory 194456 kb
Host smart-e34e8757-a75c-46f3-a700-7942d77f3033
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713624375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1713624375
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.180736127
Short name T799
Test name
Test status
Simulation time 41596274 ps
CPU time 0.61 seconds
Started Aug 08 05:11:38 PM PDT 24
Finished Aug 08 05:11:39 PM PDT 24
Peak memory 194364 kb
Host smart-4169de5a-565a-4731-a6a7-a10fa86feaf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180736127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.180736127
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2356629686
Short name T768
Test name
Test status
Simulation time 19636322 ps
CPU time 0.64 seconds
Started Aug 08 05:11:36 PM PDT 24
Finished Aug 08 05:11:37 PM PDT 24
Peak memory 195020 kb
Host smart-05c3c51c-a791-400c-aa44-e642cc5a9af1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356629686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2356629686
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3486010843
Short name T725
Test name
Test status
Simulation time 16716326 ps
CPU time 0.65 seconds
Started Aug 08 05:11:41 PM PDT 24
Finished Aug 08 05:11:42 PM PDT 24
Peak memory 195000 kb
Host smart-cd8ea69a-a9c8-4c6c-b7c9-1d6d74fe8b51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486010843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3486010843
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.2738368052
Short name T770
Test name
Test status
Simulation time 15311624 ps
CPU time 0.68 seconds
Started Aug 08 05:11:41 PM PDT 24
Finished Aug 08 05:11:41 PM PDT 24
Peak memory 195120 kb
Host smart-c6fa65af-9eea-4b57-a0cc-e1eaf3ac8658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738368052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.2738368052
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.128797962
Short name T794
Test name
Test status
Simulation time 12845328 ps
CPU time 0.56 seconds
Started Aug 08 05:11:35 PM PDT 24
Finished Aug 08 05:11:35 PM PDT 24
Peak memory 194376 kb
Host smart-82064745-8edd-4321-9cbd-0a5904c37d08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128797962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.128797962
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2975039125
Short name T806
Test name
Test status
Simulation time 31411002 ps
CPU time 0.65 seconds
Started Aug 08 05:11:41 PM PDT 24
Finished Aug 08 05:11:42 PM PDT 24
Peak memory 194552 kb
Host smart-e53f3198-445c-4ef2-9440-f3835b9b07fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975039125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2975039125
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.4092735422
Short name T86
Test name
Test status
Simulation time 16310396 ps
CPU time 0.78 seconds
Started Aug 08 05:11:32 PM PDT 24
Finished Aug 08 05:11:33 PM PDT 24
Peak memory 196596 kb
Host smart-72807d77-9b3e-46c3-b3b9-2679de8fa84d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092735422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.4092735422
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3282519226
Short name T107
Test name
Test status
Simulation time 503972383 ps
CPU time 3.08 seconds
Started Aug 08 05:11:37 PM PDT 24
Finished Aug 08 05:11:41 PM PDT 24
Peak memory 197068 kb
Host smart-762cd998-8dc5-4d67-b8b4-c275f735768f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282519226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3282519226
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1094578875
Short name T80
Test name
Test status
Simulation time 16912658 ps
CPU time 0.61 seconds
Started Aug 08 05:11:40 PM PDT 24
Finished Aug 08 05:11:41 PM PDT 24
Peak memory 195264 kb
Host smart-375877a2-473f-4b71-aed6-5a0f67d2150e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094578875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1094578875
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1816942724
Short name T730
Test name
Test status
Simulation time 88163145 ps
CPU time 0.78 seconds
Started Aug 08 05:11:26 PM PDT 24
Finished Aug 08 05:11:27 PM PDT 24
Peak memory 198656 kb
Host smart-abe4dc25-a7c2-4526-b7d2-46495b6af5e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816942724 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1816942724
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1686417346
Short name T816
Test name
Test status
Simulation time 53082762 ps
CPU time 0.65 seconds
Started Aug 08 05:11:33 PM PDT 24
Finished Aug 08 05:11:34 PM PDT 24
Peak memory 195432 kb
Host smart-175f77bb-58e9-4050-b194-0928d9864ece
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686417346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1686417346
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1556179831
Short name T766
Test name
Test status
Simulation time 11407504 ps
CPU time 0.61 seconds
Started Aug 08 05:11:27 PM PDT 24
Finished Aug 08 05:11:28 PM PDT 24
Peak memory 194376 kb
Host smart-e88b0fb9-98e3-4f0b-9c4c-378773714c76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556179831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1556179831
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1106924263
Short name T92
Test name
Test status
Simulation time 53609786 ps
CPU time 0.71 seconds
Started Aug 08 05:11:36 PM PDT 24
Finished Aug 08 05:11:37 PM PDT 24
Peak memory 195220 kb
Host smart-fd7afb52-3f64-434f-b20c-c299c2193c7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106924263 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1106924263
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3271064492
Short name T743
Test name
Test status
Simulation time 104070124 ps
CPU time 1.31 seconds
Started Aug 08 05:11:32 PM PDT 24
Finished Aug 08 05:11:34 PM PDT 24
Peak memory 198732 kb
Host smart-b7bdd50a-1ba9-404a-82cf-a30e514fad6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271064492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3271064492
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1742349126
Short name T801
Test name
Test status
Simulation time 42943299 ps
CPU time 0.61 seconds
Started Aug 08 05:11:47 PM PDT 24
Finished Aug 08 05:11:48 PM PDT 24
Peak memory 195040 kb
Host smart-ce861086-b5ae-496e-807c-1c958dacd43f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742349126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1742349126
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3132550615
Short name T753
Test name
Test status
Simulation time 23365063 ps
CPU time 0.59 seconds
Started Aug 08 05:11:49 PM PDT 24
Finished Aug 08 05:11:50 PM PDT 24
Peak memory 194504 kb
Host smart-34b327eb-2fda-4871-a8ce-8f9054085dbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132550615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3132550615
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1017620929
Short name T827
Test name
Test status
Simulation time 27829587 ps
CPU time 0.62 seconds
Started Aug 08 05:11:50 PM PDT 24
Finished Aug 08 05:11:50 PM PDT 24
Peak memory 194984 kb
Host smart-731c2edc-2bb3-4a96-acf4-96b96f675689
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017620929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1017620929
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1723408470
Short name T765
Test name
Test status
Simulation time 13697382 ps
CPU time 0.61 seconds
Started Aug 08 05:11:46 PM PDT 24
Finished Aug 08 05:11:47 PM PDT 24
Peak memory 194480 kb
Host smart-2e8882a6-7db2-4d14-9ae1-4b8555b19bef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723408470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1723408470
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.791469265
Short name T830
Test name
Test status
Simulation time 30428515 ps
CPU time 0.58 seconds
Started Aug 08 05:11:54 PM PDT 24
Finished Aug 08 05:11:54 PM PDT 24
Peak memory 194420 kb
Host smart-49993b66-d69a-4f92-8a20-d2c31b2dcd59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791469265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.791469265
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3868695035
Short name T764
Test name
Test status
Simulation time 15516922 ps
CPU time 0.6 seconds
Started Aug 08 05:11:43 PM PDT 24
Finished Aug 08 05:11:44 PM PDT 24
Peak memory 194452 kb
Host smart-c8ba21d6-c249-4690-9d39-48eac20c113c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868695035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3868695035
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2295384037
Short name T786
Test name
Test status
Simulation time 13218662 ps
CPU time 0.6 seconds
Started Aug 08 05:11:47 PM PDT 24
Finished Aug 08 05:11:48 PM PDT 24
Peak memory 194344 kb
Host smart-7deea906-6843-48d2-8f5b-217c5d25778c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295384037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2295384037
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3472161907
Short name T728
Test name
Test status
Simulation time 48957718 ps
CPU time 0.58 seconds
Started Aug 08 05:11:51 PM PDT 24
Finished Aug 08 05:11:52 PM PDT 24
Peak memory 194396 kb
Host smart-73bc7713-63ca-4b96-ba9b-a4a2497c662d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472161907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3472161907
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3221367066
Short name T772
Test name
Test status
Simulation time 13931775 ps
CPU time 0.6 seconds
Started Aug 08 05:11:45 PM PDT 24
Finished Aug 08 05:11:46 PM PDT 24
Peak memory 194524 kb
Host smart-052dc3be-ba8a-4922-a541-6742ba848040
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221367066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3221367066
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2357141928
Short name T783
Test name
Test status
Simulation time 66248450 ps
CPU time 0.61 seconds
Started Aug 08 05:11:49 PM PDT 24
Finished Aug 08 05:11:55 PM PDT 24
Peak memory 194480 kb
Host smart-f77c3bba-6d40-438d-8484-9944b11c9cd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357141928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2357141928
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1690359794
Short name T79
Test name
Test status
Simulation time 55315852 ps
CPU time 0.73 seconds
Started Aug 08 05:11:26 PM PDT 24
Finished Aug 08 05:11:27 PM PDT 24
Peak memory 196680 kb
Host smart-6e5e768d-95f6-492e-8319-20919be1df63
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690359794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.1690359794
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3995924516
Short name T106
Test name
Test status
Simulation time 77578242 ps
CPU time 1.34 seconds
Started Aug 08 05:11:41 PM PDT 24
Finished Aug 08 05:11:42 PM PDT 24
Peak memory 197460 kb
Host smart-b4bbebef-bf61-4ffc-8fe5-b3272c376d9d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995924516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.3995924516
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.85604833
Short name T105
Test name
Test status
Simulation time 18176595 ps
CPU time 0.67 seconds
Started Aug 08 05:11:32 PM PDT 24
Finished Aug 08 05:11:33 PM PDT 24
Peak memory 195528 kb
Host smart-3f91767f-ddad-4a5b-8ae8-73ecb6cd0e87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85604833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.85604833
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1363391512
Short name T744
Test name
Test status
Simulation time 30877893 ps
CPU time 0.71 seconds
Started Aug 08 05:11:37 PM PDT 24
Finished Aug 08 05:11:38 PM PDT 24
Peak memory 198572 kb
Host smart-5b32264d-d2e1-4329-adf3-5e271d3a8f2e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363391512 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1363391512
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.428276464
Short name T774
Test name
Test status
Simulation time 52405284 ps
CPU time 0.63 seconds
Started Aug 08 05:11:39 PM PDT 24
Finished Aug 08 05:11:41 PM PDT 24
Peak memory 195232 kb
Host smart-3679a2f8-0625-4b8e-9747-e3c416b7cab6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428276464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.428276464
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.4208801903
Short name T773
Test name
Test status
Simulation time 14533302 ps
CPU time 0.62 seconds
Started Aug 08 05:11:35 PM PDT 24
Finished Aug 08 05:11:36 PM PDT 24
Peak memory 194436 kb
Host smart-c805b526-bf46-41d8-9cf4-d8295ee28988
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208801903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.4208801903
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1837160287
Short name T782
Test name
Test status
Simulation time 17177928 ps
CPU time 0.65 seconds
Started Aug 08 05:11:29 PM PDT 24
Finished Aug 08 05:11:29 PM PDT 24
Peak memory 195828 kb
Host smart-11619a8d-2b7a-4bfd-9430-f014dc515188
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837160287 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1837160287
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3103349547
Short name T811
Test name
Test status
Simulation time 149864294 ps
CPU time 1.19 seconds
Started Aug 08 05:11:30 PM PDT 24
Finished Aug 08 05:11:32 PM PDT 24
Peak memory 198684 kb
Host smart-7d994228-0d4c-4ecc-ae16-c292cea2e535
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103349547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3103349547
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1385016688
Short name T40
Test name
Test status
Simulation time 161070643 ps
CPU time 0.87 seconds
Started Aug 08 05:11:28 PM PDT 24
Finished Aug 08 05:11:29 PM PDT 24
Peak memory 197516 kb
Host smart-8d02e086-8b80-44ef-83c5-4ff8cd4e4db8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385016688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1385016688
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.231773780
Short name T826
Test name
Test status
Simulation time 17419801 ps
CPU time 0.59 seconds
Started Aug 08 05:11:52 PM PDT 24
Finished Aug 08 05:11:57 PM PDT 24
Peak memory 194416 kb
Host smart-743e7a4c-2394-41f5-a72d-f672facbb72d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231773780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.231773780
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.186312571
Short name T745
Test name
Test status
Simulation time 27772687 ps
CPU time 0.61 seconds
Started Aug 08 05:11:51 PM PDT 24
Finished Aug 08 05:11:52 PM PDT 24
Peak memory 194320 kb
Host smart-10ba5fe1-8f8f-40e3-b37f-6bed85b40444
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186312571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.186312571
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2201487946
Short name T729
Test name
Test status
Simulation time 87058620 ps
CPU time 0.58 seconds
Started Aug 08 05:11:52 PM PDT 24
Finished Aug 08 05:11:53 PM PDT 24
Peak memory 195128 kb
Host smart-bb755764-d5c9-4c08-bca6-7c5e524d5bc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201487946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2201487946
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2918160605
Short name T721
Test name
Test status
Simulation time 18982491 ps
CPU time 0.63 seconds
Started Aug 08 05:11:49 PM PDT 24
Finished Aug 08 05:11:50 PM PDT 24
Peak memory 194416 kb
Host smart-cfb39d95-7882-4376-b05b-11956368ea33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918160605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2918160605
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2245439279
Short name T737
Test name
Test status
Simulation time 23480838 ps
CPU time 0.61 seconds
Started Aug 08 05:11:48 PM PDT 24
Finished Aug 08 05:11:49 PM PDT 24
Peak memory 194968 kb
Host smart-ff94bd1d-d489-45a0-b05b-70d4754fdae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245439279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2245439279
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3265789821
Short name T733
Test name
Test status
Simulation time 15020184 ps
CPU time 0.63 seconds
Started Aug 08 05:11:48 PM PDT 24
Finished Aug 08 05:11:49 PM PDT 24
Peak memory 194484 kb
Host smart-4d481182-1050-4452-bab7-cd1b8f87f37a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265789821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3265789821
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.4086011985
Short name T795
Test name
Test status
Simulation time 40780220 ps
CPU time 0.6 seconds
Started Aug 08 05:11:51 PM PDT 24
Finished Aug 08 05:11:52 PM PDT 24
Peak memory 195004 kb
Host smart-dd9c8dc4-2f2f-497f-a4f9-f9a21d13892d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086011985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.4086011985
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3095101602
Short name T752
Test name
Test status
Simulation time 17452946 ps
CPU time 0.62 seconds
Started Aug 08 05:11:48 PM PDT 24
Finished Aug 08 05:11:49 PM PDT 24
Peak memory 195088 kb
Host smart-9857b27e-8ed1-4568-809a-dc91b795a74e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095101602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3095101602
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.303477896
Short name T722
Test name
Test status
Simulation time 12809418 ps
CPU time 0.62 seconds
Started Aug 08 05:11:49 PM PDT 24
Finished Aug 08 05:11:50 PM PDT 24
Peak memory 194524 kb
Host smart-9c6bd0b4-4ea8-46d1-b86e-56f2581a6662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303477896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.303477896
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3309849760
Short name T740
Test name
Test status
Simulation time 38310571 ps
CPU time 0.6 seconds
Started Aug 08 05:11:46 PM PDT 24
Finished Aug 08 05:11:52 PM PDT 24
Peak memory 194416 kb
Host smart-9ab781d5-493b-40c6-8ba2-a4c048ad407c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309849760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3309849760
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.508633331
Short name T831
Test name
Test status
Simulation time 71008354 ps
CPU time 0.73 seconds
Started Aug 08 05:11:30 PM PDT 24
Finished Aug 08 05:11:31 PM PDT 24
Peak memory 198412 kb
Host smart-5220c565-5efb-4a13-babc-41b703c5a67e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508633331 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.508633331
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3352242562
Short name T792
Test name
Test status
Simulation time 52569200 ps
CPU time 0.63 seconds
Started Aug 08 05:11:26 PM PDT 24
Finished Aug 08 05:11:27 PM PDT 24
Peak memory 195436 kb
Host smart-0115d683-e1ab-4cea-b655-c0dbf6e7da6a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352242562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3352242562
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.4219988634
Short name T824
Test name
Test status
Simulation time 26302204 ps
CPU time 0.57 seconds
Started Aug 08 05:11:38 PM PDT 24
Finished Aug 08 05:11:39 PM PDT 24
Peak memory 194420 kb
Host smart-422384f3-0e0e-4ed0-8f0f-fea0ca19f917
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219988634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.4219988634
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3593198265
Short name T812
Test name
Test status
Simulation time 73598191 ps
CPU time 0.92 seconds
Started Aug 08 05:11:36 PM PDT 24
Finished Aug 08 05:11:37 PM PDT 24
Peak memory 198564 kb
Host smart-bb6c2718-901e-41c3-9531-cd81068ecb57
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593198265 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3593198265
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2852392200
Short name T776
Test name
Test status
Simulation time 64410144 ps
CPU time 1.49 seconds
Started Aug 08 05:11:32 PM PDT 24
Finished Aug 08 05:11:34 PM PDT 24
Peak memory 198804 kb
Host smart-6d8d8ed2-2c5d-42cb-869d-2f3e9bcc554a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852392200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2852392200
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1363872547
Short name T822
Test name
Test status
Simulation time 565989814 ps
CPU time 1.48 seconds
Started Aug 08 05:11:28 PM PDT 24
Finished Aug 08 05:11:29 PM PDT 24
Peak memory 198608 kb
Host smart-5095d93e-82a2-4955-ba6d-8f7f14009737
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363872547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1363872547
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.201160779
Short name T746
Test name
Test status
Simulation time 39615911 ps
CPU time 0.79 seconds
Started Aug 08 05:11:37 PM PDT 24
Finished Aug 08 05:11:38 PM PDT 24
Peak memory 198532 kb
Host smart-141322e0-0de2-4566-9dee-ca208b9ad85a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201160779 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.201160779
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.354163925
Short name T81
Test name
Test status
Simulation time 47240802 ps
CPU time 0.64 seconds
Started Aug 08 05:11:30 PM PDT 24
Finished Aug 08 05:11:31 PM PDT 24
Peak memory 195468 kb
Host smart-9649ba15-85fc-4094-afb1-79debf7e0056
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354163925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.354163925
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3665054984
Short name T804
Test name
Test status
Simulation time 31855256 ps
CPU time 0.62 seconds
Started Aug 08 05:11:36 PM PDT 24
Finished Aug 08 05:11:37 PM PDT 24
Peak memory 194568 kb
Host smart-22de2810-e1af-485f-bbcb-0422c61a75d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665054984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3665054984
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.386991170
Short name T76
Test name
Test status
Simulation time 77353025 ps
CPU time 0.77 seconds
Started Aug 08 05:11:39 PM PDT 24
Finished Aug 08 05:11:40 PM PDT 24
Peak memory 196360 kb
Host smart-2892ff8e-c3e0-495f-85c3-9abcbcccdd14
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386991170 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.386991170
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2298558996
Short name T839
Test name
Test status
Simulation time 147340061 ps
CPU time 3.18 seconds
Started Aug 08 05:11:28 PM PDT 24
Finished Aug 08 05:11:31 PM PDT 24
Peak memory 198712 kb
Host smart-fdfd8e2e-a1ae-4cb6-b910-f70ffcc69d01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298558996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2298558996
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.282863157
Short name T37
Test name
Test status
Simulation time 45889011 ps
CPU time 0.9 seconds
Started Aug 08 05:11:30 PM PDT 24
Finished Aug 08 05:11:31 PM PDT 24
Peak memory 197660 kb
Host smart-cfc0fff5-7062-44a8-961d-10d15d8e1b34
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282863157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.282863157
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3411210076
Short name T823
Test name
Test status
Simulation time 18339353 ps
CPU time 0.91 seconds
Started Aug 08 05:11:27 PM PDT 24
Finished Aug 08 05:11:28 PM PDT 24
Peak memory 198572 kb
Host smart-306b064d-7d14-4af0-bc01-7d2445dcb0d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411210076 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.3411210076
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1169540744
Short name T833
Test name
Test status
Simulation time 47508535 ps
CPU time 0.63 seconds
Started Aug 08 05:11:38 PM PDT 24
Finished Aug 08 05:11:39 PM PDT 24
Peak memory 195592 kb
Host smart-68b2978d-6bdf-41d4-8f28-b926499fe7c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169540744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1169540744
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.683648533
Short name T767
Test name
Test status
Simulation time 16050146 ps
CPU time 0.62 seconds
Started Aug 08 05:11:33 PM PDT 24
Finished Aug 08 05:11:34 PM PDT 24
Peak memory 194376 kb
Host smart-e5940374-d781-48ff-9117-1b8eadda15f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683648533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.683648533
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1964807810
Short name T94
Test name
Test status
Simulation time 123741783 ps
CPU time 0.76 seconds
Started Aug 08 05:11:36 PM PDT 24
Finished Aug 08 05:11:37 PM PDT 24
Peak memory 196456 kb
Host smart-76d04ef2-4037-4123-8cc3-7c1a7046e6c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964807810 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1964807810
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.433887111
Short name T736
Test name
Test status
Simulation time 25953572 ps
CPU time 1.25 seconds
Started Aug 08 05:11:32 PM PDT 24
Finished Aug 08 05:11:33 PM PDT 24
Peak memory 198796 kb
Host smart-980e136f-dc86-4cfa-b52a-bc0feaadee51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433887111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.433887111
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3495990611
Short name T747
Test name
Test status
Simulation time 31550407 ps
CPU time 0.9 seconds
Started Aug 08 05:11:38 PM PDT 24
Finished Aug 08 05:11:39 PM PDT 24
Peak memory 198528 kb
Host smart-08762562-9dca-477c-8489-91e7f61a8df8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495990611 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3495990611
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1185973709
Short name T78
Test name
Test status
Simulation time 28747289 ps
CPU time 0.6 seconds
Started Aug 08 05:11:30 PM PDT 24
Finished Aug 08 05:11:31 PM PDT 24
Peak memory 195156 kb
Host smart-35c06443-d854-47c4-8678-1c6105ba7bd9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185973709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.1185973709
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3674605956
Short name T817
Test name
Test status
Simulation time 23596890 ps
CPU time 0.65 seconds
Started Aug 08 05:11:36 PM PDT 24
Finished Aug 08 05:11:37 PM PDT 24
Peak memory 194400 kb
Host smart-04ca14c8-0b9e-4610-b6a3-e914cf722066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674605956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3674605956
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1444835043
Short name T800
Test name
Test status
Simulation time 60264323 ps
CPU time 0.77 seconds
Started Aug 08 05:11:33 PM PDT 24
Finished Aug 08 05:11:34 PM PDT 24
Peak memory 197364 kb
Host smart-ce8876ee-e021-4432-b3cf-4773878349b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444835043 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1444835043
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.750749884
Short name T820
Test name
Test status
Simulation time 48099038 ps
CPU time 2.37 seconds
Started Aug 08 05:11:37 PM PDT 24
Finished Aug 08 05:11:39 PM PDT 24
Peak memory 198692 kb
Host smart-ebb74657-a811-4c12-9eb9-fd84a7c13185
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750749884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.750749884
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3273745810
Short name T775
Test name
Test status
Simulation time 39742107 ps
CPU time 0.91 seconds
Started Aug 08 05:11:27 PM PDT 24
Finished Aug 08 05:11:28 PM PDT 24
Peak memory 198036 kb
Host smart-ac8f0486-3e41-4590-aaca-df4510ab8617
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273745810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3273745810
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3238772005
Short name T838
Test name
Test status
Simulation time 30810224 ps
CPU time 0.81 seconds
Started Aug 08 05:11:43 PM PDT 24
Finished Aug 08 05:11:44 PM PDT 24
Peak memory 198528 kb
Host smart-c6592489-a19f-4746-a5d0-97c063568e7f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238772005 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3238772005
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2048997930
Short name T87
Test name
Test status
Simulation time 72566119 ps
CPU time 0.58 seconds
Started Aug 08 05:11:33 PM PDT 24
Finished Aug 08 05:11:33 PM PDT 24
Peak memory 194252 kb
Host smart-ab195d1b-f1ef-404a-8e5f-8a0c696e72e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048997930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2048997930
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3751869093
Short name T756
Test name
Test status
Simulation time 10340447 ps
CPU time 0.58 seconds
Started Aug 08 05:11:41 PM PDT 24
Finished Aug 08 05:11:42 PM PDT 24
Peak memory 194448 kb
Host smart-ca1f43ae-c3d2-486f-88af-8c35efe9d0c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751869093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3751869093
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.4121106640
Short name T807
Test name
Test status
Simulation time 66368734 ps
CPU time 0.64 seconds
Started Aug 08 05:11:42 PM PDT 24
Finished Aug 08 05:11:42 PM PDT 24
Peak memory 196172 kb
Host smart-2c4fdd35-f843-4f70-b552-7beb0c9bcca6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121106640 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.4121106640
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3752832184
Short name T798
Test name
Test status
Simulation time 62179335 ps
CPU time 1.4 seconds
Started Aug 08 05:11:38 PM PDT 24
Finished Aug 08 05:11:40 PM PDT 24
Peak memory 198680 kb
Host smart-bc18d445-dc5d-4813-ab7d-927d20ba72ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752832184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3752832184
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3121970159
Short name T814
Test name
Test status
Simulation time 427751758 ps
CPU time 1.46 seconds
Started Aug 08 05:11:30 PM PDT 24
Finished Aug 08 05:11:32 PM PDT 24
Peak memory 198616 kb
Host smart-128a3baf-e67e-47bd-8f6e-c8ff1f0c377d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121970159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3121970159
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.112023526
Short name T259
Test name
Test status
Simulation time 53958197 ps
CPU time 0.57 seconds
Started Aug 08 05:12:18 PM PDT 24
Finished Aug 08 05:12:19 PM PDT 24
Peak memory 194384 kb
Host smart-82dd473b-b57e-4a7b-82c8-b6b4775dc9bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112023526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.112023526
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2773283964
Short name T604
Test name
Test status
Simulation time 150291902 ps
CPU time 0.78 seconds
Started Aug 08 05:11:56 PM PDT 24
Finished Aug 08 05:11:57 PM PDT 24
Peak memory 195832 kb
Host smart-28a7958a-ae89-42b6-a294-b332189608db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773283964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2773283964
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3075667183
Short name T98
Test name
Test status
Simulation time 792050833 ps
CPU time 24.3 seconds
Started Aug 08 05:12:17 PM PDT 24
Finished Aug 08 05:12:42 PM PDT 24
Peak memory 196688 kb
Host smart-9370b8d7-0067-4b77-bb7c-c98009e52a2b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075667183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3075667183
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3202096285
Short name T549
Test name
Test status
Simulation time 341714090 ps
CPU time 0.68 seconds
Started Aug 08 05:12:17 PM PDT 24
Finished Aug 08 05:12:18 PM PDT 24
Peak memory 194928 kb
Host smart-735ac2c9-d2fa-4443-94d7-fb1ce0169a43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202096285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3202096285
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2807890666
Short name T47
Test name
Test status
Simulation time 319507506 ps
CPU time 1.26 seconds
Started Aug 08 05:12:10 PM PDT 24
Finished Aug 08 05:12:11 PM PDT 24
Peak memory 196656 kb
Host smart-525e52f3-30ba-4b74-b41d-faffd16b4297
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807890666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2807890666
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.135936896
Short name T563
Test name
Test status
Simulation time 58166195 ps
CPU time 2.42 seconds
Started Aug 08 05:12:00 PM PDT 24
Finished Aug 08 05:12:03 PM PDT 24
Peak memory 198472 kb
Host smart-67114406-4a90-40cc-9327-9765ad171600
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135936896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.135936896
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1652582152
Short name T236
Test name
Test status
Simulation time 490464748 ps
CPU time 1.43 seconds
Started Aug 08 05:12:13 PM PDT 24
Finished Aug 08 05:12:14 PM PDT 24
Peak memory 196624 kb
Host smart-1775dd71-d9bd-47bd-af1d-7e7be6a484c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652582152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1652582152
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1456517197
Short name T412
Test name
Test status
Simulation time 98921364 ps
CPU time 1.13 seconds
Started Aug 08 05:12:07 PM PDT 24
Finished Aug 08 05:12:08 PM PDT 24
Peak memory 197628 kb
Host smart-28cfdae1-7015-4619-906e-2cee066d18dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456517197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1456517197
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3463099663
Short name T663
Test name
Test status
Simulation time 122673915 ps
CPU time 0.7 seconds
Started Aug 08 05:12:12 PM PDT 24
Finished Aug 08 05:12:13 PM PDT 24
Peak memory 195436 kb
Host smart-17829ea2-6079-4d1b-8017-fb2eec0d594d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463099663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3463099663
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2601308781
Short name T354
Test name
Test status
Simulation time 78016170 ps
CPU time 1.29 seconds
Started Aug 08 05:12:06 PM PDT 24
Finished Aug 08 05:12:08 PM PDT 24
Peak memory 198360 kb
Host smart-a406d4ed-f422-412a-bfa9-9e10b0ee82d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601308781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2601308781
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.4258953999
Short name T516
Test name
Test status
Simulation time 34514942 ps
CPU time 0.77 seconds
Started Aug 08 05:12:07 PM PDT 24
Finished Aug 08 05:12:08 PM PDT 24
Peak memory 195520 kb
Host smart-3c89df63-785b-4dc1-ad39-4225adf56e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258953999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.4258953999
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2816727710
Short name T131
Test name
Test status
Simulation time 67307397 ps
CPU time 1.31 seconds
Started Aug 08 05:12:06 PM PDT 24
Finished Aug 08 05:12:07 PM PDT 24
Peak memory 197308 kb
Host smart-5e235232-fba3-41c9-bbe7-8e77a8218f64
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816727710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2816727710
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1882392948
Short name T435
Test name
Test status
Simulation time 30413437397 ps
CPU time 183.97 seconds
Started Aug 08 05:12:11 PM PDT 24
Finished Aug 08 05:15:15 PM PDT 24
Peak memory 198664 kb
Host smart-cf52389f-12d6-4bf4-acfa-ab25c2dedfe8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882392948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1882392948
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2443349928
Short name T393
Test name
Test status
Simulation time 45127618 ps
CPU time 0.56 seconds
Started Aug 08 05:12:15 PM PDT 24
Finished Aug 08 05:12:16 PM PDT 24
Peak memory 194408 kb
Host smart-a38c7647-2484-4c3e-92e1-96375597ab92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443349928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2443349928
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1941488035
Short name T636
Test name
Test status
Simulation time 43387541 ps
CPU time 0.71 seconds
Started Aug 08 05:12:06 PM PDT 24
Finished Aug 08 05:12:07 PM PDT 24
Peak memory 194404 kb
Host smart-ed8d5751-880c-4e05-a5b9-65482361bfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941488035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1941488035
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1368253312
Short name T123
Test name
Test status
Simulation time 600733133 ps
CPU time 20.12 seconds
Started Aug 08 05:12:15 PM PDT 24
Finished Aug 08 05:12:35 PM PDT 24
Peak memory 197476 kb
Host smart-48a37ae5-5c00-4121-8ddc-b7df5a2b343a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368253312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1368253312
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.555071224
Short name T349
Test name
Test status
Simulation time 77616349 ps
CPU time 1.17 seconds
Started Aug 08 05:12:16 PM PDT 24
Finished Aug 08 05:12:18 PM PDT 24
Peak memory 198532 kb
Host smart-1c3f93cf-1e0d-4554-bdcc-47ca8b56be1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555071224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.555071224
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3788819498
Short name T170
Test name
Test status
Simulation time 42517558 ps
CPU time 1.25 seconds
Started Aug 08 05:12:15 PM PDT 24
Finished Aug 08 05:12:17 PM PDT 24
Peak memory 196448 kb
Host smart-3e8c38e6-9647-4eb5-a1de-ef3dc4f543a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788819498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3788819498
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3298885412
Short name T360
Test name
Test status
Simulation time 70171662 ps
CPU time 2.77 seconds
Started Aug 08 05:12:16 PM PDT 24
Finished Aug 08 05:12:19 PM PDT 24
Peak memory 198504 kb
Host smart-e01217e0-7693-46b3-b97c-a647eeafb432
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298885412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3298885412
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1701009415
Short name T628
Test name
Test status
Simulation time 61662783 ps
CPU time 1.91 seconds
Started Aug 08 05:12:05 PM PDT 24
Finished Aug 08 05:12:07 PM PDT 24
Peak memory 198512 kb
Host smart-0735fa33-6ac8-41fd-9fb7-f77167246b5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701009415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1701009415
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.120729045
Short name T285
Test name
Test status
Simulation time 88095166 ps
CPU time 0.96 seconds
Started Aug 08 05:12:16 PM PDT 24
Finished Aug 08 05:12:17 PM PDT 24
Peak memory 196516 kb
Host smart-103171b9-3618-4bb9-a0be-4dc67fe86338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120729045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.120729045
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.291356915
Short name T547
Test name
Test status
Simulation time 136208433 ps
CPU time 0.63 seconds
Started Aug 08 05:12:09 PM PDT 24
Finished Aug 08 05:12:10 PM PDT 24
Peak memory 194820 kb
Host smart-56a45bff-5f0d-45ac-bef0-f47f72fac436
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291356915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.291356915
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1629363496
Short name T574
Test name
Test status
Simulation time 1601893795 ps
CPU time 3.45 seconds
Started Aug 08 05:12:06 PM PDT 24
Finished Aug 08 05:12:10 PM PDT 24
Peak memory 198596 kb
Host smart-beb7e585-5723-4c8c-8834-564ccfc1e2f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629363496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1629363496
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.66912756
Short name T32
Test name
Test status
Simulation time 373796273 ps
CPU time 1.02 seconds
Started Aug 08 05:12:17 PM PDT 24
Finished Aug 08 05:12:18 PM PDT 24
Peak memory 215444 kb
Host smart-18cd0f8d-ee5d-4372-9084-09d6a8460625
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66912756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.66912756
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2533904387
Short name T696
Test name
Test status
Simulation time 139803951 ps
CPU time 1.23 seconds
Started Aug 08 05:12:02 PM PDT 24
Finished Aug 08 05:12:03 PM PDT 24
Peak memory 196228 kb
Host smart-9ba49fff-5db4-483a-ab82-e539415718ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533904387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2533904387
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2301770479
Short name T692
Test name
Test status
Simulation time 177651322 ps
CPU time 1.36 seconds
Started Aug 08 05:12:16 PM PDT 24
Finished Aug 08 05:12:18 PM PDT 24
Peak memory 197324 kb
Host smart-bdceddf3-1a1f-401a-890b-dc42dd5837c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301770479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2301770479
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.608026396
Short name T510
Test name
Test status
Simulation time 21998217382 ps
CPU time 85.83 seconds
Started Aug 08 05:12:17 PM PDT 24
Finished Aug 08 05:13:43 PM PDT 24
Peak memory 198680 kb
Host smart-672441fa-a698-4ed7-acfd-83cdcebb57f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608026396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.608026396
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3837838867
Short name T312
Test name
Test status
Simulation time 13863718 ps
CPU time 0.62 seconds
Started Aug 08 05:12:31 PM PDT 24
Finished Aug 08 05:12:32 PM PDT 24
Peak memory 194620 kb
Host smart-349562d4-5cfd-41e7-b0d1-bbe80565412c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837838867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3837838867
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1196993364
Short name T526
Test name
Test status
Simulation time 79763099 ps
CPU time 0.9 seconds
Started Aug 08 05:12:44 PM PDT 24
Finished Aug 08 05:12:46 PM PDT 24
Peak memory 197128 kb
Host smart-fe8818e3-4537-45b3-a422-39d7af23e3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196993364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1196993364
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.4140302790
Short name T532
Test name
Test status
Simulation time 399574230 ps
CPU time 19.85 seconds
Started Aug 08 05:12:32 PM PDT 24
Finished Aug 08 05:12:52 PM PDT 24
Peak memory 197644 kb
Host smart-076b1f03-8a79-49fa-bba9-e9844c760d25
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140302790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.4140302790
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1960741778
Short name T391
Test name
Test status
Simulation time 24013576 ps
CPU time 0.69 seconds
Started Aug 08 05:12:34 PM PDT 24
Finished Aug 08 05:12:35 PM PDT 24
Peak memory 195196 kb
Host smart-8c5b0b5a-c143-4c76-bb58-f8b024988733
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960741778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1960741778
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.642478990
Short name T479
Test name
Test status
Simulation time 101708791 ps
CPU time 1.47 seconds
Started Aug 08 05:12:32 PM PDT 24
Finished Aug 08 05:12:33 PM PDT 24
Peak memory 198596 kb
Host smart-c741124f-82e9-4d04-ba95-5e2e69a22d9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642478990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.642478990
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.612692381
Short name T377
Test name
Test status
Simulation time 56237252 ps
CPU time 2.25 seconds
Started Aug 08 05:12:31 PM PDT 24
Finished Aug 08 05:12:33 PM PDT 24
Peak memory 198488 kb
Host smart-8020b4a0-dc91-4aed-8f4e-25d35fa42325
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612692381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_intr_with_filter_rand_intr_event.612692381
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3641468425
Short name T231
Test name
Test status
Simulation time 299075148 ps
CPU time 1.56 seconds
Started Aug 08 05:12:41 PM PDT 24
Finished Aug 08 05:12:43 PM PDT 24
Peak memory 196976 kb
Host smart-6459e038-149d-43be-8ceb-b3850658245e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641468425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3641468425
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1613716562
Short name T19
Test name
Test status
Simulation time 198699419 ps
CPU time 0.77 seconds
Started Aug 08 05:12:30 PM PDT 24
Finished Aug 08 05:12:31 PM PDT 24
Peak memory 195804 kb
Host smart-a4f07ae5-ed89-402c-bd3d-7c4285dda183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613716562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1613716562
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3034030999
Short name T629
Test name
Test status
Simulation time 52315752 ps
CPU time 1.11 seconds
Started Aug 08 05:12:28 PM PDT 24
Finished Aug 08 05:12:29 PM PDT 24
Peak memory 196532 kb
Host smart-ff2a4bd4-6cf7-4efb-a341-126aca70ffe4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034030999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3034030999
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1426748784
Short name T64
Test name
Test status
Simulation time 48138646 ps
CPU time 2.12 seconds
Started Aug 08 05:12:38 PM PDT 24
Finished Aug 08 05:12:40 PM PDT 24
Peak memory 198448 kb
Host smart-41c3b19f-5f86-4223-b70f-3f428491fbb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426748784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1426748784
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.240476355
Short name T471
Test name
Test status
Simulation time 82312905 ps
CPU time 0.84 seconds
Started Aug 08 05:12:31 PM PDT 24
Finished Aug 08 05:12:32 PM PDT 24
Peak memory 195816 kb
Host smart-e3f13db0-e9a2-4520-bca8-e13fc428b01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240476355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.240476355
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.4015169886
Short name T337
Test name
Test status
Simulation time 36583296 ps
CPU time 1.1 seconds
Started Aug 08 05:12:21 PM PDT 24
Finished Aug 08 05:12:22 PM PDT 24
Peak memory 196052 kb
Host smart-b9242405-c840-4657-b65a-fed1e2d3a48e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015169886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.4015169886
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1002812837
Short name T187
Test name
Test status
Simulation time 5231953776 ps
CPU time 76.93 seconds
Started Aug 08 05:12:34 PM PDT 24
Finished Aug 08 05:13:51 PM PDT 24
Peak memory 198720 kb
Host smart-b992f019-5d54-4949-afdb-576c4fbe1321
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002812837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1002812837
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.16245954
Short name T509
Test name
Test status
Simulation time 13323883 ps
CPU time 0.6 seconds
Started Aug 08 05:12:34 PM PDT 24
Finished Aug 08 05:12:35 PM PDT 24
Peak memory 195416 kb
Host smart-a52765da-be93-4747-a9b8-6bf2d977a219
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16245954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.16245954
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2475845779
Short name T455
Test name
Test status
Simulation time 46324904 ps
CPU time 0.88 seconds
Started Aug 08 05:12:30 PM PDT 24
Finished Aug 08 05:12:31 PM PDT 24
Peak memory 196808 kb
Host smart-e8d068e3-f062-4235-89b0-eb80e43eb618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475845779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2475845779
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.177362950
Short name T219
Test name
Test status
Simulation time 130015436 ps
CPU time 3.47 seconds
Started Aug 08 05:12:40 PM PDT 24
Finished Aug 08 05:12:44 PM PDT 24
Peak memory 196352 kb
Host smart-d12d9027-2400-41a1-89aa-7d403d5edc8a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177362950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stres
s.177362950
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.189498895
Short name T302
Test name
Test status
Simulation time 143410050 ps
CPU time 1.01 seconds
Started Aug 08 05:12:30 PM PDT 24
Finished Aug 08 05:12:31 PM PDT 24
Peak memory 198348 kb
Host smart-b251a368-58d9-4c2f-b4aa-bab1b07b4947
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189498895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.189498895
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3074911222
Short name T470
Test name
Test status
Simulation time 46432587 ps
CPU time 1.17 seconds
Started Aug 08 05:12:32 PM PDT 24
Finished Aug 08 05:12:34 PM PDT 24
Peak memory 196428 kb
Host smart-ef3a2113-337d-4875-b0e5-58c729463b04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074911222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3074911222
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.75295083
Short name T54
Test name
Test status
Simulation time 50624133 ps
CPU time 1.1 seconds
Started Aug 08 05:12:30 PM PDT 24
Finished Aug 08 05:12:31 PM PDT 24
Peak memory 197828 kb
Host smart-8e59a908-8967-40cf-917e-80fa45afda99
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75295083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.gpio_intr_with_filter_rand_intr_event.75295083
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1769973980
Short name T584
Test name
Test status
Simulation time 123497681 ps
CPU time 1.22 seconds
Started Aug 08 05:12:34 PM PDT 24
Finished Aug 08 05:12:35 PM PDT 24
Peak memory 196908 kb
Host smart-35422404-4207-42cc-864c-d8d063a8844e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769973980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1769973980
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.918404499
Short name T518
Test name
Test status
Simulation time 52192281 ps
CPU time 0.71 seconds
Started Aug 08 05:12:44 PM PDT 24
Finished Aug 08 05:12:45 PM PDT 24
Peak memory 196544 kb
Host smart-1064b6b4-5adc-4786-a054-082e72dbd4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918404499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.918404499
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2315089556
Short name T531
Test name
Test status
Simulation time 44177176 ps
CPU time 0.95 seconds
Started Aug 08 05:12:33 PM PDT 24
Finished Aug 08 05:12:34 PM PDT 24
Peak memory 196252 kb
Host smart-a34538b3-90e0-445c-ab6f-c11b9f94884e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315089556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2315089556
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3749559
Short name T311
Test name
Test status
Simulation time 1490419559 ps
CPU time 3.4 seconds
Started Aug 08 05:12:42 PM PDT 24
Finished Aug 08 05:12:45 PM PDT 24
Peak memory 198456 kb
Host smart-e1836a06-3cb7-43a8-b0dd-235fe9c771a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_wr
ites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rando
m_long_reg_writes_reg_reads.3749559
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3921210572
Short name T575
Test name
Test status
Simulation time 136569194 ps
CPU time 1.37 seconds
Started Aug 08 05:12:39 PM PDT 24
Finished Aug 08 05:12:40 PM PDT 24
Peak memory 196068 kb
Host smart-4639cdad-403a-4d31-9640-6b9a628bdb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921210572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3921210572
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1160231605
Short name T521
Test name
Test status
Simulation time 1597687301 ps
CPU time 1.23 seconds
Started Aug 08 05:12:33 PM PDT 24
Finished Aug 08 05:12:35 PM PDT 24
Peak memory 196288 kb
Host smart-218950a7-412c-413b-9ebd-49a7fb978b86
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160231605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1160231605
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3700446043
Short name T260
Test name
Test status
Simulation time 18953885289 ps
CPU time 205.86 seconds
Started Aug 08 05:12:35 PM PDT 24
Finished Aug 08 05:16:01 PM PDT 24
Peak memory 198732 kb
Host smart-9a724fa6-29f6-4415-a931-2454f356c39e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700446043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3700446043
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.327679234
Short name T712
Test name
Test status
Simulation time 138691922 ps
CPU time 0.56 seconds
Started Aug 08 05:12:41 PM PDT 24
Finished Aug 08 05:12:42 PM PDT 24
Peak memory 194588 kb
Host smart-4a41711e-a6b7-4338-be18-eedd862b4f5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327679234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.327679234
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.1653092885
Short name T190
Test name
Test status
Simulation time 119153126 ps
CPU time 0.91 seconds
Started Aug 08 05:12:33 PM PDT 24
Finished Aug 08 05:12:34 PM PDT 24
Peak memory 196364 kb
Host smart-9e6535f9-c0b2-40ef-806e-5c75d54c47da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653092885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.1653092885
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2171341411
Short name T176
Test name
Test status
Simulation time 141049272 ps
CPU time 3.55 seconds
Started Aug 08 05:12:35 PM PDT 24
Finished Aug 08 05:12:38 PM PDT 24
Peak memory 196176 kb
Host smart-7127169d-3a90-4adc-8147-b94f65a63afd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171341411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2171341411
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.856573918
Short name T448
Test name
Test status
Simulation time 376606192 ps
CPU time 0.77 seconds
Started Aug 08 05:12:35 PM PDT 24
Finished Aug 08 05:12:36 PM PDT 24
Peak memory 196392 kb
Host smart-fda53c8c-ff88-4dc8-b435-e3493d5d149a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856573918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.856573918
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2294913207
Short name T306
Test name
Test status
Simulation time 36296503 ps
CPU time 0.99 seconds
Started Aug 08 05:12:35 PM PDT 24
Finished Aug 08 05:12:36 PM PDT 24
Peak memory 196280 kb
Host smart-8aee2808-5368-4b20-9c0d-0aac6fbc5b4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294913207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2294913207
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1893892946
Short name T623
Test name
Test status
Simulation time 698703595 ps
CPU time 1.93 seconds
Started Aug 08 05:12:39 PM PDT 24
Finished Aug 08 05:12:41 PM PDT 24
Peak memory 196468 kb
Host smart-84eeb7a9-d2f2-451a-80c6-b0c702dd7325
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893892946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1893892946
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.109850975
Short name T130
Test name
Test status
Simulation time 100880718 ps
CPU time 0.67 seconds
Started Aug 08 05:12:37 PM PDT 24
Finished Aug 08 05:12:38 PM PDT 24
Peak memory 194780 kb
Host smart-39d444be-16ca-491c-93f9-6e4b24687a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109850975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.109850975
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.165161596
Short name T535
Test name
Test status
Simulation time 109441997 ps
CPU time 0.83 seconds
Started Aug 08 05:12:57 PM PDT 24
Finished Aug 08 05:12:58 PM PDT 24
Peak memory 195984 kb
Host smart-dbdbd58a-4794-4eb2-99d1-d83b88d6f356
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165161596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.165161596
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1446270299
Short name T515
Test name
Test status
Simulation time 381292303 ps
CPU time 3.11 seconds
Started Aug 08 05:12:41 PM PDT 24
Finished Aug 08 05:12:44 PM PDT 24
Peak memory 198416 kb
Host smart-9b6e1977-2867-40d9-8aeb-627268cf57b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446270299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1446270299
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.488385636
Short name T624
Test name
Test status
Simulation time 159647250 ps
CPU time 0.93 seconds
Started Aug 08 05:12:35 PM PDT 24
Finished Aug 08 05:12:36 PM PDT 24
Peak memory 197552 kb
Host smart-6cf4705e-8be6-4f38-9ff8-8c607b64b37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488385636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.488385636
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.4064837261
Short name T514
Test name
Test status
Simulation time 80904231 ps
CPU time 1.22 seconds
Started Aug 08 05:12:44 PM PDT 24
Finished Aug 08 05:12:45 PM PDT 24
Peak memory 196944 kb
Host smart-fa348504-372b-438e-ae50-0a250c10decc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064837261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.4064837261
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3480855185
Short name T46
Test name
Test status
Simulation time 5623538003 ps
CPU time 76.03 seconds
Started Aug 08 05:12:31 PM PDT 24
Finished Aug 08 05:13:48 PM PDT 24
Peak memory 198740 kb
Host smart-65332242-1559-4cef-9bef-fd042eeb69c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480855185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3480855185
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.557461381
Short name T343
Test name
Test status
Simulation time 14875331 ps
CPU time 0.59 seconds
Started Aug 08 05:12:34 PM PDT 24
Finished Aug 08 05:12:35 PM PDT 24
Peak memory 194468 kb
Host smart-6e32e199-535a-46c0-b251-48884633f406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557461381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.557461381
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.476014441
Short name T631
Test name
Test status
Simulation time 102294659 ps
CPU time 0.73 seconds
Started Aug 08 05:12:26 PM PDT 24
Finished Aug 08 05:12:27 PM PDT 24
Peak memory 194836 kb
Host smart-46e21de0-69ee-4d66-acd1-dbe5405af621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476014441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.476014441
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3684204940
Short name T652
Test name
Test status
Simulation time 507899753 ps
CPU time 5.34 seconds
Started Aug 08 05:12:27 PM PDT 24
Finished Aug 08 05:12:32 PM PDT 24
Peak memory 196676 kb
Host smart-af75a726-eb98-44fb-8c0f-a2980eb8aeb3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684204940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3684204940
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3684044517
Short name T256
Test name
Test status
Simulation time 133953469 ps
CPU time 0.97 seconds
Started Aug 08 05:12:40 PM PDT 24
Finished Aug 08 05:12:42 PM PDT 24
Peak memory 198296 kb
Host smart-e5b3199c-b0e3-4802-879b-3104b754f4f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684044517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3684044517
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3206256546
Short name T603
Test name
Test status
Simulation time 572888120 ps
CPU time 1.5 seconds
Started Aug 08 05:12:34 PM PDT 24
Finished Aug 08 05:12:36 PM PDT 24
Peak memory 197624 kb
Host smart-49adac8d-fa62-4da0-b6ef-0badb77d8ed8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206256546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3206256546
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2949272889
Short name T656
Test name
Test status
Simulation time 141068092 ps
CPU time 2.52 seconds
Started Aug 08 05:12:34 PM PDT 24
Finished Aug 08 05:12:37 PM PDT 24
Peak memory 196952 kb
Host smart-1b1c5546-1597-4b77-88b0-d6b9c5268bbe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949272889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2949272889
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.450686904
Short name T315
Test name
Test status
Simulation time 1101968865 ps
CPU time 1.48 seconds
Started Aug 08 05:12:35 PM PDT 24
Finished Aug 08 05:12:37 PM PDT 24
Peak memory 196984 kb
Host smart-99ef771e-b9a0-4b93-b758-6ea3557af9d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450686904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
450686904
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.3014840878
Short name T442
Test name
Test status
Simulation time 24002884 ps
CPU time 0.77 seconds
Started Aug 08 05:12:33 PM PDT 24
Finished Aug 08 05:12:35 PM PDT 24
Peak memory 196620 kb
Host smart-fc493cf0-1cac-4cc9-9a9c-56968c1173f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014840878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3014840878
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3856804966
Short name T339
Test name
Test status
Simulation time 39946514 ps
CPU time 0.92 seconds
Started Aug 08 05:12:47 PM PDT 24
Finished Aug 08 05:12:49 PM PDT 24
Peak memory 197180 kb
Host smart-9fe2665c-288f-48ee-a2c1-54bd23347194
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856804966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3856804966
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.713795381
Short name T4
Test name
Test status
Simulation time 1857568841 ps
CPU time 5.63 seconds
Started Aug 08 05:12:32 PM PDT 24
Finished Aug 08 05:12:38 PM PDT 24
Peak memory 198504 kb
Host smart-6baeab0a-e67b-4ccd-801b-30a272def894
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713795381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran
dom_long_reg_writes_reg_reads.713795381
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3133901517
Short name T319
Test name
Test status
Simulation time 433934900 ps
CPU time 1.3 seconds
Started Aug 08 05:12:37 PM PDT 24
Finished Aug 08 05:12:38 PM PDT 24
Peak memory 196012 kb
Host smart-a3467756-9b55-4179-ba56-f4feca3aaca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133901517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3133901517
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2900881979
Short name T519
Test name
Test status
Simulation time 113323210 ps
CPU time 0.82 seconds
Started Aug 08 05:12:33 PM PDT 24
Finished Aug 08 05:12:34 PM PDT 24
Peak memory 195836 kb
Host smart-ad23ce2e-3013-4242-8a4f-fc0ce7ed1046
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900881979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2900881979
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2705050673
Short name T564
Test name
Test status
Simulation time 4432033072 ps
CPU time 117.34 seconds
Started Aug 08 05:12:38 PM PDT 24
Finished Aug 08 05:14:35 PM PDT 24
Peak memory 198656 kb
Host smart-70ce8ca8-fb08-48a4-9a98-da7e7a5cd299
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705050673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2705050673
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3282714763
Short name T494
Test name
Test status
Simulation time 35611560 ps
CPU time 0.58 seconds
Started Aug 08 05:12:43 PM PDT 24
Finished Aug 08 05:12:43 PM PDT 24
Peak memory 194392 kb
Host smart-3628dc48-e5e4-4997-8daf-6107e7cbfc77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282714763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3282714763
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.4293187446
Short name T621
Test name
Test status
Simulation time 114600643 ps
CPU time 0.78 seconds
Started Aug 08 05:12:40 PM PDT 24
Finished Aug 08 05:12:41 PM PDT 24
Peak memory 195840 kb
Host smart-fbd40abe-d76b-4d3c-b88d-a74ba41e90d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293187446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.4293187446
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3084466083
Short name T325
Test name
Test status
Simulation time 3071508182 ps
CPU time 22.5 seconds
Started Aug 08 05:12:28 PM PDT 24
Finished Aug 08 05:12:51 PM PDT 24
Peak memory 198624 kb
Host smart-da85cb39-7992-450f-8042-57afb3228d4e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084466083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3084466083
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.4142113338
Short name T541
Test name
Test status
Simulation time 137255958 ps
CPU time 0.92 seconds
Started Aug 08 05:12:33 PM PDT 24
Finished Aug 08 05:12:34 PM PDT 24
Peak memory 197528 kb
Host smart-74a827ba-bdb8-4a9e-b287-36fdbb52912b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142113338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.4142113338
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2032380509
Short name T588
Test name
Test status
Simulation time 205110145 ps
CPU time 0.9 seconds
Started Aug 08 05:12:34 PM PDT 24
Finished Aug 08 05:12:35 PM PDT 24
Peak memory 197944 kb
Host smart-fe4538ee-840b-4030-ba24-0cc7f9806f2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032380509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2032380509
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3510107054
Short name T227
Test name
Test status
Simulation time 53663531 ps
CPU time 2.09 seconds
Started Aug 08 05:12:31 PM PDT 24
Finished Aug 08 05:12:33 PM PDT 24
Peak memory 198692 kb
Host smart-72a6181a-3700-4e73-a64b-50f43c51d33e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510107054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3510107054
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3392241948
Short name T576
Test name
Test status
Simulation time 40667899 ps
CPU time 1.31 seconds
Started Aug 08 05:12:34 PM PDT 24
Finished Aug 08 05:12:35 PM PDT 24
Peak memory 196728 kb
Host smart-9d6c4ae4-80b0-4c10-8123-06b056b8e122
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392241948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3392241948
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.201134511
Short name T425
Test name
Test status
Simulation time 95260953 ps
CPU time 1.05 seconds
Started Aug 08 05:12:38 PM PDT 24
Finished Aug 08 05:12:39 PM PDT 24
Peak memory 197164 kb
Host smart-c89c3444-ea63-4e5a-b59b-14a435032340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201134511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.201134511
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1580298361
Short name T163
Test name
Test status
Simulation time 300875366 ps
CPU time 1.23 seconds
Started Aug 08 05:12:36 PM PDT 24
Finished Aug 08 05:12:38 PM PDT 24
Peak memory 197440 kb
Host smart-abeb95e1-749e-4e99-9700-cb7841721e9f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580298361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1580298361
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2581545931
Short name T8
Test name
Test status
Simulation time 1591028040 ps
CPU time 5.46 seconds
Started Aug 08 05:12:34 PM PDT 24
Finished Aug 08 05:12:40 PM PDT 24
Peak memory 198544 kb
Host smart-84985271-aca1-4117-abff-a9f740b0dc51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581545931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2581545931
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.588572766
Short name T402
Test name
Test status
Simulation time 200158629 ps
CPU time 1.08 seconds
Started Aug 08 05:12:29 PM PDT 24
Finished Aug 08 05:12:31 PM PDT 24
Peak memory 196844 kb
Host smart-fe0b19d9-6acc-4d00-84e4-a7a1a895d363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588572766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.588572766
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.4154002699
Short name T512
Test name
Test status
Simulation time 34668456 ps
CPU time 1.04 seconds
Started Aug 08 05:12:48 PM PDT 24
Finished Aug 08 05:12:49 PM PDT 24
Peak memory 196156 kb
Host smart-a90a030d-f1c4-4a44-8603-534dd535318c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154002699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.4154002699
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1454327662
Short name T263
Test name
Test status
Simulation time 12970989735 ps
CPU time 138.82 seconds
Started Aug 08 05:12:36 PM PDT 24
Finished Aug 08 05:14:55 PM PDT 24
Peak memory 198712 kb
Host smart-93eac152-32e4-4ba7-8cd7-97e370808ff3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454327662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1454327662
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2090312679
Short name T310
Test name
Test status
Simulation time 13782416 ps
CPU time 0.58 seconds
Started Aug 08 05:12:32 PM PDT 24
Finished Aug 08 05:12:33 PM PDT 24
Peak memory 194428 kb
Host smart-82bfac33-50cf-41df-9634-1cfc1e71d1c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090312679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2090312679
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1389949334
Short name T407
Test name
Test status
Simulation time 71162971 ps
CPU time 0.87 seconds
Started Aug 08 05:12:33 PM PDT 24
Finished Aug 08 05:12:34 PM PDT 24
Peak memory 197568 kb
Host smart-c925ca01-3307-4611-8228-20a39e18edb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389949334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1389949334
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.681486888
Short name T283
Test name
Test status
Simulation time 468861347 ps
CPU time 22.47 seconds
Started Aug 08 05:12:38 PM PDT 24
Finished Aug 08 05:13:01 PM PDT 24
Peak memory 196048 kb
Host smart-6cbf0c3e-25a8-47aa-b24e-e9a9445527f3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681486888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.681486888
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1391452115
Short name T333
Test name
Test status
Simulation time 90901895 ps
CPU time 1.03 seconds
Started Aug 08 05:12:32 PM PDT 24
Finished Aug 08 05:12:34 PM PDT 24
Peak memory 197468 kb
Host smart-c93b5519-dee5-43db-b13e-baefdc57923a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391452115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1391452115
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2044080470
Short name T424
Test name
Test status
Simulation time 62367324 ps
CPU time 1.16 seconds
Started Aug 08 05:12:37 PM PDT 24
Finished Aug 08 05:12:38 PM PDT 24
Peak memory 196520 kb
Host smart-6126174d-d47b-4b17-9ed1-c4a2e6c56f5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044080470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2044080470
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3650761654
Short name T554
Test name
Test status
Simulation time 395328330 ps
CPU time 3.56 seconds
Started Aug 08 05:12:35 PM PDT 24
Finished Aug 08 05:12:39 PM PDT 24
Peak memory 198656 kb
Host smart-fa9b2a8a-a91c-418b-8dd0-053d8d7befe0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650761654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3650761654
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2556803628
Short name T460
Test name
Test status
Simulation time 86622803 ps
CPU time 0.88 seconds
Started Aug 08 05:12:32 PM PDT 24
Finished Aug 08 05:12:33 PM PDT 24
Peak memory 195972 kb
Host smart-be787edf-cd13-4985-9beb-cb89f8faab84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556803628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2556803628
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2375993655
Short name T660
Test name
Test status
Simulation time 40711816 ps
CPU time 1.1 seconds
Started Aug 08 05:12:29 PM PDT 24
Finished Aug 08 05:12:30 PM PDT 24
Peak memory 196364 kb
Host smart-92ec0d16-dfa8-4855-a3a5-dc0d1af42363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375993655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2375993655
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.2929889296
Short name T694
Test name
Test status
Simulation time 88480713 ps
CPU time 1.25 seconds
Started Aug 08 05:12:42 PM PDT 24
Finished Aug 08 05:12:43 PM PDT 24
Peak memory 198536 kb
Host smart-27100b33-8df1-402c-8d7f-8e8ef0f91ac6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929889296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.2929889296
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2568545135
Short name T443
Test name
Test status
Simulation time 364544161 ps
CPU time 5.74 seconds
Started Aug 08 05:12:35 PM PDT 24
Finished Aug 08 05:12:41 PM PDT 24
Peak memory 198440 kb
Host smart-9d3b301e-4d02-4349-8cc3-7afaaa4bee18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568545135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2568545135
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3846375636
Short name T608
Test name
Test status
Simulation time 31949654 ps
CPU time 0.91 seconds
Started Aug 08 05:12:37 PM PDT 24
Finished Aug 08 05:12:38 PM PDT 24
Peak memory 195760 kb
Host smart-b4f4ea2d-afbf-4b72-845d-9f3aca695ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846375636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3846375636
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.4210230253
Short name T145
Test name
Test status
Simulation time 262054030 ps
CPU time 1.1 seconds
Started Aug 08 05:12:32 PM PDT 24
Finished Aug 08 05:12:33 PM PDT 24
Peak memory 196204 kb
Host smart-2ed77728-b85c-4b16-b3e7-ac5b441d2da5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210230253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.4210230253
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2799587271
Short name T708
Test name
Test status
Simulation time 37419825084 ps
CPU time 94.09 seconds
Started Aug 08 05:12:34 PM PDT 24
Finished Aug 08 05:14:08 PM PDT 24
Peak memory 198740 kb
Host smart-afc8c366-2a42-479f-8f88-2ce9cb1bda5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799587271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2799587271
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.4052430420
Short name T711
Test name
Test status
Simulation time 98287822 ps
CPU time 0.7 seconds
Started Aug 08 05:12:34 PM PDT 24
Finished Aug 08 05:12:35 PM PDT 24
Peak memory 195244 kb
Host smart-aaf9e01e-38d9-4786-9a42-3441bbd9d8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052430420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.4052430420
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3723575917
Short name T632
Test name
Test status
Simulation time 2336739425 ps
CPU time 15.9 seconds
Started Aug 08 05:12:35 PM PDT 24
Finished Aug 08 05:12:51 PM PDT 24
Peak memory 196232 kb
Host smart-8f0c3414-3d46-4c86-984f-791b89d203b3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723575917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3723575917
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3129272096
Short name T357
Test name
Test status
Simulation time 21727580 ps
CPU time 0.65 seconds
Started Aug 08 05:12:46 PM PDT 24
Finished Aug 08 05:12:47 PM PDT 24
Peak memory 195012 kb
Host smart-d265fecb-7163-42a6-b724-0eacb83fa2ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129272096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3129272096
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2195794498
Short name T192
Test name
Test status
Simulation time 42797853 ps
CPU time 0.71 seconds
Started Aug 08 05:12:36 PM PDT 24
Finished Aug 08 05:12:37 PM PDT 24
Peak memory 195756 kb
Host smart-c82a67a0-a99c-4452-914b-0a32bdaa0f1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195794498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2195794498
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.4088782353
Short name T161
Test name
Test status
Simulation time 65569811 ps
CPU time 2.64 seconds
Started Aug 08 05:12:30 PM PDT 24
Finished Aug 08 05:12:33 PM PDT 24
Peak memory 197780 kb
Host smart-e1b074c4-a28f-4a05-98f7-a6b15ab84bfb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088782353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.4088782353
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2566846247
Short name T567
Test name
Test status
Simulation time 73642302 ps
CPU time 2.17 seconds
Started Aug 08 05:12:51 PM PDT 24
Finished Aug 08 05:12:53 PM PDT 24
Peak memory 197528 kb
Host smart-0c0afc1a-9c79-4891-9e08-299236dd1a42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566846247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2566846247
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2703881895
Short name T454
Test name
Test status
Simulation time 45676593 ps
CPU time 0.72 seconds
Started Aug 08 05:12:36 PM PDT 24
Finished Aug 08 05:12:37 PM PDT 24
Peak memory 195800 kb
Host smart-fe8202e3-4ea9-4bb3-9d17-5987e74c73be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703881895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2703881895
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3305807036
Short name T476
Test name
Test status
Simulation time 38929324 ps
CPU time 0.62 seconds
Started Aug 08 05:12:34 PM PDT 24
Finished Aug 08 05:12:35 PM PDT 24
Peak memory 194644 kb
Host smart-6c52e5d0-3128-4519-88fd-c466eff20177
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305807036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3305807036
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1326149980
Short name T490
Test name
Test status
Simulation time 434758520 ps
CPU time 5.15 seconds
Started Aug 08 05:12:47 PM PDT 24
Finished Aug 08 05:12:52 PM PDT 24
Peak memory 198508 kb
Host smart-58accfed-9481-4a53-bb8d-7a571e33b2d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326149980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1326149980
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3727955152
Short name T715
Test name
Test status
Simulation time 55154592 ps
CPU time 1.06 seconds
Started Aug 08 05:12:45 PM PDT 24
Finished Aug 08 05:12:47 PM PDT 24
Peak memory 196824 kb
Host smart-10f81e7a-d211-48c0-99e6-6bddef999f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727955152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3727955152
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.4032095135
Short name T427
Test name
Test status
Simulation time 56232266 ps
CPU time 0.95 seconds
Started Aug 08 05:12:36 PM PDT 24
Finished Aug 08 05:12:37 PM PDT 24
Peak memory 196984 kb
Host smart-3848b0d1-4681-483b-85ae-c9ac45807b90
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032095135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.4032095135
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2022206656
Short name T239
Test name
Test status
Simulation time 13658619220 ps
CPU time 97.92 seconds
Started Aug 08 05:12:57 PM PDT 24
Finished Aug 08 05:14:35 PM PDT 24
Peak memory 198668 kb
Host smart-f62a8496-552c-4c99-bb71-b9cf605b4494
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022206656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2022206656
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.2649094561
Short name T59
Test name
Test status
Simulation time 100290000608 ps
CPU time 664.31 seconds
Started Aug 08 05:12:33 PM PDT 24
Finished Aug 08 05:23:38 PM PDT 24
Peak memory 206948 kb
Host smart-8c0bceb6-3053-493e-988e-645c7bba98b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2649094561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.2649094561
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1517094712
Short name T307
Test name
Test status
Simulation time 13097061 ps
CPU time 0.59 seconds
Started Aug 08 05:12:40 PM PDT 24
Finished Aug 08 05:12:41 PM PDT 24
Peak memory 194396 kb
Host smart-4f60b348-9851-431f-8b5f-4ebc725c09f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517094712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1517094712
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.495681850
Short name T326
Test name
Test status
Simulation time 155353097 ps
CPU time 0.9 seconds
Started Aug 08 05:12:33 PM PDT 24
Finished Aug 08 05:12:34 PM PDT 24
Peak memory 197852 kb
Host smart-ac61ed9a-b460-4c0f-b17c-40f7c3e57095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495681850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.495681850
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2181921630
Short name T445
Test name
Test status
Simulation time 579099381 ps
CPU time 15.95 seconds
Started Aug 08 05:12:45 PM PDT 24
Finished Aug 08 05:13:02 PM PDT 24
Peak memory 197496 kb
Host smart-7845b96d-8bec-4e78-baed-4813f27b9d46
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181921630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2181921630
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.118190804
Short name T522
Test name
Test status
Simulation time 55870709 ps
CPU time 0.74 seconds
Started Aug 08 05:12:32 PM PDT 24
Finished Aug 08 05:12:33 PM PDT 24
Peak memory 196040 kb
Host smart-770d1097-44c3-47e1-8021-2c75b48f8c24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118190804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.118190804
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.4141566224
Short name T658
Test name
Test status
Simulation time 38070233 ps
CPU time 0.88 seconds
Started Aug 08 05:12:58 PM PDT 24
Finished Aug 08 05:12:59 PM PDT 24
Peak memory 195860 kb
Host smart-20b51f03-5ee1-4155-be39-894e3c4502c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141566224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.4141566224
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.164916812
Short name T112
Test name
Test status
Simulation time 64287975 ps
CPU time 1.36 seconds
Started Aug 08 05:12:46 PM PDT 24
Finished Aug 08 05:12:48 PM PDT 24
Peak memory 197224 kb
Host smart-59c4ed50-3b21-4065-a622-cdfe78f456e3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164916812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.164916812
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.2769938559
Short name T115
Test name
Test status
Simulation time 109615391 ps
CPU time 3.29 seconds
Started Aug 08 05:12:47 PM PDT 24
Finished Aug 08 05:12:55 PM PDT 24
Peak memory 197632 kb
Host smart-462b798d-3860-4a2e-89c4-3515d20ff618
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769938559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.2769938559
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.385233774
Short name T637
Test name
Test status
Simulation time 45934561 ps
CPU time 0.97 seconds
Started Aug 08 05:12:34 PM PDT 24
Finished Aug 08 05:12:35 PM PDT 24
Peak memory 197240 kb
Host smart-cbd40d07-11d7-41c3-8224-4bdea57aa298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385233774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.385233774
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.4239164204
Short name T358
Test name
Test status
Simulation time 138767668 ps
CPU time 0.95 seconds
Started Aug 08 05:12:43 PM PDT 24
Finished Aug 08 05:12:44 PM PDT 24
Peak memory 197088 kb
Host smart-5e7d3a6d-7dde-4078-9609-2d7094f4e530
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239164204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.4239164204
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3659486758
Short name T473
Test name
Test status
Simulation time 1274184333 ps
CPU time 5.31 seconds
Started Aug 08 05:13:06 PM PDT 24
Finished Aug 08 05:13:11 PM PDT 24
Peak memory 198540 kb
Host smart-71717471-b47c-44d4-8ce1-b45f958683db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659486758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3659486758
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2535754531
Short name T321
Test name
Test status
Simulation time 155558364 ps
CPU time 0.97 seconds
Started Aug 08 05:13:06 PM PDT 24
Finished Aug 08 05:13:07 PM PDT 24
Peak memory 196356 kb
Host smart-667d4072-fa16-4420-ae07-37450cdfdd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535754531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2535754531
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3579863124
Short name T545
Test name
Test status
Simulation time 354746035 ps
CPU time 0.87 seconds
Started Aug 08 05:12:45 PM PDT 24
Finished Aug 08 05:12:46 PM PDT 24
Peak memory 196540 kb
Host smart-e1955672-1024-4335-aef6-823ef259bd86
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579863124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3579863124
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2519748813
Short name T149
Test name
Test status
Simulation time 16265869747 ps
CPU time 194.07 seconds
Started Aug 08 05:12:55 PM PDT 24
Finished Aug 08 05:16:10 PM PDT 24
Peak memory 198780 kb
Host smart-4c7efc35-d341-4c02-b495-215316115ef9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519748813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2519748813
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.1278017406
Short name T525
Test name
Test status
Simulation time 8273020571 ps
CPU time 227.24 seconds
Started Aug 08 05:12:45 PM PDT 24
Finished Aug 08 05:16:33 PM PDT 24
Peak memory 198812 kb
Host smart-6261527e-4d24-4c49-bd73-44feb1e48ff5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1278017406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.1278017406
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3983905414
Short name T216
Test name
Test status
Simulation time 21613264 ps
CPU time 0.57 seconds
Started Aug 08 05:12:37 PM PDT 24
Finished Aug 08 05:12:38 PM PDT 24
Peak memory 195080 kb
Host smart-7701e09f-956d-49b4-8786-7c85c2a8b008
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983905414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3983905414
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2021419992
Short name T392
Test name
Test status
Simulation time 47617251 ps
CPU time 0.84 seconds
Started Aug 08 05:12:40 PM PDT 24
Finished Aug 08 05:12:41 PM PDT 24
Peak memory 196864 kb
Host smart-b4e6b829-72b9-4154-9973-b472d3e96f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021419992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2021419992
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2532288861
Short name T278
Test name
Test status
Simulation time 681993718 ps
CPU time 17.39 seconds
Started Aug 08 05:12:41 PM PDT 24
Finished Aug 08 05:12:58 PM PDT 24
Peak memory 198588 kb
Host smart-313bedaf-00ec-4e0a-9ca4-4170dce24930
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532288861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2532288861
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1685153104
Short name T520
Test name
Test status
Simulation time 89110344 ps
CPU time 0.97 seconds
Started Aug 08 05:12:42 PM PDT 24
Finished Aug 08 05:12:43 PM PDT 24
Peak memory 197516 kb
Host smart-1d01037b-6b8b-433a-b820-b5fd87c58d54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685153104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1685153104
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1622560445
Short name T682
Test name
Test status
Simulation time 529997578 ps
CPU time 1.3 seconds
Started Aug 08 05:12:40 PM PDT 24
Finished Aug 08 05:12:42 PM PDT 24
Peak memory 196352 kb
Host smart-e3aa6432-c01f-4061-a3f6-c9aae0b91891
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622560445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1622560445
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2502515773
Short name T625
Test name
Test status
Simulation time 187635410 ps
CPU time 3.62 seconds
Started Aug 08 05:12:40 PM PDT 24
Finished Aug 08 05:12:44 PM PDT 24
Peak memory 197068 kb
Host smart-96e2b699-0d54-4499-95a5-278e0e5bb6cb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502515773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2502515773
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.4039962372
Short name T594
Test name
Test status
Simulation time 463282832 ps
CPU time 1.47 seconds
Started Aug 08 05:12:40 PM PDT 24
Finished Aug 08 05:12:42 PM PDT 24
Peak memory 197336 kb
Host smart-e7fb1d83-7e18-438c-b207-aa944ba37785
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039962372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.4039962372
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.538426633
Short name T573
Test name
Test status
Simulation time 390378259 ps
CPU time 1.13 seconds
Started Aug 08 05:12:47 PM PDT 24
Finished Aug 08 05:12:48 PM PDT 24
Peak memory 196508 kb
Host smart-89c9b773-c863-48d6-a182-9db4b388281b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538426633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.538426633
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2751530674
Short name T180
Test name
Test status
Simulation time 30874004 ps
CPU time 0.85 seconds
Started Aug 08 05:12:39 PM PDT 24
Finished Aug 08 05:12:41 PM PDT 24
Peak memory 196992 kb
Host smart-beac5d35-f3cd-460f-a45f-4d6764de4cff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751530674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2751530674
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3429271983
Short name T378
Test name
Test status
Simulation time 91670783 ps
CPU time 1.83 seconds
Started Aug 08 05:12:44 PM PDT 24
Finished Aug 08 05:12:47 PM PDT 24
Peak memory 198516 kb
Host smart-e489d56b-6a1b-41a3-8f3e-ecfbd811581e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429271983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3429271983
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3984859236
Short name T153
Test name
Test status
Simulation time 84145268 ps
CPU time 1.32 seconds
Started Aug 08 05:12:34 PM PDT 24
Finished Aug 08 05:12:46 PM PDT 24
Peak memory 197356 kb
Host smart-a459223e-8a7b-4924-884d-079d902b991a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984859236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3984859236
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.4182354317
Short name T361
Test name
Test status
Simulation time 420296923 ps
CPU time 1.44 seconds
Started Aug 08 05:12:49 PM PDT 24
Finished Aug 08 05:12:51 PM PDT 24
Peak memory 196032 kb
Host smart-6d03e2cf-fd70-4609-bd2c-fe6af83d62e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182354317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.4182354317
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.852239929
Short name T630
Test name
Test status
Simulation time 6001902422 ps
CPU time 78.74 seconds
Started Aug 08 05:12:36 PM PDT 24
Finished Aug 08 05:13:55 PM PDT 24
Peak memory 198656 kb
Host smart-ca4e7e64-9d6c-43a4-80f2-4958cd986feb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852239929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.852239929
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.2059885201
Short name T56
Test name
Test status
Simulation time 56992721395 ps
CPU time 1154.23 seconds
Started Aug 08 05:12:38 PM PDT 24
Finished Aug 08 05:31:53 PM PDT 24
Peak memory 198900 kb
Host smart-3a13c56a-34c2-498f-b1f0-8e28a5ed87ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2059885201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.2059885201
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1559028341
Short name T557
Test name
Test status
Simulation time 11261852 ps
CPU time 0.55 seconds
Started Aug 08 05:12:44 PM PDT 24
Finished Aug 08 05:12:45 PM PDT 24
Peak memory 195032 kb
Host smart-8139a502-7049-4e52-aaa9-ef823d733d30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559028341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1559028341
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.792922550
Short name T431
Test name
Test status
Simulation time 44392915 ps
CPU time 0.79 seconds
Started Aug 08 05:12:47 PM PDT 24
Finished Aug 08 05:12:48 PM PDT 24
Peak memory 195740 kb
Host smart-a796e31d-427d-4685-ad60-3e9f5e78dad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792922550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.792922550
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.26044986
Short name T117
Test name
Test status
Simulation time 1496034899 ps
CPU time 16.88 seconds
Started Aug 08 05:12:51 PM PDT 24
Finished Aug 08 05:13:08 PM PDT 24
Peak memory 198420 kb
Host smart-528a60f5-54f5-423a-8688-f65cb7207432
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26044986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stress
.26044986
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.4062757056
Short name T536
Test name
Test status
Simulation time 119617281 ps
CPU time 0.74 seconds
Started Aug 08 05:13:01 PM PDT 24
Finished Aug 08 05:13:02 PM PDT 24
Peak memory 195496 kb
Host smart-120186fe-a0c5-4798-92c1-dba1b1277333
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062757056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.4062757056
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1176627857
Short name T364
Test name
Test status
Simulation time 55809885 ps
CPU time 0.66 seconds
Started Aug 08 05:12:41 PM PDT 24
Finished Aug 08 05:12:42 PM PDT 24
Peak memory 194772 kb
Host smart-7d8fcc8d-2e9c-4291-b27a-c58ac2aaf7f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176627857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1176627857
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3307345949
Short name T267
Test name
Test status
Simulation time 129342273 ps
CPU time 2.8 seconds
Started Aug 08 05:12:45 PM PDT 24
Finished Aug 08 05:12:48 PM PDT 24
Peak memory 198588 kb
Host smart-448a4fda-c33f-4906-be24-d87de37c70b2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307345949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3307345949
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1538201026
Short name T437
Test name
Test status
Simulation time 316057082 ps
CPU time 2.39 seconds
Started Aug 08 05:12:39 PM PDT 24
Finished Aug 08 05:12:42 PM PDT 24
Peak memory 197708 kb
Host smart-90f0c560-7cf6-4310-aaa4-3d855ccf9b57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538201026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1538201026
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.2211253952
Short name T416
Test name
Test status
Simulation time 215007921 ps
CPU time 1.31 seconds
Started Aug 08 05:12:47 PM PDT 24
Finished Aug 08 05:12:49 PM PDT 24
Peak memory 198444 kb
Host smart-72a0ce6d-bfe0-4c6c-a5b6-3a8cc43d9abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211253952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.2211253952
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3935307782
Short name T665
Test name
Test status
Simulation time 23194706 ps
CPU time 0.71 seconds
Started Aug 08 05:12:44 PM PDT 24
Finished Aug 08 05:12:45 PM PDT 24
Peak memory 195784 kb
Host smart-963f3bf8-5697-4c39-81c2-6016378814ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935307782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3935307782
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.39120712
Short name T10
Test name
Test status
Simulation time 446412125 ps
CPU time 2.95 seconds
Started Aug 08 05:12:40 PM PDT 24
Finished Aug 08 05:12:43 PM PDT 24
Peak memory 198404 kb
Host smart-27eeab1f-910e-4d27-a14c-404591b68d70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39120712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand
om_long_reg_writes_reg_reads.39120712
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.4159483237
Short name T681
Test name
Test status
Simulation time 80231564 ps
CPU time 1.23 seconds
Started Aug 08 05:13:12 PM PDT 24
Finished Aug 08 05:13:14 PM PDT 24
Peak memory 197608 kb
Host smart-e61f2184-3c0f-4b0c-b4a3-53fe3be6e644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159483237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.4159483237
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2077930000
Short name T211
Test name
Test status
Simulation time 66436575 ps
CPU time 1.26 seconds
Started Aug 08 05:12:44 PM PDT 24
Finished Aug 08 05:12:46 PM PDT 24
Peak memory 196180 kb
Host smart-116de2a5-f46c-4729-821f-16965a253232
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077930000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2077930000
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.4287758831
Short name T5
Test name
Test status
Simulation time 9581603669 ps
CPU time 105.39 seconds
Started Aug 08 05:12:44 PM PDT 24
Finished Aug 08 05:14:30 PM PDT 24
Peak memory 198736 kb
Host smart-86d88c82-aac8-4439-b12b-77ca0d676646
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287758831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.4287758831
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.3140993309
Short name T58
Test name
Test status
Simulation time 66591782639 ps
CPU time 303.12 seconds
Started Aug 08 05:12:40 PM PDT 24
Finished Aug 08 05:17:43 PM PDT 24
Peak memory 198824 kb
Host smart-629d5031-76a8-4d9d-a10e-542b5238a7c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3140993309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.3140993309
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3613350912
Short name T369
Test name
Test status
Simulation time 10730348 ps
CPU time 0.61 seconds
Started Aug 08 05:12:13 PM PDT 24
Finished Aug 08 05:12:14 PM PDT 24
Peak memory 194360 kb
Host smart-bb671940-8702-4e62-be51-d7ec9c05f807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613350912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3613350912
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.945214046
Short name T667
Test name
Test status
Simulation time 25954253 ps
CPU time 0.88 seconds
Started Aug 08 05:12:19 PM PDT 24
Finished Aug 08 05:12:20 PM PDT 24
Peak memory 196860 kb
Host smart-f732c4eb-12ca-4564-84ea-76f286d55edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945214046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.945214046
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2974075040
Short name T530
Test name
Test status
Simulation time 76874352 ps
CPU time 3.54 seconds
Started Aug 08 05:12:19 PM PDT 24
Finished Aug 08 05:12:22 PM PDT 24
Peak memory 197248 kb
Host smart-45343197-2863-466d-b32f-f400b5176c9c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974075040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2974075040
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2016720544
Short name T376
Test name
Test status
Simulation time 261897300 ps
CPU time 0.97 seconds
Started Aug 08 05:12:20 PM PDT 24
Finished Aug 08 05:12:21 PM PDT 24
Peak memory 197128 kb
Host smart-f95aa116-63b3-4220-9bf3-c2bd72cb2e40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016720544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2016720544
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2643746822
Short name T146
Test name
Test status
Simulation time 324734629 ps
CPU time 1.09 seconds
Started Aug 08 05:12:29 PM PDT 24
Finished Aug 08 05:12:31 PM PDT 24
Peak memory 196588 kb
Host smart-dac40c76-19c3-43d8-83cc-6007940ccee9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643746822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2643746822
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3131262688
Short name T286
Test name
Test status
Simulation time 173804198 ps
CPU time 3.25 seconds
Started Aug 08 05:12:20 PM PDT 24
Finished Aug 08 05:12:23 PM PDT 24
Peak memory 198632 kb
Host smart-08e694e2-4bd6-45ea-9ef5-79eb74cc8766
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131262688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3131262688
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3062109572
Short name T252
Test name
Test status
Simulation time 216626557 ps
CPU time 2.35 seconds
Started Aug 08 05:12:18 PM PDT 24
Finished Aug 08 05:12:20 PM PDT 24
Peak memory 198536 kb
Host smart-66aac56e-3456-4d32-a3ca-65f887b8d0e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062109572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3062109572
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3802602322
Short name T483
Test name
Test status
Simulation time 143694941 ps
CPU time 0.84 seconds
Started Aug 08 05:12:19 PM PDT 24
Finished Aug 08 05:12:20 PM PDT 24
Peak memory 197128 kb
Host smart-3b2244bf-8a56-4b2a-8edb-c98993b62aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802602322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3802602322
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2673754911
Short name T191
Test name
Test status
Simulation time 47151636 ps
CPU time 1.03 seconds
Started Aug 08 05:12:10 PM PDT 24
Finished Aug 08 05:12:11 PM PDT 24
Peak memory 197272 kb
Host smart-1f31b9c7-1d18-4bd5-89ec-176983e4a984
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673754911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2673754911
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.318520079
Short name T452
Test name
Test status
Simulation time 161017276 ps
CPU time 2.05 seconds
Started Aug 08 05:12:11 PM PDT 24
Finished Aug 08 05:12:13 PM PDT 24
Peak memory 198536 kb
Host smart-0cb9df82-7ecb-4e37-945a-13b172f07fd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318520079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.318520079
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1816244532
Short name T30
Test name
Test status
Simulation time 79297472 ps
CPU time 0.9 seconds
Started Aug 08 05:12:18 PM PDT 24
Finished Aug 08 05:12:19 PM PDT 24
Peak memory 214272 kb
Host smart-50a711c8-2d80-4eba-9e12-f79336d71e0e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816244532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1816244532
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3702842928
Short name T633
Test name
Test status
Simulation time 82158416 ps
CPU time 0.9 seconds
Started Aug 08 05:12:20 PM PDT 24
Finished Aug 08 05:12:21 PM PDT 24
Peak memory 196748 kb
Host smart-a00aa19b-fab3-4113-95d9-34b3dbeebe49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702842928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3702842928
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2679584249
Short name T495
Test name
Test status
Simulation time 34450705 ps
CPU time 1.12 seconds
Started Aug 08 05:12:16 PM PDT 24
Finished Aug 08 05:12:18 PM PDT 24
Peak memory 196148 kb
Host smart-d2db79ab-7f4b-410b-8816-543e6b055be4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679584249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2679584249
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3708383500
Short name T529
Test name
Test status
Simulation time 10838286014 ps
CPU time 75.17 seconds
Started Aug 08 05:12:13 PM PDT 24
Finished Aug 08 05:13:28 PM PDT 24
Peak memory 198708 kb
Host smart-5b7b55d9-0cf7-4bba-80ae-2952960bcd2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708383500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3708383500
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.3310264690
Short name T690
Test name
Test status
Simulation time 65526994 ps
CPU time 0.56 seconds
Started Aug 08 05:12:34 PM PDT 24
Finished Aug 08 05:12:35 PM PDT 24
Peak memory 195224 kb
Host smart-2f76282c-5bb9-4bb1-8b1a-eb6704eb8408
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310264690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.3310264690
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.341460465
Short name T162
Test name
Test status
Simulation time 187533274 ps
CPU time 0.91 seconds
Started Aug 08 05:12:40 PM PDT 24
Finished Aug 08 05:12:41 PM PDT 24
Peak memory 196856 kb
Host smart-4ed981ba-52a5-462b-bd3b-bc3d124b669a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341460465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.341460465
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1616328527
Short name T269
Test name
Test status
Simulation time 2015807706 ps
CPU time 15.94 seconds
Started Aug 08 05:12:34 PM PDT 24
Finished Aug 08 05:12:50 PM PDT 24
Peak memory 195976 kb
Host smart-486e1782-9045-4856-9acf-95b015064eb2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616328527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1616328527
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1492427082
Short name T69
Test name
Test status
Simulation time 44337909 ps
CPU time 0.8 seconds
Started Aug 08 05:12:46 PM PDT 24
Finished Aug 08 05:12:47 PM PDT 24
Peak memory 196272 kb
Host smart-57c78af7-c769-4850-af16-e606e0306f95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492427082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1492427082
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2367314934
Short name T229
Test name
Test status
Simulation time 146582573 ps
CPU time 1.19 seconds
Started Aug 08 05:12:53 PM PDT 24
Finished Aug 08 05:12:54 PM PDT 24
Peak memory 196656 kb
Host smart-544504f0-08c4-4634-9da8-826725976254
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367314934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2367314934
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.81151241
Short name T265
Test name
Test status
Simulation time 58448468 ps
CPU time 1.27 seconds
Started Aug 08 05:12:48 PM PDT 24
Finished Aug 08 05:12:49 PM PDT 24
Peak memory 196780 kb
Host smart-fe7d6c2d-0508-4872-8843-1f588d32ef94
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81151241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.gpio_intr_with_filter_rand_intr_event.81151241
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.658372946
Short name T508
Test name
Test status
Simulation time 87792667 ps
CPU time 1.99 seconds
Started Aug 08 05:12:38 PM PDT 24
Finished Aug 08 05:12:40 PM PDT 24
Peak memory 197344 kb
Host smart-35d3582e-701c-473f-baac-256905cf614f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658372946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.
658372946
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1519098703
Short name T152
Test name
Test status
Simulation time 35347087 ps
CPU time 0.66 seconds
Started Aug 08 05:12:53 PM PDT 24
Finished Aug 08 05:12:53 PM PDT 24
Peak memory 194724 kb
Host smart-1a646d94-7460-4b33-acd3-7cf80743e244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519098703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1519098703
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.4222227360
Short name T179
Test name
Test status
Simulation time 24470304 ps
CPU time 1.04 seconds
Started Aug 08 05:12:39 PM PDT 24
Finished Aug 08 05:12:41 PM PDT 24
Peak memory 196580 kb
Host smart-2ca17894-0149-494f-be0f-7f0c7cda0843
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222227360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.4222227360
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2764551688
Short name T242
Test name
Test status
Simulation time 451023639 ps
CPU time 5.43 seconds
Started Aug 08 05:12:42 PM PDT 24
Finished Aug 08 05:12:48 PM PDT 24
Peak memory 198468 kb
Host smart-e9179a28-d5c0-4b38-9f78-a091269a3bc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764551688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2764551688
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2900734066
Short name T275
Test name
Test status
Simulation time 197711775 ps
CPU time 1.1 seconds
Started Aug 08 05:12:45 PM PDT 24
Finished Aug 08 05:12:46 PM PDT 24
Peak memory 196204 kb
Host smart-43e6de1c-b447-4a23-9e64-357a3e593cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900734066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2900734066
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.619650706
Short name T371
Test name
Test status
Simulation time 168449377 ps
CPU time 0.97 seconds
Started Aug 08 05:12:48 PM PDT 24
Finished Aug 08 05:12:49 PM PDT 24
Peak memory 196388 kb
Host smart-ab92c104-95c4-4250-a270-4f519c1ae3dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619650706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.619650706
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.3349346389
Short name T342
Test name
Test status
Simulation time 25357208548 ps
CPU time 79.86 seconds
Started Aug 08 05:12:41 PM PDT 24
Finished Aug 08 05:14:01 PM PDT 24
Peak memory 198752 kb
Host smart-0ba17faf-e8c8-4b55-a6cb-2fbc34ba816e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349346389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3349346389
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1368803320
Short name T261
Test name
Test status
Simulation time 11568527 ps
CPU time 0.56 seconds
Started Aug 08 05:12:45 PM PDT 24
Finished Aug 08 05:12:46 PM PDT 24
Peak memory 194456 kb
Host smart-119b2237-15e9-459c-8af3-fe6ebaef95d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368803320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1368803320
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1628772112
Short name T63
Test name
Test status
Simulation time 64379108 ps
CPU time 0.68 seconds
Started Aug 08 05:12:57 PM PDT 24
Finished Aug 08 05:12:58 PM PDT 24
Peak memory 194472 kb
Host smart-06658c0f-8f4a-4385-a68d-33f70c7bde01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628772112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1628772112
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2940102954
Short name T258
Test name
Test status
Simulation time 263616445 ps
CPU time 9.22 seconds
Started Aug 08 05:12:49 PM PDT 24
Finished Aug 08 05:12:58 PM PDT 24
Peak memory 197480 kb
Host smart-96dadf3a-7f42-4528-a202-297da4d63c7c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940102954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2940102954
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.3199534410
Short name T168
Test name
Test status
Simulation time 119620403 ps
CPU time 0.66 seconds
Started Aug 08 05:12:39 PM PDT 24
Finished Aug 08 05:12:39 PM PDT 24
Peak memory 195192 kb
Host smart-48dcaeba-d29b-46ff-adba-aab8bf2fc1bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199534410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3199534410
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.865665281
Short name T385
Test name
Test status
Simulation time 49158195 ps
CPU time 0.85 seconds
Started Aug 08 05:12:51 PM PDT 24
Finished Aug 08 05:12:52 PM PDT 24
Peak memory 196988 kb
Host smart-c4aebe54-8465-4fb1-943b-bfb30f548c2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865665281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.865665281
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.333534575
Short name T502
Test name
Test status
Simulation time 99634483 ps
CPU time 1.61 seconds
Started Aug 08 05:12:37 PM PDT 24
Finished Aug 08 05:12:38 PM PDT 24
Peak memory 198664 kb
Host smart-18ac9bf7-2b43-4861-8a82-766cf7d28436
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333534575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.333534575
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1689486593
Short name T53
Test name
Test status
Simulation time 165965640 ps
CPU time 3.63 seconds
Started Aug 08 05:12:47 PM PDT 24
Finished Aug 08 05:12:51 PM PDT 24
Peak memory 198628 kb
Host smart-bff76a10-f749-43a7-8317-876495c662e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689486593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1689486593
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3782915188
Short name T475
Test name
Test status
Simulation time 312708077 ps
CPU time 1.22 seconds
Started Aug 08 05:12:51 PM PDT 24
Finished Aug 08 05:12:52 PM PDT 24
Peak memory 197544 kb
Host smart-2c1577e5-f12d-4f67-8d0b-a592cd7c9828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782915188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3782915188
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.882609809
Short name T330
Test name
Test status
Simulation time 42054895 ps
CPU time 1.03 seconds
Started Aug 08 05:12:39 PM PDT 24
Finished Aug 08 05:12:41 PM PDT 24
Peak memory 196484 kb
Host smart-e1e589f4-19e9-4975-9760-64ab2049f3ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882609809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.882609809
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2782709194
Short name T279
Test name
Test status
Simulation time 203812977 ps
CPU time 2.77 seconds
Started Aug 08 05:12:43 PM PDT 24
Finished Aug 08 05:12:46 PM PDT 24
Peak memory 198808 kb
Host smart-c63ffdc4-73d7-452e-ba2f-09d39e682227
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782709194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2782709194
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1331954362
Short name T171
Test name
Test status
Simulation time 305335501 ps
CPU time 1.37 seconds
Started Aug 08 05:12:45 PM PDT 24
Finished Aug 08 05:12:47 PM PDT 24
Peak memory 196040 kb
Host smart-143b93d9-585c-4e55-a30e-213a4483a46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331954362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1331954362
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1247502156
Short name T139
Test name
Test status
Simulation time 30677364 ps
CPU time 0.8 seconds
Started Aug 08 05:12:42 PM PDT 24
Finished Aug 08 05:12:43 PM PDT 24
Peak memory 195656 kb
Host smart-67451a05-0da6-4ba6-9ca8-47923a2ab4df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247502156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1247502156
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1551704930
Short name T42
Test name
Test status
Simulation time 40399350329 ps
CPU time 145.04 seconds
Started Aug 08 05:12:55 PM PDT 24
Finished Aug 08 05:15:20 PM PDT 24
Peak memory 198652 kb
Host smart-463ee233-d8ef-4cae-a521-13e50cab73a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551704930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1551704930
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.3976389224
Short name T60
Test name
Test status
Simulation time 120172469302 ps
CPU time 821.95 seconds
Started Aug 08 05:12:59 PM PDT 24
Finished Aug 08 05:26:41 PM PDT 24
Peak memory 198820 kb
Host smart-26ce5add-f9e6-4fd2-9fcf-c229203fc176
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3976389224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.3976389224
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.541088938
Short name T548
Test name
Test status
Simulation time 12671463 ps
CPU time 0.59 seconds
Started Aug 08 05:12:51 PM PDT 24
Finished Aug 08 05:12:51 PM PDT 24
Peak memory 194408 kb
Host smart-16d85e08-c8a7-49ac-af26-ab75ad5eb2b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541088938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.541088938
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2306951124
Short name T500
Test name
Test status
Simulation time 74566534 ps
CPU time 0.87 seconds
Started Aug 08 05:12:45 PM PDT 24
Finished Aug 08 05:12:46 PM PDT 24
Peak memory 196912 kb
Host smart-03ec549f-0e02-4b47-97c8-31613b68c565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306951124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2306951124
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3003968965
Short name T617
Test name
Test status
Simulation time 87653241 ps
CPU time 4.55 seconds
Started Aug 08 05:12:53 PM PDT 24
Finished Aug 08 05:12:57 PM PDT 24
Peak memory 196680 kb
Host smart-d1290389-b929-4884-9a06-36dbe4eba445
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003968965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3003968965
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3686400091
Short name T670
Test name
Test status
Simulation time 207021657 ps
CPU time 0.92 seconds
Started Aug 08 05:12:48 PM PDT 24
Finished Aug 08 05:12:49 PM PDT 24
Peak memory 196832 kb
Host smart-bad6db68-2902-4b67-852f-3cd26f90580a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686400091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3686400091
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2171973287
Short name T209
Test name
Test status
Simulation time 1291889013 ps
CPU time 1.22 seconds
Started Aug 08 05:12:39 PM PDT 24
Finished Aug 08 05:12:40 PM PDT 24
Peak memory 196548 kb
Host smart-9ed8cc37-6251-4a85-9dfe-05a66046e94b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171973287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2171973287
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2160852086
Short name T689
Test name
Test status
Simulation time 570927776 ps
CPU time 2.34 seconds
Started Aug 08 05:13:00 PM PDT 24
Finished Aug 08 05:13:03 PM PDT 24
Peak memory 198628 kb
Host smart-6bf7a9d8-b257-4279-95b3-8ab1fdf34770
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160852086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2160852086
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2371582564
Short name T538
Test name
Test status
Simulation time 547010775 ps
CPU time 1.89 seconds
Started Aug 08 05:12:57 PM PDT 24
Finished Aug 08 05:12:59 PM PDT 24
Peak memory 197128 kb
Host smart-b817e40e-1cc8-44f9-982e-eb83ecb26fd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371582564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2371582564
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2496921864
Short name T497
Test name
Test status
Simulation time 22192297 ps
CPU time 0.95 seconds
Started Aug 08 05:13:01 PM PDT 24
Finished Aug 08 05:13:02 PM PDT 24
Peak memory 196476 kb
Host smart-32e00c0d-9c92-4f17-95ac-7a11b1eb4a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496921864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2496921864
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3581683983
Short name T668
Test name
Test status
Simulation time 90067299 ps
CPU time 1.06 seconds
Started Aug 08 05:12:44 PM PDT 24
Finished Aug 08 05:12:45 PM PDT 24
Peak memory 196400 kb
Host smart-f4f5d5c3-f88c-45b5-bf2d-f4b2dd9648e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581683983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3581683983
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1001326009
Short name T172
Test name
Test status
Simulation time 555091100 ps
CPU time 4.38 seconds
Started Aug 08 05:12:50 PM PDT 24
Finished Aug 08 05:12:54 PM PDT 24
Peak memory 198440 kb
Host smart-584e43b2-aa0a-41eb-827c-2a6a1396750b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001326009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1001326009
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1923595123
Short name T200
Test name
Test status
Simulation time 100026100 ps
CPU time 1.45 seconds
Started Aug 08 05:12:45 PM PDT 24
Finished Aug 08 05:12:47 PM PDT 24
Peak memory 198416 kb
Host smart-d2d5674e-6713-445e-9acf-6deced0419cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923595123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1923595123
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3292702070
Short name T374
Test name
Test status
Simulation time 50261746 ps
CPU time 1.03 seconds
Started Aug 08 05:12:47 PM PDT 24
Finished Aug 08 05:12:48 PM PDT 24
Peak memory 196296 kb
Host smart-8cdd7e9b-e7da-4e28-b7c0-7c9d12853ee5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292702070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3292702070
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.1943318070
Short name T222
Test name
Test status
Simulation time 4320980752 ps
CPU time 54.7 seconds
Started Aug 08 05:12:55 PM PDT 24
Finished Aug 08 05:13:50 PM PDT 24
Peak memory 198756 kb
Host smart-1e67ca8d-1d77-41b2-99c4-66782b090d3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943318070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.1943318070
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2720647140
Short name T579
Test name
Test status
Simulation time 24328067 ps
CPU time 0.57 seconds
Started Aug 08 05:12:57 PM PDT 24
Finished Aug 08 05:12:57 PM PDT 24
Peak memory 194416 kb
Host smart-3ec83848-3a37-4a4e-8ffa-52786deeae64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720647140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2720647140
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.874362550
Short name T488
Test name
Test status
Simulation time 52143557 ps
CPU time 0.79 seconds
Started Aug 08 05:12:59 PM PDT 24
Finished Aug 08 05:13:00 PM PDT 24
Peak memory 195816 kb
Host smart-cc880320-f31b-4be0-8ff2-ae2b97acf2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874362550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.874362550
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.3096147817
Short name T647
Test name
Test status
Simulation time 2779462462 ps
CPU time 21.88 seconds
Started Aug 08 05:12:54 PM PDT 24
Finished Aug 08 05:13:16 PM PDT 24
Peak memory 197980 kb
Host smart-db5c1226-756d-4cf9-b6ca-ece5e2b3c8aa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096147817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.3096147817
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1519415471
Short name T645
Test name
Test status
Simulation time 38598522 ps
CPU time 0.75 seconds
Started Aug 08 05:12:44 PM PDT 24
Finished Aug 08 05:12:46 PM PDT 24
Peak memory 195160 kb
Host smart-f05edaaf-f82a-433f-b077-2158e1546847
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519415471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1519415471
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1095794710
Short name T372
Test name
Test status
Simulation time 111269932 ps
CPU time 1.31 seconds
Started Aug 08 05:12:50 PM PDT 24
Finished Aug 08 05:12:52 PM PDT 24
Peak memory 198552 kb
Host smart-b48e583d-da2f-41ec-8647-77bdb13f8e0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095794710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1095794710
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2720592668
Short name T411
Test name
Test status
Simulation time 42877501 ps
CPU time 1.88 seconds
Started Aug 08 05:13:03 PM PDT 24
Finished Aug 08 05:13:05 PM PDT 24
Peak memory 198664 kb
Host smart-714fca0e-65da-4f55-91f7-fccce76151b2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720592668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2720592668
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3629694077
Short name T602
Test name
Test status
Simulation time 78382242 ps
CPU time 2.49 seconds
Started Aug 08 05:12:35 PM PDT 24
Finished Aug 08 05:12:37 PM PDT 24
Peak memory 197036 kb
Host smart-7edaed4f-5754-4187-a134-1dafedf77253
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629694077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3629694077
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1863542713
Short name T693
Test name
Test status
Simulation time 166948963 ps
CPU time 0.97 seconds
Started Aug 08 05:12:35 PM PDT 24
Finished Aug 08 05:12:36 PM PDT 24
Peak memory 197108 kb
Host smart-7e74f854-30e4-4d0f-8968-e87a94195882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863542713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1863542713
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1004295186
Short name T218
Test name
Test status
Simulation time 20748407 ps
CPU time 0.91 seconds
Started Aug 08 05:13:01 PM PDT 24
Finished Aug 08 05:13:03 PM PDT 24
Peak memory 196412 kb
Host smart-0c321220-d042-4b03-8f33-65f05dd0ff49
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004295186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1004295186
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.586063779
Short name T688
Test name
Test status
Simulation time 489705278 ps
CPU time 5.72 seconds
Started Aug 08 05:12:55 PM PDT 24
Finished Aug 08 05:13:01 PM PDT 24
Peak memory 198412 kb
Host smart-d44b4065-4593-48b7-8fe4-8355a0f261a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586063779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ran
dom_long_reg_writes_reg_reads.586063779
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2224276283
Short name T327
Test name
Test status
Simulation time 58665401 ps
CPU time 1.1 seconds
Started Aug 08 05:13:01 PM PDT 24
Finished Aug 08 05:13:03 PM PDT 24
Peak memory 196360 kb
Host smart-c6180a97-5a90-4009-b748-ea67de3a905e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224276283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2224276283
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3741186751
Short name T121
Test name
Test status
Simulation time 67529314 ps
CPU time 1.12 seconds
Started Aug 08 05:12:52 PM PDT 24
Finished Aug 08 05:12:53 PM PDT 24
Peak memory 196980 kb
Host smart-552ecf2b-c4ba-4088-9a84-8948a21f9642
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741186751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3741186751
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3800890613
Short name T185
Test name
Test status
Simulation time 93557211941 ps
CPU time 170.54 seconds
Started Aug 08 05:12:57 PM PDT 24
Finished Aug 08 05:15:47 PM PDT 24
Peak memory 198656 kb
Host smart-340c45ae-3cf6-4ef0-bffe-d9141dfdafb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800890613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3800890613
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1557539648
Short name T511
Test name
Test status
Simulation time 13927704 ps
CPU time 0.57 seconds
Started Aug 08 05:13:00 PM PDT 24
Finished Aug 08 05:13:01 PM PDT 24
Peak memory 195120 kb
Host smart-fbb9208e-d4e1-4590-ba30-c6dab72dd1e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557539648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1557539648
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3431148668
Short name T390
Test name
Test status
Simulation time 17298413 ps
CPU time 0.63 seconds
Started Aug 08 05:13:07 PM PDT 24
Finished Aug 08 05:13:08 PM PDT 24
Peak memory 194708 kb
Host smart-97ba774d-0d52-47a1-aff0-5445ec8d03e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431148668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3431148668
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2471030174
Short name T23
Test name
Test status
Simulation time 1052654782 ps
CPU time 18.42 seconds
Started Aug 08 05:13:05 PM PDT 24
Finished Aug 08 05:13:23 PM PDT 24
Peak memory 197276 kb
Host smart-57ff72a7-1977-44f5-ac42-5830cd4d25d9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471030174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2471030174
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1111284865
Short name T642
Test name
Test status
Simulation time 410391129 ps
CPU time 1.07 seconds
Started Aug 08 05:12:57 PM PDT 24
Finished Aug 08 05:12:58 PM PDT 24
Peak memory 196756 kb
Host smart-aa637e04-767d-4e4a-aa05-287d05b9bc71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111284865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1111284865
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.438083194
Short name T589
Test name
Test status
Simulation time 35946609 ps
CPU time 0.76 seconds
Started Aug 08 05:13:08 PM PDT 24
Finished Aug 08 05:13:09 PM PDT 24
Peak memory 196784 kb
Host smart-040099de-65ae-407c-9350-ebe5dbc53b4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438083194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.438083194
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1540057240
Short name T619
Test name
Test status
Simulation time 91613541 ps
CPU time 1.78 seconds
Started Aug 08 05:13:05 PM PDT 24
Finished Aug 08 05:13:07 PM PDT 24
Peak memory 197040 kb
Host smart-fb6166c7-721b-4869-931b-76f8d5566de2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540057240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1540057240
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3021470671
Short name T166
Test name
Test status
Simulation time 117506979 ps
CPU time 2.57 seconds
Started Aug 08 05:12:58 PM PDT 24
Finished Aug 08 05:13:01 PM PDT 24
Peak memory 197684 kb
Host smart-d87deb65-7ab3-4b25-a047-f182177caa44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021470671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3021470671
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.268297119
Short name T463
Test name
Test status
Simulation time 144177929 ps
CPU time 0.81 seconds
Started Aug 08 05:12:48 PM PDT 24
Finished Aug 08 05:12:54 PM PDT 24
Peak memory 196984 kb
Host smart-52a8d653-c620-4f35-989b-f28941adef10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268297119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.268297119
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3869844586
Short name T662
Test name
Test status
Simulation time 39737706 ps
CPU time 0.94 seconds
Started Aug 08 05:12:52 PM PDT 24
Finished Aug 08 05:12:53 PM PDT 24
Peak memory 197256 kb
Host smart-748fdb76-992d-4bc8-83dd-a50757b13a76
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869844586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3869844586
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2474535208
Short name T414
Test name
Test status
Simulation time 292061653 ps
CPU time 2.91 seconds
Started Aug 08 05:13:01 PM PDT 24
Finished Aug 08 05:13:04 PM PDT 24
Peak memory 198480 kb
Host smart-8d68c0d8-385f-4b6d-9063-264b7280f5fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474535208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2474535208
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2424043857
Short name T462
Test name
Test status
Simulation time 49965942 ps
CPU time 0.91 seconds
Started Aug 08 05:12:48 PM PDT 24
Finished Aug 08 05:12:49 PM PDT 24
Peak memory 196780 kb
Host smart-d6710764-5f85-48c1-9345-f5399e61c059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424043857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2424043857
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2663157130
Short name T148
Test name
Test status
Simulation time 64019041 ps
CPU time 1 seconds
Started Aug 08 05:12:53 PM PDT 24
Finished Aug 08 05:12:55 PM PDT 24
Peak memory 196356 kb
Host smart-419b536b-c12e-4260-89aa-e9c10c96c856
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663157130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2663157130
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.918377053
Short name T300
Test name
Test status
Simulation time 45215240260 ps
CPU time 167.77 seconds
Started Aug 08 05:13:09 PM PDT 24
Finished Aug 08 05:15:57 PM PDT 24
Peak memory 192568 kb
Host smart-2f50b7bb-1627-4c4b-8264-9ba09be64246
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918377053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.918377053
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2588231725
Short name T202
Test name
Test status
Simulation time 13237249 ps
CPU time 0.6 seconds
Started Aug 08 05:13:00 PM PDT 24
Finished Aug 08 05:13:01 PM PDT 24
Peak memory 194468 kb
Host smart-b54705c6-0c19-4d0f-a525-748a93b5a0d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588231725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2588231725
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2619529076
Short name T205
Test name
Test status
Simulation time 181341502 ps
CPU time 0.84 seconds
Started Aug 08 05:12:57 PM PDT 24
Finished Aug 08 05:12:58 PM PDT 24
Peak memory 196872 kb
Host smart-7c3110fb-53cd-4447-b862-db4c01df6b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619529076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2619529076
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.429329683
Short name T147
Test name
Test status
Simulation time 304003652 ps
CPU time 15.11 seconds
Started Aug 08 05:13:11 PM PDT 24
Finished Aug 08 05:13:26 PM PDT 24
Peak memory 197512 kb
Host smart-3c22d9f2-80c7-46c4-a5df-56a50ac547b7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429329683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.429329683
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1022578444
Short name T165
Test name
Test status
Simulation time 44704056 ps
CPU time 0.69 seconds
Started Aug 08 05:13:00 PM PDT 24
Finished Aug 08 05:13:01 PM PDT 24
Peak memory 194844 kb
Host smart-a56fbf99-d99c-47f4-8597-3f1d481ee700
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022578444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1022578444
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.4282202588
Short name T335
Test name
Test status
Simulation time 27408863 ps
CPU time 0.86 seconds
Started Aug 08 05:13:04 PM PDT 24
Finished Aug 08 05:13:05 PM PDT 24
Peak memory 197096 kb
Host smart-4b1b0f82-8198-4a6f-8a10-5d108bbca1bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282202588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.4282202588
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1773067319
Short name T270
Test name
Test status
Simulation time 149128104 ps
CPU time 1.88 seconds
Started Aug 08 05:13:04 PM PDT 24
Finished Aug 08 05:13:06 PM PDT 24
Peak memory 198528 kb
Host smart-76f27206-bfa1-4b5f-abbd-34cc97f7a264
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773067319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1773067319
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.508308256
Short name T169
Test name
Test status
Simulation time 151975703 ps
CPU time 2.38 seconds
Started Aug 08 05:12:56 PM PDT 24
Finished Aug 08 05:12:58 PM PDT 24
Peak memory 197716 kb
Host smart-56190339-eb1e-4748-8218-7b857c24be03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508308256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
508308256
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.338818486
Short name T540
Test name
Test status
Simulation time 658117011 ps
CPU time 1.23 seconds
Started Aug 08 05:13:07 PM PDT 24
Finished Aug 08 05:13:08 PM PDT 24
Peak memory 196440 kb
Host smart-cfe3e78d-5dd4-4fc8-99f5-4fd707bef26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338818486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.338818486
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.4123617868
Short name T544
Test name
Test status
Simulation time 118305960 ps
CPU time 0.83 seconds
Started Aug 08 05:13:05 PM PDT 24
Finished Aug 08 05:13:06 PM PDT 24
Peak memory 197664 kb
Host smart-6e4b7b7a-1ffd-4c99-8dde-5106712f326e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123617868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.4123617868
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2969916043
Short name T129
Test name
Test status
Simulation time 937292518 ps
CPU time 3.21 seconds
Started Aug 08 05:13:07 PM PDT 24
Finished Aug 08 05:13:11 PM PDT 24
Peak memory 198472 kb
Host smart-25b8eaec-ab3d-4ed8-8bf3-d6bcec60d3ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969916043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2969916043
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.218096056
Short name T118
Test name
Test status
Simulation time 55592892 ps
CPU time 0.97 seconds
Started Aug 08 05:12:56 PM PDT 24
Finished Aug 08 05:12:57 PM PDT 24
Peak memory 197700 kb
Host smart-4fd63493-8adf-4657-8867-a611270487fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218096056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.218096056
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.4279785210
Short name T491
Test name
Test status
Simulation time 211649307 ps
CPU time 1.11 seconds
Started Aug 08 05:13:01 PM PDT 24
Finished Aug 08 05:13:02 PM PDT 24
Peak memory 195980 kb
Host smart-46b18219-1bb6-4e0f-9c76-4d46459f519c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279785210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.4279785210
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.649477042
Short name T528
Test name
Test status
Simulation time 37669762769 ps
CPU time 53.36 seconds
Started Aug 08 05:12:53 PM PDT 24
Finished Aug 08 05:13:46 PM PDT 24
Peak memory 198732 kb
Host smart-037d1b70-c88a-4704-9b9d-8a0014f819af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649477042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.649477042
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.3323898760
Short name T614
Test name
Test status
Simulation time 38796039768 ps
CPU time 950.15 seconds
Started Aug 08 05:13:01 PM PDT 24
Finished Aug 08 05:28:51 PM PDT 24
Peak memory 198772 kb
Host smart-6122bdc1-17ca-48ef-89dc-8874dd2b30a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3323898760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.3323898760
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.4044536391
Short name T33
Test name
Test status
Simulation time 61117958 ps
CPU time 0.57 seconds
Started Aug 08 05:13:07 PM PDT 24
Finished Aug 08 05:13:08 PM PDT 24
Peak memory 194428 kb
Host smart-ca6a47a3-ef4a-4d2a-bff7-9ac2967e67de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044536391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.4044536391
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3454383794
Short name T408
Test name
Test status
Simulation time 39157634 ps
CPU time 0.67 seconds
Started Aug 08 05:13:05 PM PDT 24
Finished Aug 08 05:13:06 PM PDT 24
Peak memory 194364 kb
Host smart-c662dc75-f06a-4e1f-8e1d-00734af71013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454383794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3454383794
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1565321150
Short name T365
Test name
Test status
Simulation time 2521792130 ps
CPU time 22.87 seconds
Started Aug 08 05:13:09 PM PDT 24
Finished Aug 08 05:13:32 PM PDT 24
Peak memory 198696 kb
Host smart-645e551f-d8f1-4d8c-8209-fe1267ecf7bd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565321150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1565321150
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2344915632
Short name T313
Test name
Test status
Simulation time 96349549 ps
CPU time 0.69 seconds
Started Aug 08 05:12:57 PM PDT 24
Finished Aug 08 05:12:58 PM PDT 24
Peak memory 194960 kb
Host smart-9f45b4a8-ba22-421f-aa18-16c4fd7ea1bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344915632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2344915632
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2842204889
Short name T309
Test name
Test status
Simulation time 91462869 ps
CPU time 0.7 seconds
Started Aug 08 05:12:53 PM PDT 24
Finished Aug 08 05:12:54 PM PDT 24
Peak memory 194816 kb
Host smart-1dcce8f6-bf67-45a3-92fa-ff702fca3c6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842204889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2842204889
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.925484634
Short name T203
Test name
Test status
Simulation time 450959424 ps
CPU time 2.88 seconds
Started Aug 08 05:13:09 PM PDT 24
Finished Aug 08 05:13:12 PM PDT 24
Peak memory 198552 kb
Host smart-ed2cd01a-e6c9-446a-bd42-70ffd5a8d2fd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925484634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.925484634
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1659763806
Short name T702
Test name
Test status
Simulation time 159831536 ps
CPU time 2.99 seconds
Started Aug 08 05:13:00 PM PDT 24
Finished Aug 08 05:13:03 PM PDT 24
Peak memory 197772 kb
Host smart-13af31bb-1dec-4576-a374-ba3ea6928e45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659763806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1659763806
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1604645345
Short name T543
Test name
Test status
Simulation time 24685548 ps
CPU time 0.73 seconds
Started Aug 08 05:12:59 PM PDT 24
Finished Aug 08 05:13:00 PM PDT 24
Peak memory 195788 kb
Host smart-963bc131-91df-4faa-8cf3-53bd994814ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604645345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1604645345
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.409060877
Short name T493
Test name
Test status
Simulation time 249040312 ps
CPU time 0.92 seconds
Started Aug 08 05:12:53 PM PDT 24
Finished Aug 08 05:12:54 PM PDT 24
Peak memory 196576 kb
Host smart-c144a769-c624-4d39-9c6d-23cb00fdfc37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409060877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.409060877
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.229842163
Short name T555
Test name
Test status
Simulation time 194170509 ps
CPU time 2.25 seconds
Started Aug 08 05:13:04 PM PDT 24
Finished Aug 08 05:13:07 PM PDT 24
Peak memory 198460 kb
Host smart-2b28b421-4e4e-4f59-907e-db6fbcb4e04b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229842163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ran
dom_long_reg_writes_reg_reads.229842163
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.847484521
Short name T352
Test name
Test status
Simulation time 193204918 ps
CPU time 1.15 seconds
Started Aug 08 05:13:14 PM PDT 24
Finished Aug 08 05:13:15 PM PDT 24
Peak memory 196712 kb
Host smart-2bebbc31-8362-4691-9da8-a8051564f7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847484521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.847484521
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2651547328
Short name T449
Test name
Test status
Simulation time 89457347 ps
CPU time 1.36 seconds
Started Aug 08 05:13:02 PM PDT 24
Finished Aug 08 05:13:03 PM PDT 24
Peak memory 197292 kb
Host smart-dc334c3b-b26d-4687-b949-a5d2893c7a76
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651547328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2651547328
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.2932729951
Short name T395
Test name
Test status
Simulation time 15573665713 ps
CPU time 105.72 seconds
Started Aug 08 05:12:56 PM PDT 24
Finished Aug 08 05:14:42 PM PDT 24
Peak memory 198780 kb
Host smart-ff64ee19-ef50-458c-a9f4-24a209a260ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932729951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.2932729951
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.3628960046
Short name T55
Test name
Test status
Simulation time 146943565529 ps
CPU time 854.95 seconds
Started Aug 08 05:13:00 PM PDT 24
Finished Aug 08 05:27:15 PM PDT 24
Peak memory 198808 kb
Host smart-7fbfa475-8d1e-4cdc-9033-73ec93c78d3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3628960046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.3628960046
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1814848720
Short name T523
Test name
Test status
Simulation time 15162548 ps
CPU time 0.61 seconds
Started Aug 08 05:13:09 PM PDT 24
Finished Aug 08 05:13:09 PM PDT 24
Peak memory 194556 kb
Host smart-8f32ac09-e081-4a1f-8619-affae78be20b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814848720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1814848720
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3309957605
Short name T301
Test name
Test status
Simulation time 40042695 ps
CPU time 0.76 seconds
Started Aug 08 05:13:20 PM PDT 24
Finished Aug 08 05:13:20 PM PDT 24
Peak memory 195696 kb
Host smart-90928e65-d5d7-49cf-85fa-7a36102c241e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309957605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3309957605
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1389673294
Short name T695
Test name
Test status
Simulation time 1457662616 ps
CPU time 10.49 seconds
Started Aug 08 05:13:06 PM PDT 24
Finished Aug 08 05:13:17 PM PDT 24
Peak memory 197564 kb
Host smart-67852396-7696-4c19-9810-1c14e22fe8fa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389673294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1389673294
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.2550285338
Short name T264
Test name
Test status
Simulation time 100712431 ps
CPU time 1.18 seconds
Started Aug 08 05:13:07 PM PDT 24
Finished Aug 08 05:13:08 PM PDT 24
Peak memory 197212 kb
Host smart-8bf7976b-1225-40d3-aae9-861407449fbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550285338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2550285338
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1048333312
Short name T160
Test name
Test status
Simulation time 80529009 ps
CPU time 1.24 seconds
Started Aug 08 05:12:59 PM PDT 24
Finished Aug 08 05:13:00 PM PDT 24
Peak memory 196584 kb
Host smart-73407b20-144f-4faf-ab7f-db1ae24b0b3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048333312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1048333312
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.30340264
Short name T438
Test name
Test status
Simulation time 86188056 ps
CPU time 3.39 seconds
Started Aug 08 05:13:17 PM PDT 24
Finished Aug 08 05:13:21 PM PDT 24
Peak memory 198652 kb
Host smart-3e4a313c-fbce-4e89-903c-43094977d920
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30340264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.gpio_intr_with_filter_rand_intr_event.30340264
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2896275349
Short name T51
Test name
Test status
Simulation time 61457873 ps
CPU time 1.96 seconds
Started Aug 08 05:13:04 PM PDT 24
Finished Aug 08 05:13:06 PM PDT 24
Peak memory 197188 kb
Host smart-91853ad9-4d2b-421d-b253-71ca4f1425f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896275349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2896275349
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2733540326
Short name T417
Test name
Test status
Simulation time 118287838 ps
CPU time 1.28 seconds
Started Aug 08 05:13:13 PM PDT 24
Finished Aug 08 05:13:14 PM PDT 24
Peak memory 198528 kb
Host smart-edd11b15-1dc7-4892-8b37-79391b62a661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733540326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2733540326
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.4049207755
Short name T273
Test name
Test status
Simulation time 78596503 ps
CPU time 1.31 seconds
Started Aug 08 05:13:06 PM PDT 24
Finished Aug 08 05:13:07 PM PDT 24
Peak memory 198656 kb
Host smart-eb44c1b4-fd48-4723-8133-ea5f983ac231
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049207755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.4049207755
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1172475358
Short name T501
Test name
Test status
Simulation time 108775451 ps
CPU time 1.63 seconds
Started Aug 08 05:13:11 PM PDT 24
Finished Aug 08 05:13:12 PM PDT 24
Peak memory 198752 kb
Host smart-06aeb2d8-49dd-492e-8755-47bc3a04319e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172475358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1172475358
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.1142615112
Short name T344
Test name
Test status
Simulation time 142687499 ps
CPU time 0.83 seconds
Started Aug 08 05:13:08 PM PDT 24
Finished Aug 08 05:13:09 PM PDT 24
Peak memory 195768 kb
Host smart-6f5d25cf-2d8b-4cf4-9d18-c30be3fd66d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142615112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1142615112
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.4138237805
Short name T298
Test name
Test status
Simulation time 27235441 ps
CPU time 0.67 seconds
Started Aug 08 05:13:11 PM PDT 24
Finished Aug 08 05:13:12 PM PDT 24
Peak memory 194580 kb
Host smart-59975b07-56cf-42c7-89dd-8752324f50a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138237805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.4138237805
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1531381241
Short name T644
Test name
Test status
Simulation time 2288290631 ps
CPU time 59.99 seconds
Started Aug 08 05:13:00 PM PDT 24
Finished Aug 08 05:14:00 PM PDT 24
Peak memory 198676 kb
Host smart-008c036d-665b-4b7b-9097-4a26a1b9590d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531381241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1531381241
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1192325133
Short name T276
Test name
Test status
Simulation time 52786472 ps
CPU time 0.58 seconds
Started Aug 08 05:13:07 PM PDT 24
Finished Aug 08 05:13:07 PM PDT 24
Peak memory 194568 kb
Host smart-a29942e2-807e-4d25-978d-8d487d26f1b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192325133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1192325133
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1521596036
Short name T661
Test name
Test status
Simulation time 27279583 ps
CPU time 0.82 seconds
Started Aug 08 05:13:12 PM PDT 24
Finished Aug 08 05:13:13 PM PDT 24
Peak memory 195928 kb
Host smart-270dabd4-168b-403f-a281-df5dcd3e8123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521596036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1521596036
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1645928703
Short name T214
Test name
Test status
Simulation time 96388745 ps
CPU time 4.73 seconds
Started Aug 08 05:13:05 PM PDT 24
Finished Aug 08 05:13:10 PM PDT 24
Peak memory 196520 kb
Host smart-9d4179c9-51c9-4f9e-8b69-c1d9a87d67f5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645928703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1645928703
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.136729294
Short name T423
Test name
Test status
Simulation time 1060651275 ps
CPU time 0.95 seconds
Started Aug 08 05:13:16 PM PDT 24
Finished Aug 08 05:13:17 PM PDT 24
Peak memory 197688 kb
Host smart-91f94a26-554d-4748-ba74-4417015c60e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136729294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.136729294
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1037421400
Short name T410
Test name
Test status
Simulation time 385059215 ps
CPU time 1.42 seconds
Started Aug 08 05:13:11 PM PDT 24
Finished Aug 08 05:13:13 PM PDT 24
Peak memory 197652 kb
Host smart-c02ae41f-b8e3-4a88-b8f9-2e4fab6ad100
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037421400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1037421400
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3915434081
Short name T420
Test name
Test status
Simulation time 61083186 ps
CPU time 1.86 seconds
Started Aug 08 05:13:06 PM PDT 24
Finished Aug 08 05:13:08 PM PDT 24
Peak memory 198668 kb
Host smart-a85ffd8c-1480-420b-a7fb-2a869fd9ac59
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915434081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3915434081
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3799502203
Short name T622
Test name
Test status
Simulation time 108402290 ps
CPU time 1.9 seconds
Started Aug 08 05:13:11 PM PDT 24
Finished Aug 08 05:13:13 PM PDT 24
Peak memory 196348 kb
Host smart-15b05123-c179-4ae3-b4bd-ba765695beed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799502203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3799502203
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3595142361
Short name T714
Test name
Test status
Simulation time 63388290 ps
CPU time 0.75 seconds
Started Aug 08 05:13:06 PM PDT 24
Finished Aug 08 05:13:07 PM PDT 24
Peak memory 195888 kb
Host smart-114700d5-f012-42b5-96c1-e2e6de34adff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595142361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3595142361
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1887517330
Short name T245
Test name
Test status
Simulation time 29002888 ps
CPU time 0.94 seconds
Started Aug 08 05:13:08 PM PDT 24
Finished Aug 08 05:13:09 PM PDT 24
Peak memory 196552 kb
Host smart-92eb1fde-31c6-456e-a3de-29750d46d737
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887517330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1887517330
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.901981563
Short name T389
Test name
Test status
Simulation time 98235202 ps
CPU time 4.52 seconds
Started Aug 08 05:13:08 PM PDT 24
Finished Aug 08 05:13:13 PM PDT 24
Peak memory 198564 kb
Host smart-3768d10b-a41c-439b-a811-b19b694d2100
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901981563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.901981563
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.88240497
Short name T505
Test name
Test status
Simulation time 59943408 ps
CPU time 1.17 seconds
Started Aug 08 05:13:11 PM PDT 24
Finished Aug 08 05:13:12 PM PDT 24
Peak memory 196324 kb
Host smart-a337f2bb-de09-4936-84a1-eddcbeabe857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88240497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.88240497
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2524566074
Short name T404
Test name
Test status
Simulation time 158465106 ps
CPU time 1.3 seconds
Started Aug 08 05:13:15 PM PDT 24
Finished Aug 08 05:13:16 PM PDT 24
Peak memory 196060 kb
Host smart-55871419-069f-416a-ae3a-f79c2a458cd4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524566074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2524566074
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1940080326
Short name T43
Test name
Test status
Simulation time 4466667756 ps
CPU time 106.73 seconds
Started Aug 08 05:13:12 PM PDT 24
Finished Aug 08 05:14:58 PM PDT 24
Peak memory 198700 kb
Host smart-f3a78ed0-78cc-4597-9308-1604ba82955b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940080326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1940080326
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.4254898184
Short name T561
Test name
Test status
Simulation time 16538109 ps
CPU time 0.6 seconds
Started Aug 08 05:13:11 PM PDT 24
Finished Aug 08 05:13:11 PM PDT 24
Peak memory 194712 kb
Host smart-6d94523a-80ea-4069-8700-5ad823858ab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254898184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.4254898184
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3855763451
Short name T120
Test name
Test status
Simulation time 48043317 ps
CPU time 0.91 seconds
Started Aug 08 05:13:08 PM PDT 24
Finished Aug 08 05:13:09 PM PDT 24
Peak memory 197144 kb
Host smart-544ac93d-2bcf-4dec-841d-8ad7b051453c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855763451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3855763451
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2318257644
Short name T221
Test name
Test status
Simulation time 338785689 ps
CPU time 17.87 seconds
Started Aug 08 05:13:06 PM PDT 24
Finished Aug 08 05:13:24 PM PDT 24
Peak memory 197496 kb
Host smart-ca35cd61-f227-4ec7-860a-484047cd78d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318257644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2318257644
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1439459244
Short name T206
Test name
Test status
Simulation time 314157441 ps
CPU time 0.99 seconds
Started Aug 08 05:13:15 PM PDT 24
Finished Aug 08 05:13:16 PM PDT 24
Peak memory 197700 kb
Host smart-353d111a-de7d-49e5-9b5d-7f224b28df2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439459244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1439459244
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2301791960
Short name T620
Test name
Test status
Simulation time 109064678 ps
CPU time 0.7 seconds
Started Aug 08 05:13:13 PM PDT 24
Finished Aug 08 05:13:14 PM PDT 24
Peak memory 194936 kb
Host smart-29e04760-b7ff-43ef-947c-34d228cd96ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301791960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2301791960
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.817481189
Short name T65
Test name
Test status
Simulation time 259597636 ps
CPU time 1.43 seconds
Started Aug 08 05:13:03 PM PDT 24
Finished Aug 08 05:13:04 PM PDT 24
Peak memory 198644 kb
Host smart-0707c908-ba1e-4cd9-b145-243a1fbd76f9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817481189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.817481189
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1886503736
Short name T706
Test name
Test status
Simulation time 155183992 ps
CPU time 1.44 seconds
Started Aug 08 05:13:11 PM PDT 24
Finished Aug 08 05:13:12 PM PDT 24
Peak memory 196300 kb
Host smart-b9a84a55-aa23-4f5d-9833-504dcc7445e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886503736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1886503736
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1721037348
Short name T68
Test name
Test status
Simulation time 125228474 ps
CPU time 1.33 seconds
Started Aug 08 05:13:13 PM PDT 24
Finished Aug 08 05:13:15 PM PDT 24
Peak memory 197376 kb
Host smart-65d829f1-afb7-4153-a2cb-1159d5e52e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721037348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1721037348
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3291655252
Short name T472
Test name
Test status
Simulation time 176708288 ps
CPU time 1.03 seconds
Started Aug 08 05:13:08 PM PDT 24
Finished Aug 08 05:13:10 PM PDT 24
Peak memory 196332 kb
Host smart-812df615-9440-4ab6-a885-828aa22f3ba3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291655252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3291655252
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1623555548
Short name T595
Test name
Test status
Simulation time 406699773 ps
CPU time 6.53 seconds
Started Aug 08 05:13:06 PM PDT 24
Finished Aug 08 05:13:13 PM PDT 24
Peak memory 198516 kb
Host smart-29725f19-2f63-475b-9b62-7a999df50bea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623555548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1623555548
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2460748256
Short name T386
Test name
Test status
Simulation time 85705707 ps
CPU time 1.25 seconds
Started Aug 08 05:13:16 PM PDT 24
Finished Aug 08 05:13:17 PM PDT 24
Peak memory 197760 kb
Host smart-c36b2118-11d2-467f-a8c7-4d52ce78835d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460748256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2460748256
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1839523996
Short name T70
Test name
Test status
Simulation time 36967944 ps
CPU time 0.88 seconds
Started Aug 08 05:13:15 PM PDT 24
Finished Aug 08 05:13:16 PM PDT 24
Peak memory 197536 kb
Host smart-93ea91c6-fe1c-4f76-8370-bc3ff2a7e37b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839523996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1839523996
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.368680027
Short name T323
Test name
Test status
Simulation time 12009087703 ps
CPU time 38.31 seconds
Started Aug 08 05:13:02 PM PDT 24
Finished Aug 08 05:13:40 PM PDT 24
Peak memory 198620 kb
Host smart-ba4db13e-aee8-4908-bb99-209048547cc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368680027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.368680027
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.4106557829
Short name T639
Test name
Test status
Simulation time 82277443336 ps
CPU time 2429.94 seconds
Started Aug 08 05:13:05 PM PDT 24
Finished Aug 08 05:53:35 PM PDT 24
Peak memory 198880 kb
Host smart-fbe10452-e491-4df5-b823-d4f5fd68e7ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4106557829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.4106557829
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3200427069
Short name T292
Test name
Test status
Simulation time 69912586 ps
CPU time 0.6 seconds
Started Aug 08 05:12:20 PM PDT 24
Finished Aug 08 05:12:21 PM PDT 24
Peak memory 194428 kb
Host smart-b45055ba-7b91-4fc5-97c7-7ff094086a4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200427069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3200427069
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1620406138
Short name T254
Test name
Test status
Simulation time 51004705 ps
CPU time 0.74 seconds
Started Aug 08 05:12:11 PM PDT 24
Finished Aug 08 05:12:12 PM PDT 24
Peak memory 194812 kb
Host smart-ed9d95c4-940c-44fd-b7d8-d1c6ff5d60b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620406138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1620406138
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1276851862
Short name T651
Test name
Test status
Simulation time 720154662 ps
CPU time 21.02 seconds
Started Aug 08 05:12:14 PM PDT 24
Finished Aug 08 05:12:35 PM PDT 24
Peak memory 198468 kb
Host smart-e68cf3ed-4dc2-42a0-a51a-63e90db91246
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276851862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1276851862
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.199944123
Short name T67
Test name
Test status
Simulation time 139030636 ps
CPU time 0.98 seconds
Started Aug 08 05:12:16 PM PDT 24
Finished Aug 08 05:12:18 PM PDT 24
Peak memory 197108 kb
Host smart-50a84fbc-2869-4df8-9789-633b008dbe84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199944123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.199944123
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2525766262
Short name T447
Test name
Test status
Simulation time 364991799 ps
CPU time 1.14 seconds
Started Aug 08 05:12:15 PM PDT 24
Finished Aug 08 05:12:16 PM PDT 24
Peak memory 196432 kb
Host smart-f2cba7a7-9503-43a7-b56d-b472b31e6a47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525766262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2525766262
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.699606255
Short name T243
Test name
Test status
Simulation time 197507453 ps
CPU time 2.12 seconds
Started Aug 08 05:12:25 PM PDT 24
Finished Aug 08 05:12:27 PM PDT 24
Peak memory 197288 kb
Host smart-1030e696-d719-4a26-9e27-0ca91bbbfddd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699606255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.699606255
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1829522662
Short name T128
Test name
Test status
Simulation time 316118170 ps
CPU time 1.32 seconds
Started Aug 08 05:12:26 PM PDT 24
Finished Aug 08 05:12:27 PM PDT 24
Peak memory 197532 kb
Host smart-9c0f90f7-f8db-42df-9d8e-47072b2040ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829522662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1829522662
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2007171759
Short name T359
Test name
Test status
Simulation time 86049956 ps
CPU time 0.94 seconds
Started Aug 08 05:12:14 PM PDT 24
Finished Aug 08 05:12:15 PM PDT 24
Peak memory 196428 kb
Host smart-8f8e579c-eeec-4788-ab87-f169aa8ce2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007171759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2007171759
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.4133579741
Short name T210
Test name
Test status
Simulation time 22692717 ps
CPU time 0.66 seconds
Started Aug 08 05:12:16 PM PDT 24
Finished Aug 08 05:12:17 PM PDT 24
Peak memory 194752 kb
Host smart-8ac175ca-ce42-41ce-ad48-c222541b3e88
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133579741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.4133579741
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2866026099
Short name T248
Test name
Test status
Simulation time 2360954294 ps
CPU time 6.45 seconds
Started Aug 08 05:12:16 PM PDT 24
Finished Aug 08 05:12:23 PM PDT 24
Peak memory 198588 kb
Host smart-060cd394-34cc-44ea-b522-7de53f241307
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866026099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2866026099
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2042346480
Short name T44
Test name
Test status
Simulation time 235233084 ps
CPU time 0.84 seconds
Started Aug 08 05:12:16 PM PDT 24
Finished Aug 08 05:12:17 PM PDT 24
Peak memory 214304 kb
Host smart-e7e1daed-b8d1-4601-8dd9-f184829e2a09
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042346480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2042346480
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.340485347
Short name T558
Test name
Test status
Simulation time 386037105 ps
CPU time 1.47 seconds
Started Aug 08 05:12:15 PM PDT 24
Finished Aug 08 05:12:16 PM PDT 24
Peak memory 197312 kb
Host smart-4ae19e99-4909-4f21-b379-a072c46bb36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340485347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.340485347
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3497542426
Short name T675
Test name
Test status
Simulation time 81094175 ps
CPU time 0.92 seconds
Started Aug 08 05:12:19 PM PDT 24
Finished Aug 08 05:12:20 PM PDT 24
Peak memory 196904 kb
Host smart-aa86d89a-7068-40b6-a2ba-405447ae304a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497542426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3497542426
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3490742695
Short name T468
Test name
Test status
Simulation time 15225335191 ps
CPU time 196.23 seconds
Started Aug 08 05:12:08 PM PDT 24
Finished Aug 08 05:15:24 PM PDT 24
Peak memory 192616 kb
Host smart-008767ee-fd7f-4472-803f-c4d7c6ca3770
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490742695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3490742695
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.603623213
Short name T709
Test name
Test status
Simulation time 30993189 ps
CPU time 0.54 seconds
Started Aug 08 05:13:14 PM PDT 24
Finished Aug 08 05:13:15 PM PDT 24
Peak memory 193208 kb
Host smart-6ccdae97-80c9-4682-8ab1-7c6d6e12694a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603623213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.603623213
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.293416550
Short name T186
Test name
Test status
Simulation time 447083283 ps
CPU time 0.93 seconds
Started Aug 08 05:13:11 PM PDT 24
Finished Aug 08 05:13:12 PM PDT 24
Peak memory 197024 kb
Host smart-4b438cbc-b674-4902-af35-e9f3e6955e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293416550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.293416550
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1353524070
Short name T382
Test name
Test status
Simulation time 2984091098 ps
CPU time 4.8 seconds
Started Aug 08 05:13:17 PM PDT 24
Finished Aug 08 05:13:22 PM PDT 24
Peak memory 196560 kb
Host smart-f68d4478-a330-4b24-8a26-fec94c0ab917
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353524070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1353524070
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.519288802
Short name T527
Test name
Test status
Simulation time 47379202 ps
CPU time 0.65 seconds
Started Aug 08 05:13:14 PM PDT 24
Finished Aug 08 05:13:14 PM PDT 24
Peak memory 194936 kb
Host smart-f239b1f3-23a1-410a-ab7e-eaf20adbedf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519288802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.519288802
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2668705719
Short name T413
Test name
Test status
Simulation time 75793576 ps
CPU time 1.18 seconds
Started Aug 08 05:13:22 PM PDT 24
Finished Aug 08 05:13:23 PM PDT 24
Peak memory 197392 kb
Host smart-4b1e1bfc-9fd3-4b73-9e87-b445434a8f0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668705719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2668705719
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.4174544678
Short name T615
Test name
Test status
Simulation time 135806353 ps
CPU time 2.71 seconds
Started Aug 08 05:13:28 PM PDT 24
Finished Aug 08 05:13:31 PM PDT 24
Peak memory 198328 kb
Host smart-82a7f151-caf7-4641-bb97-73f1d01b096f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174544678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.4174544678
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.287635341
Short name T324
Test name
Test status
Simulation time 204813438 ps
CPU time 1.76 seconds
Started Aug 08 05:13:23 PM PDT 24
Finished Aug 08 05:13:25 PM PDT 24
Peak memory 197420 kb
Host smart-691e458f-e3c4-48df-bccb-bab12bdefb5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287635341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.
287635341
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3186587472
Short name T282
Test name
Test status
Simulation time 97941059 ps
CPU time 0.96 seconds
Started Aug 08 05:13:35 PM PDT 24
Finished Aug 08 05:13:36 PM PDT 24
Peak memory 197072 kb
Host smart-273241bf-4deb-4584-bd12-75bd995ac29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186587472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3186587472
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2975614676
Short name T363
Test name
Test status
Simulation time 102480103 ps
CPU time 0.87 seconds
Started Aug 08 05:13:15 PM PDT 24
Finished Aug 08 05:13:16 PM PDT 24
Peak memory 196996 kb
Host smart-b0283539-8a1c-4b37-8829-fedbc53c1e89
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975614676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2975614676
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2432691379
Short name T167
Test name
Test status
Simulation time 745840730 ps
CPU time 3.86 seconds
Started Aug 08 05:13:14 PM PDT 24
Finished Aug 08 05:13:18 PM PDT 24
Peak memory 198492 kb
Host smart-48c3c4b8-7d65-468d-92a0-ce5197eedc87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432691379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2432691379
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3028239735
Short name T680
Test name
Test status
Simulation time 68429586 ps
CPU time 1.13 seconds
Started Aug 08 05:13:13 PM PDT 24
Finished Aug 08 05:13:14 PM PDT 24
Peak memory 196976 kb
Host smart-4bb4c9da-0a85-4ef6-a535-b54e9f4584fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028239735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3028239735
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.723966888
Short name T173
Test name
Test status
Simulation time 86675157 ps
CPU time 1.37 seconds
Started Aug 08 05:13:05 PM PDT 24
Finished Aug 08 05:13:06 PM PDT 24
Peak memory 198456 kb
Host smart-9c96a0ec-4ed6-49e9-866d-34373a668dce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723966888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.723966888
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1032338026
Short name T593
Test name
Test status
Simulation time 20120697193 ps
CPU time 129.09 seconds
Started Aug 08 05:13:06 PM PDT 24
Finished Aug 08 05:15:16 PM PDT 24
Peak memory 198740 kb
Host smart-7704e14a-1559-4432-8032-ae5a52bf7802
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032338026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1032338026
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.358295301
Short name T691
Test name
Test status
Simulation time 108392343013 ps
CPU time 122.8 seconds
Started Aug 08 05:13:11 PM PDT 24
Finished Aug 08 05:15:14 PM PDT 24
Peak memory 198832 kb
Host smart-0c7d1102-75fd-43fa-b904-8e4eb6030470
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=358295301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.358295301
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.9859342
Short name T635
Test name
Test status
Simulation time 29816707 ps
CPU time 0.61 seconds
Started Aug 08 05:13:08 PM PDT 24
Finished Aug 08 05:13:09 PM PDT 24
Peak memory 195408 kb
Host smart-e08f39d2-6b2d-47ea-ab7d-a44a45df9a72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9859342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.9859342
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1032839827
Short name T314
Test name
Test status
Simulation time 90879275 ps
CPU time 0.89 seconds
Started Aug 08 05:13:09 PM PDT 24
Finished Aug 08 05:13:10 PM PDT 24
Peak memory 195856 kb
Host smart-10b1cb31-70c7-4dc9-9af1-536175dc2fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032839827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1032839827
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.924781079
Short name T451
Test name
Test status
Simulation time 211868320 ps
CPU time 11.58 seconds
Started Aug 08 05:13:25 PM PDT 24
Finished Aug 08 05:13:36 PM PDT 24
Peak memory 196064 kb
Host smart-943ee8f6-8b26-459d-a6b8-16f83e72d663
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924781079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.924781079
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3562173566
Short name T244
Test name
Test status
Simulation time 89404783 ps
CPU time 1.02 seconds
Started Aug 08 05:13:21 PM PDT 24
Finished Aug 08 05:13:22 PM PDT 24
Peak memory 197104 kb
Host smart-c91fe514-8759-466f-b090-9541b21cd6d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562173566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3562173566
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3642185059
Short name T568
Test name
Test status
Simulation time 58890314 ps
CPU time 0.97 seconds
Started Aug 08 05:13:19 PM PDT 24
Finished Aug 08 05:13:20 PM PDT 24
Peak memory 196596 kb
Host smart-b0d85d37-d9b7-4c14-9720-aac13097fdf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642185059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3642185059
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2790165068
Short name T100
Test name
Test status
Simulation time 395587910 ps
CPU time 2.34 seconds
Started Aug 08 05:13:26 PM PDT 24
Finished Aug 08 05:13:28 PM PDT 24
Peak memory 198460 kb
Host smart-c01f6a60-fc09-4675-ac31-5ddfff824403
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790165068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2790165068
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2042779917
Short name T598
Test name
Test status
Simulation time 1935276766 ps
CPU time 3.04 seconds
Started Aug 08 05:13:16 PM PDT 24
Finished Aug 08 05:13:19 PM PDT 24
Peak memory 196348 kb
Host smart-f1340530-ca59-40df-80c3-afc4a45ac1dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042779917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2042779917
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.553496232
Short name T287
Test name
Test status
Simulation time 130427428 ps
CPU time 0.86 seconds
Started Aug 08 05:13:23 PM PDT 24
Finished Aug 08 05:13:24 PM PDT 24
Peak memory 195848 kb
Host smart-556b7853-ab90-42f4-a6e9-50a5cf1a005f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553496232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.553496232
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.333975306
Short name T197
Test name
Test status
Simulation time 62816754 ps
CPU time 0.77 seconds
Started Aug 08 05:13:17 PM PDT 24
Finished Aug 08 05:13:18 PM PDT 24
Peak memory 195756 kb
Host smart-1d80091c-d7de-4272-9052-b54d6806fca7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333975306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup
_pulldown.333975306
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1159166506
Short name T341
Test name
Test status
Simulation time 123240781 ps
CPU time 1.6 seconds
Started Aug 08 05:13:22 PM PDT 24
Finished Aug 08 05:13:24 PM PDT 24
Peak memory 198508 kb
Host smart-0ccad27e-d174-4406-babc-3b22bd5a5c09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159166506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1159166506
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2191279475
Short name T605
Test name
Test status
Simulation time 61354798 ps
CPU time 1.12 seconds
Started Aug 08 05:13:19 PM PDT 24
Finished Aug 08 05:13:21 PM PDT 24
Peak memory 196024 kb
Host smart-3a6e4212-78f3-4f1b-9702-f5b5acd4e317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191279475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2191279475
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2678878883
Short name T140
Test name
Test status
Simulation time 114440730 ps
CPU time 1.03 seconds
Started Aug 08 05:13:16 PM PDT 24
Finished Aug 08 05:13:17 PM PDT 24
Peak memory 196916 kb
Host smart-f461519c-0d08-41ab-b226-cd2a4c83fc01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678878883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2678878883
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.735726908
Short name T6
Test name
Test status
Simulation time 48308025294 ps
CPU time 121.38 seconds
Started Aug 08 05:13:28 PM PDT 24
Finished Aug 08 05:15:29 PM PDT 24
Peak memory 198708 kb
Host smart-6b6b528e-009a-465e-be16-f4d98b27b76f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735726908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.735726908
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1369934322
Short name T141
Test name
Test status
Simulation time 15963321 ps
CPU time 0.57 seconds
Started Aug 08 05:13:14 PM PDT 24
Finished Aug 08 05:13:15 PM PDT 24
Peak memory 194412 kb
Host smart-6bb3afe8-ba29-4b92-b7f5-f8c8547bd578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369934322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1369934322
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.513120269
Short name T643
Test name
Test status
Simulation time 24711882 ps
CPU time 0.81 seconds
Started Aug 08 05:13:19 PM PDT 24
Finished Aug 08 05:13:19 PM PDT 24
Peak memory 195856 kb
Host smart-2adaecb1-8f9c-43aa-ae45-b8638475690e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513120269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.513120269
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2618236311
Short name T113
Test name
Test status
Simulation time 260132943 ps
CPU time 6.91 seconds
Started Aug 08 05:13:10 PM PDT 24
Finished Aug 08 05:13:17 PM PDT 24
Peak memory 197324 kb
Host smart-a917676f-52b3-4c65-912f-2676c4f02dc8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618236311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2618236311
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.983771706
Short name T596
Test name
Test status
Simulation time 31543756 ps
CPU time 0.68 seconds
Started Aug 08 05:13:22 PM PDT 24
Finished Aug 08 05:13:23 PM PDT 24
Peak memory 194664 kb
Host smart-233fd546-8a5b-4e4b-838a-7be9b46730f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983771706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.983771706
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1913727234
Short name T542
Test name
Test status
Simulation time 331933287 ps
CPU time 1.18 seconds
Started Aug 08 05:13:25 PM PDT 24
Finished Aug 08 05:13:26 PM PDT 24
Peak memory 197128 kb
Host smart-0ad8bfc2-9330-4215-8004-6f21b67acacc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913727234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1913727234
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3596529077
Short name T158
Test name
Test status
Simulation time 173661701 ps
CPU time 3.61 seconds
Started Aug 08 05:13:14 PM PDT 24
Finished Aug 08 05:13:18 PM PDT 24
Peak memory 198664 kb
Host smart-d9629cf4-5d84-43c5-bad2-c51d3e80bbb6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596529077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3596529077
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1260146186
Short name T159
Test name
Test status
Simulation time 253846016 ps
CPU time 2.45 seconds
Started Aug 08 05:13:13 PM PDT 24
Finished Aug 08 05:13:16 PM PDT 24
Peak memory 196376 kb
Host smart-5c66d9d0-7b54-4147-8c80-91e9aec3230a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260146186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1260146186
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.1857212493
Short name T234
Test name
Test status
Simulation time 81365729 ps
CPU time 0.91 seconds
Started Aug 08 05:13:14 PM PDT 24
Finished Aug 08 05:13:15 PM PDT 24
Peak memory 196276 kb
Host smart-e5ab154a-2ef7-4b38-8aef-563eec67ea94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857212493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.1857212493
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.492242441
Short name T572
Test name
Test status
Simulation time 91765337 ps
CPU time 1.12 seconds
Started Aug 08 05:13:16 PM PDT 24
Finished Aug 08 05:13:18 PM PDT 24
Peak memory 197268 kb
Host smart-b9f6726b-b910-4e1b-8f36-96d60a78154d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492242441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.492242441
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.4069953056
Short name T338
Test name
Test status
Simulation time 194941460 ps
CPU time 3.28 seconds
Started Aug 08 05:13:17 PM PDT 24
Finished Aug 08 05:13:21 PM PDT 24
Peak memory 198436 kb
Host smart-769665b5-4d03-40a5-bec2-4a07fbdf6910
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069953056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.4069953056
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1298295430
Short name T290
Test name
Test status
Simulation time 60816564 ps
CPU time 1.22 seconds
Started Aug 08 05:13:10 PM PDT 24
Finished Aug 08 05:13:11 PM PDT 24
Peak memory 196364 kb
Host smart-a2a5d7a0-c2f3-4c32-b40c-2117d10bae35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298295430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1298295430
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1811313533
Short name T428
Test name
Test status
Simulation time 249992910 ps
CPU time 0.79 seconds
Started Aug 08 05:13:19 PM PDT 24
Finished Aug 08 05:13:20 PM PDT 24
Peak memory 195692 kb
Host smart-4462b33e-f3d3-48ce-bfab-5698211ff2f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811313533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1811313533
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3488395203
Short name T232
Test name
Test status
Simulation time 6952869254 ps
CPU time 47.27 seconds
Started Aug 08 05:13:19 PM PDT 24
Finished Aug 08 05:14:06 PM PDT 24
Peak memory 198760 kb
Host smart-541c5cfd-92e1-4b98-bfb3-f55b0ecd3d7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488395203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3488395203
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3019839238
Short name T684
Test name
Test status
Simulation time 19125056 ps
CPU time 0.57 seconds
Started Aug 08 05:13:25 PM PDT 24
Finished Aug 08 05:13:26 PM PDT 24
Peak memory 194260 kb
Host smart-f74b156b-aee5-4cf2-afb5-fd159de6bf1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019839238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3019839238
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1007918256
Short name T220
Test name
Test status
Simulation time 35301501 ps
CPU time 0.91 seconds
Started Aug 08 05:13:28 PM PDT 24
Finished Aug 08 05:13:29 PM PDT 24
Peak memory 197024 kb
Host smart-bb188e35-ce0a-44d7-9776-95378db73b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007918256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1007918256
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3266037539
Short name T474
Test name
Test status
Simulation time 187788683 ps
CPU time 9.96 seconds
Started Aug 08 05:13:17 PM PDT 24
Finished Aug 08 05:13:27 PM PDT 24
Peak memory 197396 kb
Host smart-b3f44269-073d-46a0-97b1-168c98f078cd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266037539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3266037539
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3194617513
Short name T334
Test name
Test status
Simulation time 78011021 ps
CPU time 0.83 seconds
Started Aug 08 05:13:14 PM PDT 24
Finished Aug 08 05:13:15 PM PDT 24
Peak memory 196268 kb
Host smart-bf1c3497-7bdc-4d78-b0d9-7ac3c783c6a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194617513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3194617513
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.454016390
Short name T303
Test name
Test status
Simulation time 171742604 ps
CPU time 0.78 seconds
Started Aug 08 05:13:15 PM PDT 24
Finished Aug 08 05:13:16 PM PDT 24
Peak memory 196764 kb
Host smart-3471bfc9-ef95-4b83-9f12-2d97bab6c0f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454016390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.454016390
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1777776059
Short name T370
Test name
Test status
Simulation time 76705300 ps
CPU time 2.85 seconds
Started Aug 08 05:13:19 PM PDT 24
Finished Aug 08 05:13:22 PM PDT 24
Peak memory 198568 kb
Host smart-eb1dace4-be4b-4d56-affb-910305ca3300
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777776059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1777776059
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3616515506
Short name T194
Test name
Test status
Simulation time 216623290 ps
CPU time 1.48 seconds
Started Aug 08 05:13:11 PM PDT 24
Finished Aug 08 05:13:12 PM PDT 24
Peak memory 197280 kb
Host smart-8bc99219-15ab-4566-9996-54631010df4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616515506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3616515506
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.4209443352
Short name T552
Test name
Test status
Simulation time 118395221 ps
CPU time 1.1 seconds
Started Aug 08 05:13:12 PM PDT 24
Finished Aug 08 05:13:13 PM PDT 24
Peak memory 197364 kb
Host smart-94e92b3d-48df-434e-ab1b-9a00d6fa71a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209443352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.4209443352
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.4190207208
Short name T606
Test name
Test status
Simulation time 296915925 ps
CPU time 1.1 seconds
Started Aug 08 05:13:27 PM PDT 24
Finished Aug 08 05:13:29 PM PDT 24
Peak memory 196524 kb
Host smart-937f4951-c130-44a3-bac5-aa0e7f23cfa4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190207208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.4190207208
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.287266907
Short name T193
Test name
Test status
Simulation time 59515645 ps
CPU time 2.54 seconds
Started Aug 08 05:13:08 PM PDT 24
Finished Aug 08 05:13:11 PM PDT 24
Peak memory 198452 kb
Host smart-06cfbde2-6c42-4275-a8bc-2b6afec122bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287266907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.287266907
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.725737689
Short name T15
Test name
Test status
Simulation time 35537321 ps
CPU time 0.96 seconds
Started Aug 08 05:13:15 PM PDT 24
Finished Aug 08 05:13:16 PM PDT 24
Peak memory 196416 kb
Host smart-9c04af33-2834-43d5-b289-349186fc3f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725737689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.725737689
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2700720341
Short name T467
Test name
Test status
Simulation time 222562699 ps
CPU time 1.17 seconds
Started Aug 08 05:13:17 PM PDT 24
Finished Aug 08 05:13:18 PM PDT 24
Peak memory 196180 kb
Host smart-ffca5ab9-2b85-4998-b0b7-304b0ddcc18d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700720341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2700720341
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3416251710
Short name T317
Test name
Test status
Simulation time 6000630073 ps
CPU time 72.04 seconds
Started Aug 08 05:13:25 PM PDT 24
Finished Aug 08 05:14:38 PM PDT 24
Peak memory 198656 kb
Host smart-8cb8f21f-167e-4e0e-8677-75aeaa2ea294
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416251710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3416251710
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3476535654
Short name T154
Test name
Test status
Simulation time 14150926 ps
CPU time 0.58 seconds
Started Aug 08 05:13:13 PM PDT 24
Finished Aug 08 05:13:14 PM PDT 24
Peak memory 194448 kb
Host smart-933608e1-9d70-4c06-a322-048de8c22c2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476535654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3476535654
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.674113463
Short name T403
Test name
Test status
Simulation time 28294023 ps
CPU time 0.76 seconds
Started Aug 08 05:13:10 PM PDT 24
Finished Aug 08 05:13:11 PM PDT 24
Peak memory 195776 kb
Host smart-2a543b4a-cfc8-471b-bf0c-9f366af5989a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674113463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.674113463
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3850059348
Short name T687
Test name
Test status
Simulation time 446529770 ps
CPU time 10.76 seconds
Started Aug 08 05:13:18 PM PDT 24
Finished Aug 08 05:13:29 PM PDT 24
Peak memory 197444 kb
Host smart-1be995bd-66ad-4ece-b955-65828a5d75c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850059348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3850059348
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.4256509850
Short name T446
Test name
Test status
Simulation time 62489095 ps
CPU time 0.92 seconds
Started Aug 08 05:13:21 PM PDT 24
Finished Aug 08 05:13:22 PM PDT 24
Peak memory 196316 kb
Host smart-f589c2eb-363f-43c2-82e3-40a8a32bb940
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256509850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.4256509850
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3432397701
Short name T701
Test name
Test status
Simulation time 79813330 ps
CPU time 1.13 seconds
Started Aug 08 05:13:24 PM PDT 24
Finished Aug 08 05:13:26 PM PDT 24
Peak memory 197336 kb
Host smart-4598fdb5-b91d-4292-8e02-7ccd20f020d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432397701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3432397701
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1383280588
Short name T440
Test name
Test status
Simulation time 149395668 ps
CPU time 3.31 seconds
Started Aug 08 05:13:27 PM PDT 24
Finished Aug 08 05:13:31 PM PDT 24
Peak memory 198592 kb
Host smart-0ddd268e-0443-4341-95eb-920eaa757a4a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383280588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1383280588
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.3881675708
Short name T601
Test name
Test status
Simulation time 60497559 ps
CPU time 1.4 seconds
Started Aug 08 05:13:20 PM PDT 24
Finished Aug 08 05:13:21 PM PDT 24
Peak memory 196976 kb
Host smart-9217abc2-d206-48a9-a1bf-fff068308ec1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881675708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.3881675708
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.359029083
Short name T713
Test name
Test status
Simulation time 49135030 ps
CPU time 0.77 seconds
Started Aug 08 05:13:21 PM PDT 24
Finished Aug 08 05:13:22 PM PDT 24
Peak memory 195948 kb
Host smart-5af6c654-9a5a-470c-8e3b-214c91adf7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359029083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.359029083
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.878231719
Short name T48
Test name
Test status
Simulation time 52875372 ps
CPU time 0.79 seconds
Started Aug 08 05:13:21 PM PDT 24
Finished Aug 08 05:13:22 PM PDT 24
Peak memory 195960 kb
Host smart-429b98e6-dc17-470e-b60e-3fa6c0fcabb8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878231719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.878231719
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.736250908
Short name T336
Test name
Test status
Simulation time 208703750 ps
CPU time 3.82 seconds
Started Aug 08 05:13:13 PM PDT 24
Finished Aug 08 05:13:17 PM PDT 24
Peak memory 198572 kb
Host smart-24e44803-9a40-41c7-96bc-85e9a4ce56fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736250908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ran
dom_long_reg_writes_reg_reads.736250908
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1213119790
Short name T432
Test name
Test status
Simulation time 295410416 ps
CPU time 1.25 seconds
Started Aug 08 05:13:14 PM PDT 24
Finished Aug 08 05:13:16 PM PDT 24
Peak memory 196932 kb
Host smart-4e74ede2-3439-4154-9886-5407e20c3dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213119790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1213119790
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.1067383225
Short name T155
Test name
Test status
Simulation time 248675088 ps
CPU time 1.18 seconds
Started Aug 08 05:13:24 PM PDT 24
Finished Aug 08 05:13:25 PM PDT 24
Peak memory 196828 kb
Host smart-6c5168a7-2030-40ba-8a38-dc52387891d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067383225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.1067383225
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2565318347
Short name T328
Test name
Test status
Simulation time 2039543169 ps
CPU time 57.33 seconds
Started Aug 08 05:13:13 PM PDT 24
Finished Aug 08 05:14:10 PM PDT 24
Peak memory 198620 kb
Host smart-36d29602-4126-4789-9007-098e91bf4b28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565318347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2565318347
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1080857585
Short name T484
Test name
Test status
Simulation time 122443438 ps
CPU time 0.58 seconds
Started Aug 08 05:13:30 PM PDT 24
Finished Aug 08 05:13:31 PM PDT 24
Peak memory 195456 kb
Host smart-4b167aa7-f6a2-4177-a225-76b5187064e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080857585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1080857585
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.722688690
Short name T215
Test name
Test status
Simulation time 18961181 ps
CPU time 0.67 seconds
Started Aug 08 05:13:25 PM PDT 24
Finished Aug 08 05:13:26 PM PDT 24
Peak memory 194484 kb
Host smart-aeb77339-6062-4726-99e5-a1855f344fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722688690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.722688690
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.722792816
Short name T581
Test name
Test status
Simulation time 308262622 ps
CPU time 9.99 seconds
Started Aug 08 05:13:17 PM PDT 24
Finished Aug 08 05:13:27 PM PDT 24
Peak memory 198532 kb
Host smart-9e21fab2-0e26-4af0-aa0f-3ee92bad9cd3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722792816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres
s.722792816
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3302176666
Short name T707
Test name
Test status
Simulation time 69045322 ps
CPU time 1.04 seconds
Started Aug 08 05:13:40 PM PDT 24
Finished Aug 08 05:13:41 PM PDT 24
Peak memory 198664 kb
Host smart-000122a1-2295-4ded-be41-e66362243bf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302176666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3302176666
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3484452341
Short name T592
Test name
Test status
Simulation time 133888138 ps
CPU time 1.15 seconds
Started Aug 08 05:13:23 PM PDT 24
Finished Aug 08 05:13:24 PM PDT 24
Peak memory 197136 kb
Host smart-e8a853d8-fb0c-4113-b0ca-e0eb0ec693a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484452341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3484452341
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.549016220
Short name T250
Test name
Test status
Simulation time 131611167 ps
CPU time 2.55 seconds
Started Aug 08 05:13:21 PM PDT 24
Finished Aug 08 05:13:24 PM PDT 24
Peak memory 198636 kb
Host smart-09aea892-9b07-422c-874e-77bc0f47b479
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549016220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.549016220
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.896814957
Short name T316
Test name
Test status
Simulation time 387968939 ps
CPU time 2.83 seconds
Started Aug 08 05:13:21 PM PDT 24
Finished Aug 08 05:13:24 PM PDT 24
Peak memory 197664 kb
Host smart-813ef3e4-d063-4a3a-952c-ad3a4e72cabb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896814957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
896814957
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1038272185
Short name T116
Test name
Test status
Simulation time 110989847 ps
CPU time 1.15 seconds
Started Aug 08 05:13:22 PM PDT 24
Finished Aug 08 05:13:23 PM PDT 24
Peak memory 198616 kb
Host smart-510d3bc3-7611-4ce2-a99d-9234e7485478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038272185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1038272185
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1794227024
Short name T246
Test name
Test status
Simulation time 47285609 ps
CPU time 0.76 seconds
Started Aug 08 05:13:22 PM PDT 24
Finished Aug 08 05:13:23 PM PDT 24
Peak memory 196600 kb
Host smart-9bee5034-6f49-401b-801c-0cf4366daefa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794227024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1794227024
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.4132779052
Short name T610
Test name
Test status
Simulation time 694873874 ps
CPU time 4.12 seconds
Started Aug 08 05:13:27 PM PDT 24
Finished Aug 08 05:13:31 PM PDT 24
Peak memory 198420 kb
Host smart-dc97ad26-d84f-4f29-8d4d-71cecd7f5115
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132779052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.4132779052
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2533714615
Short name T384
Test name
Test status
Simulation time 37338372 ps
CPU time 1.08 seconds
Started Aug 08 05:13:25 PM PDT 24
Finished Aug 08 05:13:26 PM PDT 24
Peak memory 197064 kb
Host smart-b4a281bc-aa9c-411a-941f-84a8d8292e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533714615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2533714615
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3533096325
Short name T297
Test name
Test status
Simulation time 112145199 ps
CPU time 1.14 seconds
Started Aug 08 05:13:24 PM PDT 24
Finished Aug 08 05:13:25 PM PDT 24
Peak memory 196288 kb
Host smart-7936816f-7fc7-4e36-97e4-7bdb7cc00c7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533096325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3533096325
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.623958091
Short name T345
Test name
Test status
Simulation time 7762901918 ps
CPU time 205.14 seconds
Started Aug 08 05:13:51 PM PDT 24
Finished Aug 08 05:17:16 PM PDT 24
Peak memory 198652 kb
Host smart-b932e440-57e0-4dc5-a0fd-295d9dc72864
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623958091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.g
pio_stress_all.623958091
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.3263754191
Short name T406
Test name
Test status
Simulation time 33559071 ps
CPU time 0.59 seconds
Started Aug 08 05:13:17 PM PDT 24
Finished Aug 08 05:13:18 PM PDT 24
Peak memory 195324 kb
Host smart-b311a084-4bcc-4589-ae33-c74619a00195
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263754191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.3263754191
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3241023298
Short name T49
Test name
Test status
Simulation time 134317991 ps
CPU time 0.87 seconds
Started Aug 08 05:13:27 PM PDT 24
Finished Aug 08 05:13:28 PM PDT 24
Peak memory 196604 kb
Host smart-00b7a5b4-23b4-417d-ba67-4a62f08ee807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241023298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3241023298
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2940368112
Short name T618
Test name
Test status
Simulation time 614774655 ps
CPU time 18.68 seconds
Started Aug 08 05:13:24 PM PDT 24
Finished Aug 08 05:13:43 PM PDT 24
Peak memory 196796 kb
Host smart-5b77f9fe-6d6c-4627-a388-0576c0a416a2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940368112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2940368112
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3553819964
Short name T686
Test name
Test status
Simulation time 98289743 ps
CPU time 1.18 seconds
Started Aug 08 05:13:14 PM PDT 24
Finished Aug 08 05:13:15 PM PDT 24
Peak memory 197112 kb
Host smart-56e3e0cf-fade-4ab2-9aba-7b8cb1b71a18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553819964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3553819964
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1098739240
Short name T398
Test name
Test status
Simulation time 348834764 ps
CPU time 0.92 seconds
Started Aug 08 05:13:26 PM PDT 24
Finished Aug 08 05:13:27 PM PDT 24
Peak memory 196912 kb
Host smart-bdfd92c3-de5b-4dbb-b3d9-34a138ca75bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098739240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1098739240
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3205101421
Short name T308
Test name
Test status
Simulation time 50595102 ps
CPU time 1.54 seconds
Started Aug 08 05:13:19 PM PDT 24
Finished Aug 08 05:13:20 PM PDT 24
Peak memory 198612 kb
Host smart-8075bf7b-e0f1-4a60-a975-81f52653a152
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205101421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3205101421
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3269191098
Short name T353
Test name
Test status
Simulation time 72846752 ps
CPU time 1.71 seconds
Started Aug 08 05:13:33 PM PDT 24
Finished Aug 08 05:13:35 PM PDT 24
Peak memory 196372 kb
Host smart-445a527e-601a-482f-b5d6-de43ff72e376
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269191098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3269191098
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1226526587
Short name T553
Test name
Test status
Simulation time 116922516 ps
CPU time 1.23 seconds
Started Aug 08 05:13:29 PM PDT 24
Finished Aug 08 05:13:30 PM PDT 24
Peak memory 197412 kb
Host smart-2b2a15f8-e205-428c-913b-8d3e3d02ebea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226526587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1226526587
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.493833718
Short name T18
Test name
Test status
Simulation time 28310952 ps
CPU time 0.7 seconds
Started Aug 08 05:13:34 PM PDT 24
Finished Aug 08 05:13:35 PM PDT 24
Peak memory 195820 kb
Host smart-5232f4d1-a09e-48b6-b215-806e2de2b820
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493833718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.493833718
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.4196712152
Short name T257
Test name
Test status
Simulation time 110775980 ps
CPU time 1.46 seconds
Started Aug 08 05:13:28 PM PDT 24
Finished Aug 08 05:13:29 PM PDT 24
Peak memory 198460 kb
Host smart-02dc51bf-c28d-4e2f-afef-62167d9301c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196712152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.4196712152
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.624282873
Short name T255
Test name
Test status
Simulation time 46177073 ps
CPU time 1.03 seconds
Started Aug 08 05:13:25 PM PDT 24
Finished Aug 08 05:13:27 PM PDT 24
Peak memory 196756 kb
Host smart-2a02ca40-1a33-4ed5-8731-770773540ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624282873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.624282873
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2959714324
Short name T396
Test name
Test status
Simulation time 185592574 ps
CPU time 1.02 seconds
Started Aug 08 05:13:24 PM PDT 24
Finished Aug 08 05:13:26 PM PDT 24
Peak memory 196344 kb
Host smart-ef7b032e-ea1f-464c-aa56-ba79ab716315
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959714324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2959714324
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1664332634
Short name T9
Test name
Test status
Simulation time 9589020798 ps
CPU time 109.04 seconds
Started Aug 08 05:13:19 PM PDT 24
Finished Aug 08 05:15:08 PM PDT 24
Peak memory 198620 kb
Host smart-3ed191fe-8942-4b76-95e6-79452811c7ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664332634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1664332634
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.581835633
Short name T102
Test name
Test status
Simulation time 12197493 ps
CPU time 0.58 seconds
Started Aug 08 05:13:25 PM PDT 24
Finished Aug 08 05:13:36 PM PDT 24
Peak memory 194196 kb
Host smart-d73c6d2e-547b-4d05-9a65-806f843697b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581835633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.581835633
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.513890360
Short name T582
Test name
Test status
Simulation time 41180388 ps
CPU time 0.84 seconds
Started Aug 08 05:13:26 PM PDT 24
Finished Aug 08 05:13:27 PM PDT 24
Peak memory 195848 kb
Host smart-6f57f0ff-930d-4b06-bde3-591d32f98892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513890360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.513890360
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1884815314
Short name T12
Test name
Test status
Simulation time 4421350166 ps
CPU time 24.29 seconds
Started Aug 08 05:13:27 PM PDT 24
Finished Aug 08 05:13:51 PM PDT 24
Peak memory 197828 kb
Host smart-c651331b-2eed-4c4c-9c2b-13e19df1e10d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884815314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1884815314
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1176091143
Short name T235
Test name
Test status
Simulation time 16612447 ps
CPU time 0.64 seconds
Started Aug 08 05:13:37 PM PDT 24
Finished Aug 08 05:13:38 PM PDT 24
Peak memory 194720 kb
Host smart-2a16f3d8-748e-4134-ab27-1e173aa4fbdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176091143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1176091143
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2156984943
Short name T486
Test name
Test status
Simulation time 75919507 ps
CPU time 1.16 seconds
Started Aug 08 05:13:28 PM PDT 24
Finished Aug 08 05:13:29 PM PDT 24
Peak memory 197280 kb
Host smart-bcdf27d4-3012-4a56-a336-599227b784a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156984943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2156984943
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2606600907
Short name T164
Test name
Test status
Simulation time 547460097 ps
CPU time 2.42 seconds
Started Aug 08 05:13:25 PM PDT 24
Finished Aug 08 05:13:28 PM PDT 24
Peak memory 198564 kb
Host smart-c85b432d-b702-4bb0-8ad7-03b5f8c9055b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606600907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2606600907
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3380694907
Short name T291
Test name
Test status
Simulation time 215668240 ps
CPU time 2.78 seconds
Started Aug 08 05:13:28 PM PDT 24
Finished Aug 08 05:13:31 PM PDT 24
Peak memory 197764 kb
Host smart-9bedb93e-1f25-4558-85b0-9706f596752a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380694907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3380694907
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3218240920
Short name T562
Test name
Test status
Simulation time 143030130 ps
CPU time 0.99 seconds
Started Aug 08 05:13:28 PM PDT 24
Finished Aug 08 05:13:29 PM PDT 24
Peak memory 196376 kb
Host smart-20270bac-6b95-41b4-837e-e5982ee4ffdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218240920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3218240920
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1282524409
Short name T459
Test name
Test status
Simulation time 47198548 ps
CPU time 0.93 seconds
Started Aug 08 05:13:23 PM PDT 24
Finished Aug 08 05:13:24 PM PDT 24
Peak memory 196936 kb
Host smart-26cfc4de-28d5-4a57-9889-267dc2d706dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282524409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1282524409
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1717920790
Short name T698
Test name
Test status
Simulation time 1287369315 ps
CPU time 3.65 seconds
Started Aug 08 05:13:39 PM PDT 24
Finished Aug 08 05:13:43 PM PDT 24
Peak memory 198396 kb
Host smart-7ddebdd0-4f31-4f1f-ba37-1472d3f3eb62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717920790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1717920790
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2939523477
Short name T504
Test name
Test status
Simulation time 85672233 ps
CPU time 1.54 seconds
Started Aug 08 05:13:24 PM PDT 24
Finished Aug 08 05:13:26 PM PDT 24
Peak memory 197308 kb
Host smart-da61eb0f-378f-409f-b91c-e45b8a427db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939523477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2939523477
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.4031738475
Short name T669
Test name
Test status
Simulation time 78355928 ps
CPU time 1.13 seconds
Started Aug 08 05:13:26 PM PDT 24
Finished Aug 08 05:13:27 PM PDT 24
Peak memory 196852 kb
Host smart-a509f679-99ec-4b31-8ab9-7cf96f04a678
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031738475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.4031738475
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2316675325
Short name T226
Test name
Test status
Simulation time 5224986357 ps
CPU time 134.76 seconds
Started Aug 08 05:13:17 PM PDT 24
Finished Aug 08 05:15:32 PM PDT 24
Peak memory 198768 kb
Host smart-80ec7f8b-cfcf-4b91-8126-7c1525a4f20e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316675325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2316675325
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2209315873
Short name T296
Test name
Test status
Simulation time 33626218 ps
CPU time 0.56 seconds
Started Aug 08 05:13:13 PM PDT 24
Finished Aug 08 05:13:14 PM PDT 24
Peak memory 195112 kb
Host smart-bbc5aedc-8eda-4636-bc38-0acf49d509c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209315873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2209315873
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.323928773
Short name T50
Test name
Test status
Simulation time 26962323 ps
CPU time 0.83 seconds
Started Aug 08 05:13:27 PM PDT 24
Finished Aug 08 05:13:28 PM PDT 24
Peak memory 194900 kb
Host smart-99c0ca69-964e-42b2-9c95-5755fbd776a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323928773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.323928773
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3774404977
Short name T224
Test name
Test status
Simulation time 176178796 ps
CPU time 9.45 seconds
Started Aug 08 05:13:24 PM PDT 24
Finished Aug 08 05:13:34 PM PDT 24
Peak memory 197332 kb
Host smart-35e32c56-63b8-4522-b49e-0324a3ef5ebd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774404977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3774404977
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3296495013
Short name T348
Test name
Test status
Simulation time 110587923 ps
CPU time 0.72 seconds
Started Aug 08 05:13:31 PM PDT 24
Finished Aug 08 05:13:32 PM PDT 24
Peak memory 195196 kb
Host smart-377a5f84-1fb1-40eb-a151-3dabf0ec5e71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296495013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3296495013
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3176715562
Short name T671
Test name
Test status
Simulation time 256421478 ps
CPU time 1.27 seconds
Started Aug 08 05:13:31 PM PDT 24
Finished Aug 08 05:13:32 PM PDT 24
Peak memory 196532 kb
Host smart-2c40b64c-320d-4b63-81b1-0e4b284e542e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176715562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3176715562
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3879283196
Short name T659
Test name
Test status
Simulation time 376905949 ps
CPU time 3 seconds
Started Aug 08 05:13:25 PM PDT 24
Finished Aug 08 05:13:28 PM PDT 24
Peak memory 198692 kb
Host smart-831e1254-5927-4c5b-9757-1858e6c84346
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879283196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3879283196
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3305061588
Short name T506
Test name
Test status
Simulation time 135374996 ps
CPU time 2.6 seconds
Started Aug 08 05:13:28 PM PDT 24
Finished Aug 08 05:13:36 PM PDT 24
Peak memory 196944 kb
Host smart-2bbaba05-e575-4c66-92b6-95ddbddf8a0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305061588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3305061588
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.4219662293
Short name T126
Test name
Test status
Simulation time 22820268 ps
CPU time 0.83 seconds
Started Aug 08 05:13:24 PM PDT 24
Finished Aug 08 05:13:25 PM PDT 24
Peak memory 196492 kb
Host smart-fd9e7b34-af43-4928-b6ce-3654bdb096f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219662293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.4219662293
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3540194792
Short name T96
Test name
Test status
Simulation time 16266452 ps
CPU time 0.64 seconds
Started Aug 08 05:13:26 PM PDT 24
Finished Aug 08 05:13:27 PM PDT 24
Peak memory 195400 kb
Host smart-da825342-49a5-4e57-8fb1-e28a98fde0ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540194792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3540194792
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3005381057
Short name T587
Test name
Test status
Simulation time 765031019 ps
CPU time 2.57 seconds
Started Aug 08 05:13:24 PM PDT 24
Finished Aug 08 05:13:27 PM PDT 24
Peak memory 198512 kb
Host smart-9f395b4a-2341-4613-9c0d-e0b4a7fb33cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005381057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3005381057
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3936870167
Short name T293
Test name
Test status
Simulation time 110807344 ps
CPU time 1.09 seconds
Started Aug 08 05:13:26 PM PDT 24
Finished Aug 08 05:13:27 PM PDT 24
Peak memory 196740 kb
Host smart-83a80747-cb7f-415f-b9a0-393d235efd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936870167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3936870167
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2789714285
Short name T415
Test name
Test status
Simulation time 213715059 ps
CPU time 1.35 seconds
Started Aug 08 05:13:13 PM PDT 24
Finished Aug 08 05:13:15 PM PDT 24
Peak memory 197372 kb
Host smart-cd22f7b3-76e0-4c0f-92f7-18656f6769d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789714285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2789714285
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.279378789
Short name T609
Test name
Test status
Simulation time 7066871913 ps
CPU time 69.91 seconds
Started Aug 08 05:13:26 PM PDT 24
Finished Aug 08 05:14:36 PM PDT 24
Peak memory 198636 kb
Host smart-45a7e4ea-896e-473d-9a18-cd1cf2be2fcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279378789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.279378789
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.225059265
Short name T481
Test name
Test status
Simulation time 43206540 ps
CPU time 0.55 seconds
Started Aug 08 05:13:23 PM PDT 24
Finished Aug 08 05:13:24 PM PDT 24
Peak memory 194344 kb
Host smart-5880685d-e127-4469-bb53-044d1f356c09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225059265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.225059265
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.344492268
Short name T201
Test name
Test status
Simulation time 28691605 ps
CPU time 0.9 seconds
Started Aug 08 05:13:21 PM PDT 24
Finished Aug 08 05:13:22 PM PDT 24
Peak memory 196332 kb
Host smart-501f2337-66e2-493b-af22-2e7efc84d0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344492268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.344492268
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1939635303
Short name T14
Test name
Test status
Simulation time 245524937 ps
CPU time 12.06 seconds
Started Aug 08 05:13:14 PM PDT 24
Finished Aug 08 05:13:26 PM PDT 24
Peak memory 197256 kb
Host smart-45172911-5b70-4074-873e-137b5882cbcc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939635303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1939635303
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3515278222
Short name T565
Test name
Test status
Simulation time 1458931670 ps
CPU time 1.04 seconds
Started Aug 08 05:13:24 PM PDT 24
Finished Aug 08 05:13:25 PM PDT 24
Peak memory 195940 kb
Host smart-6af3c9ce-171a-492b-8856-9805761e0721
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515278222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3515278222
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.4168351822
Short name T62
Test name
Test status
Simulation time 491110253 ps
CPU time 1.23 seconds
Started Aug 08 05:13:21 PM PDT 24
Finished Aug 08 05:13:22 PM PDT 24
Peak memory 196416 kb
Host smart-4370fb51-424c-4848-9abb-6c3428df3737
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168351822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.4168351822
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2437223630
Short name T230
Test name
Test status
Simulation time 322842558 ps
CPU time 2.84 seconds
Started Aug 08 05:13:44 PM PDT 24
Finished Aug 08 05:13:47 PM PDT 24
Peak memory 198492 kb
Host smart-66d46d1f-a942-459e-9d22-7a666bd31c9f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437223630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2437223630
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1494516790
Short name T611
Test name
Test status
Simulation time 60000952 ps
CPU time 1.32 seconds
Started Aug 08 05:13:22 PM PDT 24
Finished Aug 08 05:13:23 PM PDT 24
Peak memory 197308 kb
Host smart-a2a2827e-abb4-4cd2-a7ff-757f3210cf9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494516790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1494516790
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3588844398
Short name T580
Test name
Test status
Simulation time 49796120 ps
CPU time 0.97 seconds
Started Aug 08 05:13:38 PM PDT 24
Finished Aug 08 05:13:39 PM PDT 24
Peak memory 196492 kb
Host smart-4d2a736d-70c7-4ac1-92a2-2869570f20b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588844398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3588844398
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3375994554
Short name T485
Test name
Test status
Simulation time 22597227 ps
CPU time 0.67 seconds
Started Aug 08 05:13:35 PM PDT 24
Finished Aug 08 05:13:36 PM PDT 24
Peak memory 194868 kb
Host smart-57c2d5fd-a319-487b-aff0-4bcf482114a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375994554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3375994554
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1687896354
Short name T127
Test name
Test status
Simulation time 230989774 ps
CPU time 2.59 seconds
Started Aug 08 05:13:31 PM PDT 24
Finished Aug 08 05:13:34 PM PDT 24
Peak memory 196996 kb
Host smart-08743407-4408-4c01-b510-a76930b2632e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687896354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1687896354
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.203458365
Short name T137
Test name
Test status
Simulation time 298112234 ps
CPU time 1.54 seconds
Started Aug 08 05:13:25 PM PDT 24
Finished Aug 08 05:13:27 PM PDT 24
Peak memory 197188 kb
Host smart-326ce43d-fe40-40fb-9bc1-383792ec166e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203458365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.203458365
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1185837550
Short name T480
Test name
Test status
Simulation time 96956884 ps
CPU time 1.42 seconds
Started Aug 08 05:13:35 PM PDT 24
Finished Aug 08 05:13:37 PM PDT 24
Peak memory 195988 kb
Host smart-b92400ae-9623-4786-8a4f-da86d26e2bb1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185837550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1185837550
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.937764581
Short name T607
Test name
Test status
Simulation time 52593541915 ps
CPU time 1531.66 seconds
Started Aug 08 05:13:25 PM PDT 24
Finished Aug 08 05:38:57 PM PDT 24
Peak memory 198752 kb
Host smart-d16108a8-d495-4274-b954-32deefffadb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=937764581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.937764581
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3282769233
Short name T208
Test name
Test status
Simulation time 112380216 ps
CPU time 0.58 seconds
Started Aug 08 05:12:21 PM PDT 24
Finished Aug 08 05:12:22 PM PDT 24
Peak memory 194356 kb
Host smart-03ba79f0-0123-44c3-9030-798e79304d4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282769233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3282769233
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.4104513680
Short name T142
Test name
Test status
Simulation time 77825225 ps
CPU time 0.79 seconds
Started Aug 08 05:12:30 PM PDT 24
Finished Aug 08 05:12:31 PM PDT 24
Peak memory 195836 kb
Host smart-7535d4b5-1aee-490b-bc07-fcbb2cf6da1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104513680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.4104513680
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.132793230
Short name T560
Test name
Test status
Simulation time 1270560102 ps
CPU time 5.15 seconds
Started Aug 08 05:12:31 PM PDT 24
Finished Aug 08 05:12:37 PM PDT 24
Peak memory 198420 kb
Host smart-830939ed-0658-4273-b54c-637c361ae833
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132793230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.132793230
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1955341320
Short name T266
Test name
Test status
Simulation time 256198061 ps
CPU time 1.06 seconds
Started Aug 08 05:12:20 PM PDT 24
Finished Aug 08 05:12:21 PM PDT 24
Peak memory 198348 kb
Host smart-d2e9d52b-78ba-4a26-baea-3296f40bf143
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955341320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1955341320
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3943571680
Short name T550
Test name
Test status
Simulation time 44830986 ps
CPU time 1.29 seconds
Started Aug 08 05:12:28 PM PDT 24
Finished Aug 08 05:12:30 PM PDT 24
Peak memory 197724 kb
Host smart-ab0a2d02-facd-4e0f-b955-ff495349f153
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943571680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3943571680
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3437537654
Short name T111
Test name
Test status
Simulation time 134292194 ps
CPU time 2.65 seconds
Started Aug 08 05:12:28 PM PDT 24
Finished Aug 08 05:12:31 PM PDT 24
Peak memory 198588 kb
Host smart-772ea8b7-2942-440a-b097-981bd6416319
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437537654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3437537654
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3828890337
Short name T331
Test name
Test status
Simulation time 272390104 ps
CPU time 2.31 seconds
Started Aug 08 05:12:18 PM PDT 24
Finished Aug 08 05:12:20 PM PDT 24
Peak memory 198548 kb
Host smart-7c99190c-5405-44f9-81c1-f504e8d4cff0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828890337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3828890337
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3806515847
Short name T559
Test name
Test status
Simulation time 215581410 ps
CPU time 0.77 seconds
Started Aug 08 05:12:10 PM PDT 24
Finished Aug 08 05:12:11 PM PDT 24
Peak memory 195912 kb
Host smart-6e90eb5d-19dc-4278-a1e8-027c57da8ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806515847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3806515847
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2922864932
Short name T356
Test name
Test status
Simulation time 42842410 ps
CPU time 1.08 seconds
Started Aug 08 05:12:22 PM PDT 24
Finished Aug 08 05:12:23 PM PDT 24
Peak memory 196532 kb
Host smart-0acfa10f-74e9-43cd-a02e-0af1593a8cb6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922864932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2922864932
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.418046771
Short name T183
Test name
Test status
Simulation time 792553797 ps
CPU time 5.57 seconds
Started Aug 08 05:12:33 PM PDT 24
Finished Aug 08 05:12:38 PM PDT 24
Peak memory 198320 kb
Host smart-edd0e949-38c5-4bce-8d9c-bdbccb0d99a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418046771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.418046771
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2622566042
Short name T45
Test name
Test status
Simulation time 295463902 ps
CPU time 1.01 seconds
Started Aug 08 05:12:32 PM PDT 24
Finished Aug 08 05:12:34 PM PDT 24
Peak memory 215456 kb
Host smart-23f4a4fb-2200-4de6-b54f-cf69c63a4115
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622566042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2622566042
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3458624891
Short name T346
Test name
Test status
Simulation time 50000167 ps
CPU time 1.02 seconds
Started Aug 08 05:12:15 PM PDT 24
Finished Aug 08 05:12:17 PM PDT 24
Peak memory 196184 kb
Host smart-12cc7337-745d-47a0-b8e6-7f0d9f6d1ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458624891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3458624891
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.164532664
Short name T380
Test name
Test status
Simulation time 364474806 ps
CPU time 0.81 seconds
Started Aug 08 05:12:20 PM PDT 24
Finished Aug 08 05:12:21 PM PDT 24
Peak memory 195800 kb
Host smart-9e1b9349-15f6-4e35-bb85-3d73acbd10b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164532664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.164532664
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.620913472
Short name T241
Test name
Test status
Simulation time 5225595566 ps
CPU time 111.56 seconds
Started Aug 08 05:12:16 PM PDT 24
Finished Aug 08 05:14:08 PM PDT 24
Peak memory 198732 kb
Host smart-547fe9e9-1366-4f8f-ac46-c8e39eae6a3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620913472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.620913472
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2948299194
Short name T136
Test name
Test status
Simulation time 80118938 ps
CPU time 0.56 seconds
Started Aug 08 05:13:27 PM PDT 24
Finished Aug 08 05:13:28 PM PDT 24
Peak memory 195108 kb
Host smart-485b8f08-cf3a-469f-a75c-6569049ce8c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948299194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2948299194
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.37408800
Short name T418
Test name
Test status
Simulation time 33620309 ps
CPU time 0.8 seconds
Started Aug 08 05:13:22 PM PDT 24
Finished Aug 08 05:13:23 PM PDT 24
Peak memory 196388 kb
Host smart-df59c6c8-dc6b-41d4-8fe4-e69b6eb09ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37408800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.37408800
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2522424472
Short name T207
Test name
Test status
Simulation time 495420978 ps
CPU time 4.05 seconds
Started Aug 08 05:13:34 PM PDT 24
Finished Aug 08 05:13:39 PM PDT 24
Peak memory 197168 kb
Host smart-626ce18b-b566-477e-93a2-04d57b15a270
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522424472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2522424472
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.578125505
Short name T650
Test name
Test status
Simulation time 51144416 ps
CPU time 0.65 seconds
Started Aug 08 05:13:26 PM PDT 24
Finished Aug 08 05:13:27 PM PDT 24
Peak memory 195788 kb
Host smart-6a34684d-d8fd-4d24-bfd2-f3a1c79c9772
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578125505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.578125505
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2068060761
Short name T503
Test name
Test status
Simulation time 102335567 ps
CPU time 1.43 seconds
Started Aug 08 05:13:28 PM PDT 24
Finished Aug 08 05:13:30 PM PDT 24
Peak memory 197504 kb
Host smart-6b296da2-b409-4d0f-9db8-5eae6f34b72b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068060761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2068060761
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.436025449
Short name T249
Test name
Test status
Simulation time 54985782 ps
CPU time 2.18 seconds
Started Aug 08 05:13:34 PM PDT 24
Finished Aug 08 05:13:36 PM PDT 24
Peak memory 198452 kb
Host smart-28d35a89-603d-473c-8a01-c9aa1b230adb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436025449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.436025449
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2456055053
Short name T649
Test name
Test status
Simulation time 71770022 ps
CPU time 1.62 seconds
Started Aug 08 05:13:25 PM PDT 24
Finished Aug 08 05:13:27 PM PDT 24
Peak memory 197260 kb
Host smart-32f7cfe5-fa59-4ad5-a29c-69f56426b4b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456055053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2456055053
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3141130606
Short name T458
Test name
Test status
Simulation time 83252294 ps
CPU time 0.76 seconds
Started Aug 08 05:13:25 PM PDT 24
Finished Aug 08 05:13:25 PM PDT 24
Peak memory 195840 kb
Host smart-43a7cf90-6b89-4c24-9de9-92b25e5624fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141130606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3141130606
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2162859332
Short name T135
Test name
Test status
Simulation time 283086562 ps
CPU time 1.3 seconds
Started Aug 08 05:13:27 PM PDT 24
Finished Aug 08 05:13:29 PM PDT 24
Peak memory 197488 kb
Host smart-3564ff48-4e00-40c8-8143-611419b35e85
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162859332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2162859332
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3803449263
Short name T600
Test name
Test status
Simulation time 536017544 ps
CPU time 1.58 seconds
Started Aug 08 05:13:28 PM PDT 24
Finished Aug 08 05:13:30 PM PDT 24
Peak memory 198508 kb
Host smart-fb96018d-8d3d-4733-bd24-33e3b3e9348e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803449263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3803449263
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.136175177
Short name T271
Test name
Test status
Simulation time 80171949 ps
CPU time 0.81 seconds
Started Aug 08 05:13:27 PM PDT 24
Finished Aug 08 05:13:28 PM PDT 24
Peak memory 194756 kb
Host smart-8a3773a4-be39-4958-9155-5e65482b6957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136175177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.136175177
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.4001750835
Short name T350
Test name
Test status
Simulation time 47632713 ps
CPU time 1.1 seconds
Started Aug 08 05:13:25 PM PDT 24
Finished Aug 08 05:13:26 PM PDT 24
Peak memory 196236 kb
Host smart-16618a23-27bf-422f-ae73-044be4683b4c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001750835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.4001750835
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.2984543561
Short name T426
Test name
Test status
Simulation time 19972588542 ps
CPU time 117.31 seconds
Started Aug 08 05:13:29 PM PDT 24
Finished Aug 08 05:15:27 PM PDT 24
Peak memory 198568 kb
Host smart-d1e53a61-3024-4f63-bb69-7bd80d4127fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984543561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.2984543561
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2502071758
Short name T188
Test name
Test status
Simulation time 41191750 ps
CPU time 0.57 seconds
Started Aug 08 05:13:26 PM PDT 24
Finished Aug 08 05:13:27 PM PDT 24
Peak memory 194408 kb
Host smart-195ea6c4-5e86-45fc-85b1-127c1d643057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502071758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2502071758
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3588882770
Short name T434
Test name
Test status
Simulation time 40290297 ps
CPU time 0.82 seconds
Started Aug 08 05:13:30 PM PDT 24
Finished Aug 08 05:13:31 PM PDT 24
Peak memory 196232 kb
Host smart-cf69e8ad-d89b-41cf-9c9b-b572d6e4ba69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588882770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3588882770
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.995926328
Short name T646
Test name
Test status
Simulation time 169531574 ps
CPU time 4.67 seconds
Started Aug 08 05:13:51 PM PDT 24
Finished Aug 08 05:13:55 PM PDT 24
Peak memory 196008 kb
Host smart-32df7418-8172-4a4f-8c96-dfea03f72cd4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995926328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.995926328
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3433137054
Short name T381
Test name
Test status
Simulation time 90364788 ps
CPU time 1 seconds
Started Aug 08 05:13:48 PM PDT 24
Finished Aug 08 05:13:49 PM PDT 24
Peak memory 196964 kb
Host smart-b6b1f7f2-e595-4adb-b35b-d762e5db392b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433137054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3433137054
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2031845814
Short name T585
Test name
Test status
Simulation time 176152399 ps
CPU time 1.25 seconds
Started Aug 08 05:13:34 PM PDT 24
Finished Aug 08 05:13:35 PM PDT 24
Peak memory 197580 kb
Host smart-d3e6e7b2-a94e-4118-9553-07523c8aacb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031845814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2031845814
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1240883885
Short name T104
Test name
Test status
Simulation time 166480381 ps
CPU time 3.25 seconds
Started Aug 08 05:13:35 PM PDT 24
Finished Aug 08 05:13:39 PM PDT 24
Peak memory 198568 kb
Host smart-df6ab2d8-0832-4bf4-a670-b3aab7b10540
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240883885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1240883885
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.1635105343
Short name T277
Test name
Test status
Simulation time 120338694 ps
CPU time 2.66 seconds
Started Aug 08 05:13:34 PM PDT 24
Finished Aug 08 05:13:37 PM PDT 24
Peak memory 197660 kb
Host smart-a5041d6e-3dfb-4e79-a14e-356fa0b3064e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635105343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.1635105343
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1407103518
Short name T421
Test name
Test status
Simulation time 391162629 ps
CPU time 1.16 seconds
Started Aug 08 05:13:26 PM PDT 24
Finished Aug 08 05:13:27 PM PDT 24
Peak memory 196624 kb
Host smart-15cfef4c-3e2d-4fd0-ae91-b3aaba966e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407103518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1407103518
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.355513633
Short name T676
Test name
Test status
Simulation time 33392181 ps
CPU time 0.87 seconds
Started Aug 08 05:13:34 PM PDT 24
Finished Aug 08 05:13:35 PM PDT 24
Peak memory 196728 kb
Host smart-aa5b3f47-cba4-42dc-ac8e-dac7c9aee935
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355513633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.355513633
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1625250084
Short name T699
Test name
Test status
Simulation time 322495246 ps
CPU time 5.18 seconds
Started Aug 08 05:13:31 PM PDT 24
Finished Aug 08 05:13:37 PM PDT 24
Peak memory 198420 kb
Host smart-e9e00a21-7311-49e5-882a-db75a7d9ee5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625250084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1625250084
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.282396024
Short name T496
Test name
Test status
Simulation time 60967312 ps
CPU time 1.21 seconds
Started Aug 08 05:13:43 PM PDT 24
Finished Aug 08 05:13:45 PM PDT 24
Peak memory 197132 kb
Host smart-e8a3e2ad-f2e4-43a8-975c-81e51b402c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282396024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.282396024
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3878564401
Short name T138
Test name
Test status
Simulation time 77765324 ps
CPU time 1.26 seconds
Started Aug 08 05:13:44 PM PDT 24
Finished Aug 08 05:13:45 PM PDT 24
Peak memory 196332 kb
Host smart-b6be35e8-5509-4e62-8c07-a6b13e1a9665
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878564401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3878564401
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3185636860
Short name T320
Test name
Test status
Simulation time 25851892603 ps
CPU time 78.72 seconds
Started Aug 08 05:13:41 PM PDT 24
Finished Aug 08 05:15:00 PM PDT 24
Peak memory 198684 kb
Host smart-8c5e9a79-3a88-4166-8a6e-7eb67ad0e25f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185636860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3185636860
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2420275472
Short name T673
Test name
Test status
Simulation time 15887824 ps
CPU time 0.6 seconds
Started Aug 08 05:13:39 PM PDT 24
Finished Aug 08 05:13:40 PM PDT 24
Peak memory 194660 kb
Host smart-101ee54f-959f-4001-9325-617a85f0dfb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420275472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2420275472
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1691256235
Short name T223
Test name
Test status
Simulation time 27196728 ps
CPU time 0.79 seconds
Started Aug 08 05:13:32 PM PDT 24
Finished Aug 08 05:13:33 PM PDT 24
Peak memory 195292 kb
Host smart-1918e457-1303-4326-bbd1-2a5e43a83891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691256235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1691256235
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2621293275
Short name T546
Test name
Test status
Simulation time 3399322168 ps
CPU time 23.17 seconds
Started Aug 08 05:13:34 PM PDT 24
Finished Aug 08 05:13:57 PM PDT 24
Peak memory 197620 kb
Host smart-2c9b0203-a95b-4da0-b663-c2fd88121cf1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621293275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2621293275
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3422545668
Short name T295
Test name
Test status
Simulation time 140070306 ps
CPU time 0.63 seconds
Started Aug 08 05:13:36 PM PDT 24
Finished Aug 08 05:13:36 PM PDT 24
Peak memory 194888 kb
Host smart-ce4ff80e-c0e3-4f16-a107-e9be32dcdcd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422545668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3422545668
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1245692662
Short name T251
Test name
Test status
Simulation time 197540918 ps
CPU time 0.72 seconds
Started Aug 08 05:13:36 PM PDT 24
Finished Aug 08 05:13:37 PM PDT 24
Peak memory 196784 kb
Host smart-865832d0-4897-4dfa-97fa-e906d41ac1b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245692662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1245692662
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.885535351
Short name T397
Test name
Test status
Simulation time 498590235 ps
CPU time 3.54 seconds
Started Aug 08 05:13:27 PM PDT 24
Finished Aug 08 05:13:31 PM PDT 24
Peak memory 198632 kb
Host smart-bf7b3648-2bfe-4f60-a820-9edcae6c3799
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885535351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.885535351
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2626798704
Short name T653
Test name
Test status
Simulation time 118526722 ps
CPU time 3.7 seconds
Started Aug 08 05:13:35 PM PDT 24
Finished Aug 08 05:13:39 PM PDT 24
Peak memory 196392 kb
Host smart-bff3d2b5-906b-410a-9038-e7c575b92496
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626798704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2626798704
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2293965472
Short name T253
Test name
Test status
Simulation time 25711326 ps
CPU time 0.65 seconds
Started Aug 08 05:13:24 PM PDT 24
Finished Aug 08 05:13:25 PM PDT 24
Peak memory 195404 kb
Host smart-90233887-b613-42b9-9628-1eafe260c4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293965472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2293965472
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.297099200
Short name T351
Test name
Test status
Simulation time 112743596 ps
CPU time 1.37 seconds
Started Aug 08 05:13:27 PM PDT 24
Finished Aug 08 05:13:29 PM PDT 24
Peak memory 197436 kb
Host smart-de4ee823-3384-4512-a17f-e25a58554870
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297099200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.297099200
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1466031429
Short name T383
Test name
Test status
Simulation time 198182533 ps
CPU time 2.12 seconds
Started Aug 08 05:13:31 PM PDT 24
Finished Aug 08 05:13:33 PM PDT 24
Peak memory 198472 kb
Host smart-ce260e9f-8047-4ee5-bb12-553927254ec6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466031429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1466031429
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3575811237
Short name T294
Test name
Test status
Simulation time 121753046 ps
CPU time 1.28 seconds
Started Aug 08 05:13:47 PM PDT 24
Finished Aug 08 05:13:49 PM PDT 24
Peak memory 197444 kb
Host smart-3feb6e40-c329-461c-a8f1-a0b410ed7a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575811237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3575811237
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.317373890
Short name T177
Test name
Test status
Simulation time 44530051 ps
CPU time 1.29 seconds
Started Aug 08 05:13:26 PM PDT 24
Finished Aug 08 05:13:28 PM PDT 24
Peak memory 197236 kb
Host smart-02fd996c-22b0-4405-b333-f10e10baa904
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317373890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.317373890
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3623509595
Short name T150
Test name
Test status
Simulation time 193574922893 ps
CPU time 212.24 seconds
Started Aug 08 05:13:27 PM PDT 24
Finished Aug 08 05:17:00 PM PDT 24
Peak memory 198652 kb
Host smart-47e11e99-2479-42e0-b574-ac0ef2a52b50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623509595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3623509595
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2211856231
Short name T178
Test name
Test status
Simulation time 27062572 ps
CPU time 0.58 seconds
Started Aug 08 05:13:28 PM PDT 24
Finished Aug 08 05:13:29 PM PDT 24
Peak memory 194448 kb
Host smart-408c0a33-87c5-43e3-9e27-94cf7ac0d995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211856231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2211856231
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2517723622
Short name T492
Test name
Test status
Simulation time 49889655 ps
CPU time 0.94 seconds
Started Aug 08 05:13:47 PM PDT 24
Finished Aug 08 05:13:48 PM PDT 24
Peak memory 196804 kb
Host smart-6158beb0-83f3-4ca5-b4b6-0d942a223009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517723622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2517723622
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3609126349
Short name T599
Test name
Test status
Simulation time 660989912 ps
CPU time 18.65 seconds
Started Aug 08 05:13:35 PM PDT 24
Finished Aug 08 05:13:53 PM PDT 24
Peak memory 196020 kb
Host smart-63b20a57-5493-4cf0-8bf1-dd8f1d8125ef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609126349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3609126349
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2493767459
Short name T499
Test name
Test status
Simulation time 42754745 ps
CPU time 0.64 seconds
Started Aug 08 05:13:26 PM PDT 24
Finished Aug 08 05:13:26 PM PDT 24
Peak memory 194844 kb
Host smart-4549bd98-4667-4430-b242-de95b292a530
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493767459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2493767459
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.4186460714
Short name T182
Test name
Test status
Simulation time 76605218 ps
CPU time 0.71 seconds
Started Aug 08 05:13:25 PM PDT 24
Finished Aug 08 05:13:25 PM PDT 24
Peak memory 195532 kb
Host smart-2fa68d69-97c8-411c-8be6-b46a86e7c2b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186460714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.4186460714
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.4096885699
Short name T664
Test name
Test status
Simulation time 49637848 ps
CPU time 1.94 seconds
Started Aug 08 05:13:33 PM PDT 24
Finished Aug 08 05:13:35 PM PDT 24
Peak memory 198692 kb
Host smart-99b40e61-517e-4e75-adcc-8608d8e041cd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096885699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.4096885699
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.1948510680
Short name T362
Test name
Test status
Simulation time 106609036 ps
CPU time 2.26 seconds
Started Aug 08 05:13:34 PM PDT 24
Finished Aug 08 05:13:37 PM PDT 24
Peak memory 198580 kb
Host smart-65049427-1be1-4646-9f1c-517ec31cc141
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948510680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.1948510680
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.4223826403
Short name T99
Test name
Test status
Simulation time 53334046 ps
CPU time 1.17 seconds
Started Aug 08 05:13:48 PM PDT 24
Finished Aug 08 05:13:49 PM PDT 24
Peak memory 196600 kb
Host smart-d124ffdd-cda5-462d-b466-553cdf90afee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223826403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.4223826403
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3407641429
Short name T125
Test name
Test status
Simulation time 127090877 ps
CPU time 1.29 seconds
Started Aug 08 05:13:44 PM PDT 24
Finished Aug 08 05:13:46 PM PDT 24
Peak memory 198500 kb
Host smart-afdbcfc3-ea2c-4c60-80a5-229c12d6b84a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407641429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3407641429
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1308086653
Short name T367
Test name
Test status
Simulation time 2758273460 ps
CPU time 5.13 seconds
Started Aug 08 05:13:51 PM PDT 24
Finished Aug 08 05:13:56 PM PDT 24
Peak memory 198684 kb
Host smart-5794469e-1bc9-4553-b7ae-580a3a4c68f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308086653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1308086653
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.369710996
Short name T114
Test name
Test status
Simulation time 78124610 ps
CPU time 1.23 seconds
Started Aug 08 05:13:37 PM PDT 24
Finished Aug 08 05:13:39 PM PDT 24
Peak memory 196052 kb
Host smart-ade5a91c-a484-49c7-a24b-5cc4fac480b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369710996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.369710996
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1266469583
Short name T340
Test name
Test status
Simulation time 1231846866 ps
CPU time 1.13 seconds
Started Aug 08 05:13:34 PM PDT 24
Finished Aug 08 05:13:35 PM PDT 24
Peak memory 196136 kb
Host smart-c0b1101f-1a3b-47c5-b9ca-12895a8fa500
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266469583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1266469583
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.296202874
Short name T394
Test name
Test status
Simulation time 8838291635 ps
CPU time 59.14 seconds
Started Aug 08 05:13:33 PM PDT 24
Finished Aug 08 05:14:32 PM PDT 24
Peak memory 198660 kb
Host smart-6e375164-86e3-45b8-b7e5-f5974a8f0007
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296202874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.296202874
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.2933327259
Short name T666
Test name
Test status
Simulation time 681874267211 ps
CPU time 1648.31 seconds
Started Aug 08 05:13:31 PM PDT 24
Finished Aug 08 05:40:59 PM PDT 24
Peak memory 206988 kb
Host smart-5f6afe7c-7706-4082-8eaf-2a8214fb1064
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2933327259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.2933327259
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.4176206543
Short name T570
Test name
Test status
Simulation time 15925801 ps
CPU time 0.62 seconds
Started Aug 08 05:13:32 PM PDT 24
Finished Aug 08 05:13:33 PM PDT 24
Peak memory 194624 kb
Host smart-1022b8f7-0040-463b-a903-2ad6952dcdf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176206543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.4176206543
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2530599120
Short name T233
Test name
Test status
Simulation time 14474238 ps
CPU time 0.62 seconds
Started Aug 08 05:13:27 PM PDT 24
Finished Aug 08 05:13:28 PM PDT 24
Peak memory 194964 kb
Host smart-ad902cda-25b3-440d-bf50-ee01e4d4b19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530599120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2530599120
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1012729214
Short name T436
Test name
Test status
Simulation time 518775885 ps
CPU time 27.48 seconds
Started Aug 08 05:13:36 PM PDT 24
Finished Aug 08 05:14:04 PM PDT 24
Peak memory 197292 kb
Host smart-27038688-aa3f-42b8-a842-6b0ac1b2f2fc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012729214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1012729214
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1630905753
Short name T677
Test name
Test status
Simulation time 143047761 ps
CPU time 1.05 seconds
Started Aug 08 05:13:47 PM PDT 24
Finished Aug 08 05:13:49 PM PDT 24
Peak memory 197148 kb
Host smart-fd13b7d3-c280-4cbc-84ce-f15ea9669128
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630905753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1630905753
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.49101489
Short name T143
Test name
Test status
Simulation time 76513912 ps
CPU time 0.66 seconds
Started Aug 08 05:13:41 PM PDT 24
Finished Aug 08 05:13:42 PM PDT 24
Peak memory 194816 kb
Host smart-c6ecad02-25ff-4a3e-aadb-71f16d1823ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49101489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.49101489
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3149827821
Short name T204
Test name
Test status
Simulation time 124615994 ps
CPU time 2.73 seconds
Started Aug 08 05:13:41 PM PDT 24
Finished Aug 08 05:13:44 PM PDT 24
Peak memory 198524 kb
Host smart-c50993b5-88eb-4e4b-bff8-c2082b8adf64
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149827821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3149827821
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1091115278
Short name T487
Test name
Test status
Simulation time 89377742 ps
CPU time 2.68 seconds
Started Aug 08 05:13:27 PM PDT 24
Finished Aug 08 05:13:30 PM PDT 24
Peak memory 198596 kb
Host smart-546cfeb1-d00e-4747-a132-4ca9c33c5a2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091115278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1091115278
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1082532722
Short name T566
Test name
Test status
Simulation time 34149286 ps
CPU time 1.13 seconds
Started Aug 08 05:13:53 PM PDT 24
Finished Aug 08 05:13:54 PM PDT 24
Peak memory 198656 kb
Host smart-02295ecc-a92a-43da-954f-c9455b3aef6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082532722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1082532722
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.843289890
Short name T439
Test name
Test status
Simulation time 38471527 ps
CPU time 0.89 seconds
Started Aug 08 05:13:27 PM PDT 24
Finished Aug 08 05:13:28 PM PDT 24
Peak memory 197716 kb
Host smart-c76804fe-9b47-4778-9779-161a584df5cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843289890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.843289890
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1975243779
Short name T683
Test name
Test status
Simulation time 1421015025 ps
CPU time 4.09 seconds
Started Aug 08 05:13:34 PM PDT 24
Finished Aug 08 05:13:38 PM PDT 24
Peak memory 198408 kb
Host smart-3de8b293-5a74-4351-b62d-cc133bbb5b04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975243779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1975243779
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3120782294
Short name T134
Test name
Test status
Simulation time 170515006 ps
CPU time 1.47 seconds
Started Aug 08 05:13:44 PM PDT 24
Finished Aug 08 05:13:46 PM PDT 24
Peak memory 196720 kb
Host smart-ece06f74-d121-4ff3-86aa-209e4524d739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120782294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3120782294
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.4282581934
Short name T429
Test name
Test status
Simulation time 202411116 ps
CPU time 1.21 seconds
Started Aug 08 05:13:31 PM PDT 24
Finished Aug 08 05:13:32 PM PDT 24
Peak memory 196296 kb
Host smart-2113b5b5-54be-4720-b5b0-ce065dbc0512
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282581934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.4282581934
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2183693252
Short name T513
Test name
Test status
Simulation time 427676526518 ps
CPU time 255.22 seconds
Started Aug 08 05:13:28 PM PDT 24
Finished Aug 08 05:17:44 PM PDT 24
Peak memory 198680 kb
Host smart-93b8a345-ab1a-46a9-bdeb-98d36c2edab1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183693252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2183693252
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3293386347
Short name T21
Test name
Test status
Simulation time 17071149 ps
CPU time 0.6 seconds
Started Aug 08 05:13:28 PM PDT 24
Finished Aug 08 05:13:29 PM PDT 24
Peak memory 195252 kb
Host smart-dd33cd3f-29a4-473d-aec0-0346676c0bdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293386347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3293386347
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.282971618
Short name T184
Test name
Test status
Simulation time 46551464 ps
CPU time 0.87 seconds
Started Aug 08 05:13:40 PM PDT 24
Finished Aug 08 05:13:41 PM PDT 24
Peak memory 197204 kb
Host smart-467f03c9-4631-4837-b593-6f2d71778af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282971618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.282971618
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3338319148
Short name T457
Test name
Test status
Simulation time 146914124 ps
CPU time 5.12 seconds
Started Aug 08 05:13:44 PM PDT 24
Finished Aug 08 05:13:49 PM PDT 24
Peak memory 197560 kb
Host smart-71563811-776f-427e-be30-f94f4ae40143
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338319148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3338319148
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.259235237
Short name T433
Test name
Test status
Simulation time 42611543 ps
CPU time 0.8 seconds
Started Aug 08 05:13:25 PM PDT 24
Finished Aug 08 05:13:26 PM PDT 24
Peak memory 196356 kb
Host smart-48d048ce-0609-4946-9df6-87e65b8cc5f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259235237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.259235237
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.4137846690
Short name T144
Test name
Test status
Simulation time 24998793 ps
CPU time 0.7 seconds
Started Aug 08 05:13:27 PM PDT 24
Finished Aug 08 05:13:28 PM PDT 24
Peak memory 194856 kb
Host smart-1f52f6bd-edd5-41d2-8a0f-2a0077077b7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137846690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.4137846690
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1852463923
Short name T281
Test name
Test status
Simulation time 117720456 ps
CPU time 2.5 seconds
Started Aug 08 05:13:47 PM PDT 24
Finished Aug 08 05:13:49 PM PDT 24
Peak memory 198584 kb
Host smart-93d8b422-7332-4252-a89c-48da3a7bbec4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852463923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1852463923
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.522072014
Short name T679
Test name
Test status
Simulation time 65074489 ps
CPU time 2 seconds
Started Aug 08 05:13:29 PM PDT 24
Finished Aug 08 05:13:31 PM PDT 24
Peak memory 198516 kb
Host smart-c7752a8b-5dcf-49cf-ab84-e42318853075
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522072014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
522072014
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2161212859
Short name T590
Test name
Test status
Simulation time 103571258 ps
CPU time 0.99 seconds
Started Aug 08 05:13:45 PM PDT 24
Finished Aug 08 05:13:46 PM PDT 24
Peak memory 197260 kb
Host smart-f52c1396-d508-420a-b67a-4a8381383c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161212859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2161212859
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1478241840
Short name T318
Test name
Test status
Simulation time 26094055 ps
CPU time 0.67 seconds
Started Aug 08 05:13:32 PM PDT 24
Finished Aug 08 05:13:32 PM PDT 24
Peak memory 195332 kb
Host smart-5c570f85-8c93-482c-89eb-c505b48958d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478241840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1478241840
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2379961664
Short name T613
Test name
Test status
Simulation time 303729073 ps
CPU time 2.6 seconds
Started Aug 08 05:13:41 PM PDT 24
Finished Aug 08 05:13:44 PM PDT 24
Peak memory 197688 kb
Host smart-ea1be538-7f72-462c-8caa-2c99a21bede0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379961664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2379961664
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1397706134
Short name T569
Test name
Test status
Simulation time 223891408 ps
CPU time 1.05 seconds
Started Aug 08 05:13:46 PM PDT 24
Finished Aug 08 05:13:48 PM PDT 24
Peak memory 196772 kb
Host smart-768518e0-4ade-47b0-8e7c-c8071d27cd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397706134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1397706134
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2201691246
Short name T247
Test name
Test status
Simulation time 353586599 ps
CPU time 1.46 seconds
Started Aug 08 05:13:27 PM PDT 24
Finished Aug 08 05:13:29 PM PDT 24
Peak memory 198512 kb
Host smart-c7eace4d-a823-43a7-88af-d875f01a4678
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201691246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2201691246
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.3098641087
Short name T373
Test name
Test status
Simulation time 13922433289 ps
CPU time 200.41 seconds
Started Aug 08 05:13:32 PM PDT 24
Finished Aug 08 05:16:53 PM PDT 24
Peak memory 198704 kb
Host smart-bfb2dabb-a219-4fa3-8ce4-3a5c3bd49d70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098641087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.3098641087
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.2879243083
Short name T26
Test name
Test status
Simulation time 193522576581 ps
CPU time 1524.48 seconds
Started Aug 08 05:13:30 PM PDT 24
Finished Aug 08 05:38:54 PM PDT 24
Peak memory 198864 kb
Host smart-322d228c-8249-485a-a1c1-a5efeeac3f22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2879243083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.2879243083
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2056688363
Short name T674
Test name
Test status
Simulation time 33658510 ps
CPU time 0.58 seconds
Started Aug 08 05:13:32 PM PDT 24
Finished Aug 08 05:13:33 PM PDT 24
Peak memory 195136 kb
Host smart-56cf7a49-af5b-442f-b4ee-e35f828b57f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056688363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2056688363
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1759092
Short name T16
Test name
Test status
Simulation time 135356872 ps
CPU time 0.93 seconds
Started Aug 08 05:13:45 PM PDT 24
Finished Aug 08 05:13:47 PM PDT 24
Peak memory 196552 kb
Host smart-3a4e1d90-9456-4474-8554-3d01d928648f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1759092
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1483032154
Short name T678
Test name
Test status
Simulation time 1293587891 ps
CPU time 16.44 seconds
Started Aug 08 05:13:47 PM PDT 24
Finished Aug 08 05:14:03 PM PDT 24
Peak memory 197336 kb
Host smart-15e2f184-8946-4493-8d2e-0036acdfd31d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483032154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1483032154
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2234442118
Short name T453
Test name
Test status
Simulation time 76913151 ps
CPU time 0.99 seconds
Started Aug 08 05:13:43 PM PDT 24
Finished Aug 08 05:13:44 PM PDT 24
Peak memory 197708 kb
Host smart-ac719c58-356a-4618-84d5-89f3e767e2a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234442118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2234442118
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.1766432435
Short name T464
Test name
Test status
Simulation time 161266685 ps
CPU time 0.97 seconds
Started Aug 08 05:13:38 PM PDT 24
Finished Aug 08 05:13:39 PM PDT 24
Peak memory 196528 kb
Host smart-d37bd675-e0a3-4a22-89ad-d3c70d9ce6eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766432435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.1766432435
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1474442544
Short name T627
Test name
Test status
Simulation time 225201889 ps
CPU time 2.66 seconds
Started Aug 08 05:13:34 PM PDT 24
Finished Aug 08 05:13:37 PM PDT 24
Peak memory 198676 kb
Host smart-0670f1af-ce10-4dbb-8958-db37539371f1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474442544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1474442544
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2283172027
Short name T405
Test name
Test status
Simulation time 120075157 ps
CPU time 0.89 seconds
Started Aug 08 05:13:31 PM PDT 24
Finished Aug 08 05:13:32 PM PDT 24
Peak memory 194908 kb
Host smart-d5d6c2d8-de30-400e-89bb-085da5c51bcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283172027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2283172027
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1377238839
Short name T66
Test name
Test status
Simulation time 199691760 ps
CPU time 1.16 seconds
Started Aug 08 05:13:52 PM PDT 24
Finished Aug 08 05:13:53 PM PDT 24
Peak memory 196604 kb
Host smart-f2a8b25a-69ae-43c7-9f7d-4e1a43e572f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377238839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1377238839
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.795268943
Short name T654
Test name
Test status
Simulation time 19733679 ps
CPU time 0.69 seconds
Started Aug 08 05:13:27 PM PDT 24
Finished Aug 08 05:13:28 PM PDT 24
Peak memory 195460 kb
Host smart-1692d8a5-dae0-4666-bb9e-c4bf6a497122
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795268943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup
_pulldown.795268943
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1431287750
Short name T456
Test name
Test status
Simulation time 338735521 ps
CPU time 2.92 seconds
Started Aug 08 05:13:34 PM PDT 24
Finished Aug 08 05:13:37 PM PDT 24
Peak memory 198440 kb
Host smart-39f530d2-2abf-4ce1-8c27-bf29b5d9e17e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431287750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1431287750
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.342833859
Short name T489
Test name
Test status
Simulation time 270932368 ps
CPU time 1.23 seconds
Started Aug 08 05:13:33 PM PDT 24
Finished Aug 08 05:13:35 PM PDT 24
Peak memory 197060 kb
Host smart-313e275e-870b-4518-9935-1b839f14340c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342833859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.342833859
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1396578887
Short name T212
Test name
Test status
Simulation time 47146932 ps
CPU time 1.21 seconds
Started Aug 08 05:13:28 PM PDT 24
Finished Aug 08 05:13:30 PM PDT 24
Peak memory 197112 kb
Host smart-667f336c-a38c-4341-b024-bcbd1c5864d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396578887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1396578887
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.764370076
Short name T217
Test name
Test status
Simulation time 21144626539 ps
CPU time 71.11 seconds
Started Aug 08 05:13:44 PM PDT 24
Finished Aug 08 05:14:55 PM PDT 24
Peak memory 198620 kb
Host smart-2c055e6f-5b70-49a4-85db-af5d8c681603
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764370076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.764370076
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1586726614
Short name T268
Test name
Test status
Simulation time 25335624 ps
CPU time 0.63 seconds
Started Aug 08 05:13:44 PM PDT 24
Finished Aug 08 05:13:44 PM PDT 24
Peak memory 194676 kb
Host smart-ce92e758-01a3-4abc-bb3f-68e1badc3548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586726614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1586726614
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1298647707
Short name T578
Test name
Test status
Simulation time 43383853 ps
CPU time 0.87 seconds
Started Aug 08 05:13:45 PM PDT 24
Finished Aug 08 05:13:46 PM PDT 24
Peak memory 197040 kb
Host smart-e91ee8f7-6c5a-4358-ab2e-e23ccf979254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298647707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1298647707
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.44862366
Short name T551
Test name
Test status
Simulation time 136901421 ps
CPU time 6.61 seconds
Started Aug 08 05:13:49 PM PDT 24
Finished Aug 08 05:13:56 PM PDT 24
Peak memory 196064 kb
Host smart-a9fea6a1-3d3f-4242-b1cf-f5f43da23df7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44862366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stress
.44862366
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1557357826
Short name T534
Test name
Test status
Simulation time 118316814 ps
CPU time 1 seconds
Started Aug 08 05:13:39 PM PDT 24
Finished Aug 08 05:13:40 PM PDT 24
Peak memory 197184 kb
Host smart-86ba03ac-70b0-4494-9beb-4d2ca5cb168d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557357826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1557357826
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1715488204
Short name T272
Test name
Test status
Simulation time 822407494 ps
CPU time 1.31 seconds
Started Aug 08 05:13:37 PM PDT 24
Finished Aug 08 05:13:38 PM PDT 24
Peak memory 197204 kb
Host smart-85a32727-85fc-40c5-86ef-38b91feb5be7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715488204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1715488204
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.333996632
Short name T151
Test name
Test status
Simulation time 39429673 ps
CPU time 1.01 seconds
Started Aug 08 05:13:46 PM PDT 24
Finished Aug 08 05:13:47 PM PDT 24
Peak memory 197188 kb
Host smart-e3ec78f4-922f-4a83-a46e-e3d66da2f179
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333996632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.333996632
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.2765187641
Short name T482
Test name
Test status
Simulation time 484769179 ps
CPU time 2.2 seconds
Started Aug 08 05:13:34 PM PDT 24
Finished Aug 08 05:13:36 PM PDT 24
Peak memory 197332 kb
Host smart-e6589034-a1b9-48c2-be53-cefc58f62952
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765187641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.2765187641
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2143947064
Short name T517
Test name
Test status
Simulation time 265756707 ps
CPU time 1.23 seconds
Started Aug 08 05:13:45 PM PDT 24
Finished Aug 08 05:13:47 PM PDT 24
Peak memory 197548 kb
Host smart-6c1a187c-c0e2-402a-bb9b-950b60f26aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143947064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2143947064
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1127559250
Short name T299
Test name
Test status
Simulation time 39335235 ps
CPU time 0.98 seconds
Started Aug 08 05:13:49 PM PDT 24
Finished Aug 08 05:13:50 PM PDT 24
Peak memory 197132 kb
Host smart-5ceb54f7-f402-4273-b16f-2ff68be80c3d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127559250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1127559250
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1883733048
Short name T450
Test name
Test status
Simulation time 129965944 ps
CPU time 1.62 seconds
Started Aug 08 05:13:40 PM PDT 24
Finished Aug 08 05:13:41 PM PDT 24
Peak memory 198336 kb
Host smart-cfb5a48e-cadb-4117-b908-3b4458032662
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883733048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1883733048
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.2300834685
Short name T17
Test name
Test status
Simulation time 138595866 ps
CPU time 0.94 seconds
Started Aug 08 05:13:38 PM PDT 24
Finished Aug 08 05:13:39 PM PDT 24
Peak memory 197024 kb
Host smart-368dac92-43d3-45b5-b79d-2b0e7e1caf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300834685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2300834685
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3736291064
Short name T174
Test name
Test status
Simulation time 353794681 ps
CPU time 1.4 seconds
Started Aug 08 05:13:43 PM PDT 24
Finished Aug 08 05:13:44 PM PDT 24
Peak memory 198440 kb
Host smart-b66fb5a5-318f-461c-b768-3588249eb479
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736291064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3736291064
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.802499875
Short name T477
Test name
Test status
Simulation time 29523326325 ps
CPU time 216.86 seconds
Started Aug 08 05:14:00 PM PDT 24
Finished Aug 08 05:17:37 PM PDT 24
Peak memory 198680 kb
Host smart-91da0ae9-1d2e-444a-a621-ab443b6c0b2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802499875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.802499875
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.1668859062
Short name T24
Test name
Test status
Simulation time 79245944409 ps
CPU time 548.37 seconds
Started Aug 08 05:13:44 PM PDT 24
Finished Aug 08 05:22:52 PM PDT 24
Peak memory 198744 kb
Host smart-75714573-c51f-41e1-8caa-42352255bf5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1668859062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.1668859062
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2778263400
Short name T238
Test name
Test status
Simulation time 12097547 ps
CPU time 0.58 seconds
Started Aug 08 05:13:35 PM PDT 24
Finished Aug 08 05:13:36 PM PDT 24
Peak memory 194300 kb
Host smart-5a7e8f8a-870b-4416-850b-d535a1f66d81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778263400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2778263400
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3962169225
Short name T119
Test name
Test status
Simulation time 13813243 ps
CPU time 0.58 seconds
Started Aug 08 05:14:01 PM PDT 24
Finished Aug 08 05:14:02 PM PDT 24
Peak memory 195056 kb
Host smart-083aa954-3b50-4eaf-adc0-53d97d0302a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962169225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3962169225
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.635052256
Short name T213
Test name
Test status
Simulation time 292940147 ps
CPU time 15.72 seconds
Started Aug 08 05:13:44 PM PDT 24
Finished Aug 08 05:14:00 PM PDT 24
Peak memory 195968 kb
Host smart-aec8455e-3d0c-42d4-8e45-f6f0044e1dc8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635052256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.635052256
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3901983928
Short name T401
Test name
Test status
Simulation time 196423144 ps
CPU time 0.76 seconds
Started Aug 08 05:13:54 PM PDT 24
Finished Aug 08 05:13:55 PM PDT 24
Peak memory 196316 kb
Host smart-bac030cb-1ac4-464a-bcac-2354eb76d14a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901983928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3901983928
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3753473521
Short name T305
Test name
Test status
Simulation time 505196904 ps
CPU time 1.26 seconds
Started Aug 08 05:13:51 PM PDT 24
Finished Aug 08 05:13:52 PM PDT 24
Peak memory 196456 kb
Host smart-d3afa475-9fe4-4cbc-afe9-b5244a3787aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753473521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3753473521
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.372440458
Short name T375
Test name
Test status
Simulation time 104088779 ps
CPU time 2.17 seconds
Started Aug 08 05:13:36 PM PDT 24
Finished Aug 08 05:13:38 PM PDT 24
Peak memory 198724 kb
Host smart-676de294-ba08-472c-af9d-1b62134b6279
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372440458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.372440458
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.611831766
Short name T672
Test name
Test status
Simulation time 294025219 ps
CPU time 1.6 seconds
Started Aug 08 05:13:49 PM PDT 24
Finished Aug 08 05:13:50 PM PDT 24
Peak memory 196340 kb
Host smart-ccec5d32-888d-4b75-816b-1d06e57e66e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611831766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
611831766
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.4059023196
Short name T366
Test name
Test status
Simulation time 44770570 ps
CPU time 1.12 seconds
Started Aug 08 05:13:31 PM PDT 24
Finished Aug 08 05:13:33 PM PDT 24
Peak memory 196988 kb
Host smart-4422686a-c6f4-4c76-b65d-6fba0aac65bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059023196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.4059023196
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1333523541
Short name T289
Test name
Test status
Simulation time 54974985 ps
CPU time 1.18 seconds
Started Aug 08 05:13:47 PM PDT 24
Finished Aug 08 05:13:49 PM PDT 24
Peak memory 196300 kb
Host smart-76708036-4e06-44f6-8510-ba5e35471c2a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333523541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.1333523541
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1689182332
Short name T97
Test name
Test status
Simulation time 137594323 ps
CPU time 2.09 seconds
Started Aug 08 05:13:50 PM PDT 24
Finished Aug 08 05:13:53 PM PDT 24
Peak memory 198544 kb
Host smart-56dd1ba1-ceaf-4b3e-a005-93a4261f81a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689182332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1689182332
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1898111922
Short name T422
Test name
Test status
Simulation time 95736789 ps
CPU time 0.78 seconds
Started Aug 08 05:13:33 PM PDT 24
Finished Aug 08 05:13:33 PM PDT 24
Peak memory 196424 kb
Host smart-802ce5a6-989b-4b95-b6fd-25f49650af3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898111922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1898111922
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2068465992
Short name T388
Test name
Test status
Simulation time 351306731 ps
CPU time 1.24 seconds
Started Aug 08 05:13:45 PM PDT 24
Finished Aug 08 05:13:47 PM PDT 24
Peak memory 197280 kb
Host smart-07ab8db4-afbb-42a2-af6f-9342c47e6573
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068465992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2068465992
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3841658588
Short name T577
Test name
Test status
Simulation time 9255519074 ps
CPU time 91.48 seconds
Started Aug 08 05:13:49 PM PDT 24
Finished Aug 08 05:15:21 PM PDT 24
Peak memory 198616 kb
Host smart-24badd2a-dbf4-47b0-9545-c6508c279493
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841658588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3841658588
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1469276435
Short name T465
Test name
Test status
Simulation time 163283907 ps
CPU time 0.53 seconds
Started Aug 08 05:13:51 PM PDT 24
Finished Aug 08 05:13:51 PM PDT 24
Peak memory 194500 kb
Host smart-a1cebb5d-8043-4e85-b65d-15abaa52900d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469276435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1469276435
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.3194798273
Short name T262
Test name
Test status
Simulation time 37253890 ps
CPU time 0.76 seconds
Started Aug 08 05:14:02 PM PDT 24
Finished Aug 08 05:14:08 PM PDT 24
Peak memory 195752 kb
Host smart-4e9d479b-c775-4b67-a56c-050831419fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194798273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.3194798273
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1871629913
Short name T641
Test name
Test status
Simulation time 443814019 ps
CPU time 3.44 seconds
Started Aug 08 05:13:35 PM PDT 24
Finished Aug 08 05:13:38 PM PDT 24
Peak memory 196000 kb
Host smart-ca35b78d-a4df-4c15-ada9-0a23251037f9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871629913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1871629913
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2672851286
Short name T685
Test name
Test status
Simulation time 1707395657 ps
CPU time 1.05 seconds
Started Aug 08 05:13:46 PM PDT 24
Finished Aug 08 05:13:47 PM PDT 24
Peak memory 196840 kb
Host smart-9a4402b2-2ead-47c0-91f1-01679d0a3ce4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672851286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2672851286
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.953323697
Short name T430
Test name
Test status
Simulation time 18636977 ps
CPU time 0.76 seconds
Started Aug 08 05:13:47 PM PDT 24
Finished Aug 08 05:13:48 PM PDT 24
Peak memory 195528 kb
Host smart-7decd145-d3e4-440f-bdd1-280b4f344937
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953323697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.953323697
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.49733917
Short name T648
Test name
Test status
Simulation time 365766254 ps
CPU time 3.74 seconds
Started Aug 08 05:13:43 PM PDT 24
Finished Aug 08 05:13:47 PM PDT 24
Peak memory 198576 kb
Host smart-96ef7e1c-315d-488b-8d3b-c70723a87f5c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49733917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.gpio_intr_with_filter_rand_intr_event.49733917
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.1649564034
Short name T400
Test name
Test status
Simulation time 54538957 ps
CPU time 1.42 seconds
Started Aug 08 05:14:04 PM PDT 24
Finished Aug 08 05:14:05 PM PDT 24
Peak memory 197000 kb
Host smart-fb6be34a-06d2-424f-a0a7-52cb4a335c40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649564034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.1649564034
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.420785919
Short name T444
Test name
Test status
Simulation time 67301635 ps
CPU time 1.12 seconds
Started Aug 08 05:13:51 PM PDT 24
Finished Aug 08 05:13:52 PM PDT 24
Peak memory 196484 kb
Host smart-056184bf-234a-4010-9e13-2c81193d6f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420785919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.420785919
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.150973484
Short name T638
Test name
Test status
Simulation time 27227508 ps
CPU time 1.05 seconds
Started Aug 08 05:13:33 PM PDT 24
Finished Aug 08 05:13:34 PM PDT 24
Peak memory 196308 kb
Host smart-ba9ac139-71c3-4528-90db-ab4d945ad27b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150973484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.150973484
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2420984341
Short name T3
Test name
Test status
Simulation time 962272574 ps
CPU time 5.27 seconds
Started Aug 08 05:13:46 PM PDT 24
Finished Aug 08 05:13:52 PM PDT 24
Peak memory 198532 kb
Host smart-15e216df-d4b0-4097-86ff-fd88d07c7158
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420984341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2420984341
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1356650770
Short name T419
Test name
Test status
Simulation time 23160386 ps
CPU time 0.74 seconds
Started Aug 08 05:13:36 PM PDT 24
Finished Aug 08 05:13:37 PM PDT 24
Peak memory 195360 kb
Host smart-312d41ed-eddd-4fe7-9769-59878e64eaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356650770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1356650770
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1772177441
Short name T288
Test name
Test status
Simulation time 431879050 ps
CPU time 1.26 seconds
Started Aug 08 05:13:46 PM PDT 24
Finished Aug 08 05:13:47 PM PDT 24
Peak memory 196028 kb
Host smart-acc71de0-0242-4254-a14c-30162142e8cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772177441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1772177441
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.754608045
Short name T198
Test name
Test status
Simulation time 4902513266 ps
CPU time 133.44 seconds
Started Aug 08 05:13:48 PM PDT 24
Finished Aug 08 05:16:01 PM PDT 24
Peak memory 198744 kb
Host smart-29d6ffad-b8e6-4d3f-a413-cdd5ae36ba0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754608045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.g
pio_stress_all.754608045
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.2556846894
Short name T57
Test name
Test status
Simulation time 496638389040 ps
CPU time 2731.38 seconds
Started Aug 08 05:13:43 PM PDT 24
Finished Aug 08 05:59:15 PM PDT 24
Peak memory 198856 kb
Host smart-9fdf209a-a766-466b-9dc4-8fc86e69a4d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2556846894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.2556846894
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1178407847
Short name T347
Test name
Test status
Simulation time 11560241 ps
CPU time 0.61 seconds
Started Aug 08 05:12:17 PM PDT 24
Finished Aug 08 05:12:17 PM PDT 24
Peak memory 195172 kb
Host smart-0af8c0e9-3c50-40a3-ad35-ccdcc0b5da89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178407847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1178407847
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2292370065
Short name T612
Test name
Test status
Simulation time 131464288 ps
CPU time 0.7 seconds
Started Aug 08 05:12:29 PM PDT 24
Finished Aug 08 05:12:30 PM PDT 24
Peak memory 194636 kb
Host smart-dfc219a7-f7b5-4897-b860-1163cc007b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292370065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2292370065
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3965684493
Short name T409
Test name
Test status
Simulation time 899325487 ps
CPU time 10.34 seconds
Started Aug 08 05:12:27 PM PDT 24
Finished Aug 08 05:12:37 PM PDT 24
Peak memory 197304 kb
Host smart-c8d97ab3-fc5b-442d-999f-7aec4da1eca0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965684493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3965684493
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1326254874
Short name T103
Test name
Test status
Simulation time 106898424 ps
CPU time 0.69 seconds
Started Aug 08 05:12:28 PM PDT 24
Finished Aug 08 05:12:29 PM PDT 24
Peak memory 195148 kb
Host smart-f79679ba-202f-4914-a99d-c2f31a21c253
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326254874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1326254874
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.2212966958
Short name T368
Test name
Test status
Simulation time 103703919 ps
CPU time 0.96 seconds
Started Aug 08 05:12:23 PM PDT 24
Finished Aug 08 05:12:24 PM PDT 24
Peak memory 196636 kb
Host smart-66b6063f-dce0-47b4-bd83-e74db6bc48cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212966958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2212966958
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.667234265
Short name T597
Test name
Test status
Simulation time 310440863 ps
CPU time 2.85 seconds
Started Aug 08 05:12:27 PM PDT 24
Finished Aug 08 05:12:30 PM PDT 24
Peak memory 198468 kb
Host smart-e022e37a-ec43-4db1-811e-9d4fd886e9b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667234265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.667234265
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.229912574
Short name T13
Test name
Test status
Simulation time 415641369 ps
CPU time 1.37 seconds
Started Aug 08 05:12:24 PM PDT 24
Finished Aug 08 05:12:26 PM PDT 24
Peak memory 197312 kb
Host smart-c5d45bd1-c11a-49d4-ba3b-97d37084e879
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229912574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.229912574
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3720917108
Short name T240
Test name
Test status
Simulation time 49672423 ps
CPU time 0.74 seconds
Started Aug 08 05:12:27 PM PDT 24
Finished Aug 08 05:12:28 PM PDT 24
Peak memory 195780 kb
Host smart-153106ac-4281-4c41-a347-befa3bea80c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720917108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3720917108
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.4245777889
Short name T640
Test name
Test status
Simulation time 39813244 ps
CPU time 0.83 seconds
Started Aug 08 05:12:14 PM PDT 24
Finished Aug 08 05:12:15 PM PDT 24
Peak memory 197180 kb
Host smart-0483d707-5616-42c7-ad96-c8cf8b3aaaab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245777889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.4245777889
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.458379677
Short name T1
Test name
Test status
Simulation time 215026018 ps
CPU time 1.77 seconds
Started Aug 08 05:12:29 PM PDT 24
Finished Aug 08 05:12:31 PM PDT 24
Peak memory 198256 kb
Host smart-6c1555f4-824a-4902-900a-88bb9f3281c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458379677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.458379677
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3751509118
Short name T591
Test name
Test status
Simulation time 63968052 ps
CPU time 0.98 seconds
Started Aug 08 05:12:18 PM PDT 24
Finished Aug 08 05:12:19 PM PDT 24
Peak memory 196144 kb
Host smart-6c191b9b-24c2-46fd-a0cd-aacd4e6d69a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751509118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3751509118
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3715776030
Short name T228
Test name
Test status
Simulation time 60537878 ps
CPU time 0.99 seconds
Started Aug 08 05:12:28 PM PDT 24
Finished Aug 08 05:12:29 PM PDT 24
Peak memory 196244 kb
Host smart-e582adb3-a6ba-458c-b46a-3c16766f547f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715776030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3715776030
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1774971054
Short name T189
Test name
Test status
Simulation time 10410486106 ps
CPU time 70.04 seconds
Started Aug 08 05:12:32 PM PDT 24
Finished Aug 08 05:13:43 PM PDT 24
Peak memory 198668 kb
Host smart-a4ca98cb-1c9d-4b89-b4d1-f02ff06f4218
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774971054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1774971054
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2340902446
Short name T583
Test name
Test status
Simulation time 29447002 ps
CPU time 0.56 seconds
Started Aug 08 05:12:26 PM PDT 24
Finished Aug 08 05:12:27 PM PDT 24
Peak memory 194340 kb
Host smart-4a922871-7e74-4ead-ba11-a9ac2847f5db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340902446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2340902446
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2680317551
Short name T379
Test name
Test status
Simulation time 38119045 ps
CPU time 0.74 seconds
Started Aug 08 05:12:30 PM PDT 24
Finished Aug 08 05:12:31 PM PDT 24
Peak memory 195476 kb
Host smart-743ba47f-f64e-49e5-8e94-fbbc19a8370b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680317551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2680317551
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.133165640
Short name T705
Test name
Test status
Simulation time 14989997617 ps
CPU time 26.55 seconds
Started Aug 08 05:12:29 PM PDT 24
Finished Aug 08 05:12:55 PM PDT 24
Peak memory 197120 kb
Host smart-ae9e0ded-e6b7-4dd1-9a77-e13c57ec1980
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133165640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.133165640
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1843402878
Short name T196
Test name
Test status
Simulation time 103533881 ps
CPU time 0.85 seconds
Started Aug 08 05:12:28 PM PDT 24
Finished Aug 08 05:12:29 PM PDT 24
Peak memory 197400 kb
Host smart-d208035f-16ff-410a-b927-56873e89445b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843402878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1843402878
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2357177164
Short name T124
Test name
Test status
Simulation time 79683298 ps
CPU time 1.12 seconds
Started Aug 08 05:12:29 PM PDT 24
Finished Aug 08 05:12:30 PM PDT 24
Peak memory 196288 kb
Host smart-9ec330c3-96f0-42e1-a111-b9a3ab9f59c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357177164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2357177164
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3018002439
Short name T329
Test name
Test status
Simulation time 156402474 ps
CPU time 1.74 seconds
Started Aug 08 05:12:25 PM PDT 24
Finished Aug 08 05:12:27 PM PDT 24
Peak memory 197636 kb
Host smart-5166b6aa-cce4-42ff-8873-acae4cff69d3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018002439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3018002439
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.883480860
Short name T586
Test name
Test status
Simulation time 157958667 ps
CPU time 2.39 seconds
Started Aug 08 05:12:32 PM PDT 24
Finished Aug 08 05:12:35 PM PDT 24
Peak memory 196300 kb
Host smart-983af2d7-0fc6-4a77-9ce9-dd1210925fad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883480860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.883480860
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.532699430
Short name T399
Test name
Test status
Simulation time 53113028 ps
CPU time 1.09 seconds
Started Aug 08 05:12:25 PM PDT 24
Finished Aug 08 05:12:26 PM PDT 24
Peak memory 196524 kb
Host smart-8753f8dd-5ca6-49ca-a4b9-7e1d251da2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532699430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.532699430
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.1563641733
Short name T157
Test name
Test status
Simulation time 40204992 ps
CPU time 0.69 seconds
Started Aug 08 05:12:25 PM PDT 24
Finished Aug 08 05:12:26 PM PDT 24
Peak memory 195824 kb
Host smart-3a8bdba1-4896-42f2-b5b7-9d7b897329e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563641733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.1563641733
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.313483734
Short name T122
Test name
Test status
Simulation time 841020093 ps
CPU time 3.76 seconds
Started Aug 08 05:12:25 PM PDT 24
Finished Aug 08 05:12:28 PM PDT 24
Peak memory 198444 kb
Host smart-af2fd286-4dad-4926-81ca-4e21da5b0a51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313483734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.313483734
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2175226236
Short name T524
Test name
Test status
Simulation time 55964847 ps
CPU time 1.03 seconds
Started Aug 08 05:12:29 PM PDT 24
Finished Aug 08 05:12:31 PM PDT 24
Peak memory 196236 kb
Host smart-f6e92330-12b6-4fc0-9a62-36a90a698f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175226236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2175226236
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3424710080
Short name T284
Test name
Test status
Simulation time 196810177 ps
CPU time 1.1 seconds
Started Aug 08 05:12:31 PM PDT 24
Finished Aug 08 05:12:33 PM PDT 24
Peak memory 196656 kb
Host smart-3fbe8b43-bd6c-4212-90bc-09ead25c0cb5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424710080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3424710080
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.228963476
Short name T304
Test name
Test status
Simulation time 11806459885 ps
CPU time 141.4 seconds
Started Aug 08 05:12:25 PM PDT 24
Finished Aug 08 05:14:46 PM PDT 24
Peak memory 198740 kb
Host smart-008f8a7b-98d4-4b56-9240-6aed02b23597
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228963476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.228963476
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.671572935
Short name T703
Test name
Test status
Simulation time 63517603581 ps
CPU time 530.1 seconds
Started Aug 08 05:12:33 PM PDT 24
Finished Aug 08 05:21:23 PM PDT 24
Peak memory 198868 kb
Host smart-cbc45b66-6bd5-42ad-a13a-28e281f8e614
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=671572935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.671572935
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1973933341
Short name T657
Test name
Test status
Simulation time 12902478 ps
CPU time 0.59 seconds
Started Aug 08 05:12:33 PM PDT 24
Finished Aug 08 05:12:34 PM PDT 24
Peak memory 194656 kb
Host smart-04308283-3782-435a-8062-da9cdf7db761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973933341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1973933341
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.194095028
Short name T539
Test name
Test status
Simulation time 288202260 ps
CPU time 0.99 seconds
Started Aug 08 05:12:25 PM PDT 24
Finished Aug 08 05:12:26 PM PDT 24
Peak memory 196408 kb
Host smart-9a3cb8bd-8402-4b1e-93c1-a5051d8d8051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194095028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.194095028
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.76629099
Short name T387
Test name
Test status
Simulation time 6621985153 ps
CPU time 16.46 seconds
Started Aug 08 05:12:15 PM PDT 24
Finished Aug 08 05:12:32 PM PDT 24
Peak memory 197216 kb
Host smart-1e81732c-95bc-4a6e-898c-f180d5a66d06
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76629099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress.76629099
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1394378062
Short name T478
Test name
Test status
Simulation time 41160045 ps
CPU time 0.65 seconds
Started Aug 08 05:12:30 PM PDT 24
Finished Aug 08 05:12:31 PM PDT 24
Peak memory 194704 kb
Host smart-6bbefa42-b7f0-4623-b301-a44a4d10aeee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394378062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1394378062
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.4270165934
Short name T700
Test name
Test status
Simulation time 46033642 ps
CPU time 1.25 seconds
Started Aug 08 05:12:18 PM PDT 24
Finished Aug 08 05:12:19 PM PDT 24
Peak memory 197880 kb
Host smart-cb0ab867-3b6d-4ff7-a347-a654ce9bac5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270165934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.4270165934
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1076858578
Short name T556
Test name
Test status
Simulation time 30635600 ps
CPU time 1.23 seconds
Started Aug 08 05:12:21 PM PDT 24
Finished Aug 08 05:12:22 PM PDT 24
Peak memory 197296 kb
Host smart-e72b4fb0-39b7-443d-b012-7969b22efad7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076858578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1076858578
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.875743487
Short name T533
Test name
Test status
Simulation time 58738774 ps
CPU time 1.1 seconds
Started Aug 08 05:12:19 PM PDT 24
Finished Aug 08 05:12:21 PM PDT 24
Peak memory 196104 kb
Host smart-c83b3a3a-f374-4610-a785-f63d8fa6e19f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875743487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.875743487
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3400002080
Short name T322
Test name
Test status
Simulation time 89514170 ps
CPU time 0.69 seconds
Started Aug 08 05:12:30 PM PDT 24
Finished Aug 08 05:12:31 PM PDT 24
Peak memory 194668 kb
Host smart-3ddfaec2-f8f1-4663-9252-70b2273ff15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400002080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3400002080
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.920849519
Short name T616
Test name
Test status
Simulation time 261923039 ps
CPU time 1.23 seconds
Started Aug 08 05:12:23 PM PDT 24
Finished Aug 08 05:12:24 PM PDT 24
Peak memory 198592 kb
Host smart-0e99853c-d0f7-4f66-87f1-aa6ec9f317b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920849519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.920849519
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2548646804
Short name T199
Test name
Test status
Simulation time 58981764 ps
CPU time 1.33 seconds
Started Aug 08 05:12:29 PM PDT 24
Finished Aug 08 05:12:31 PM PDT 24
Peak memory 198456 kb
Host smart-25cd4c97-412a-4010-88c3-9daf8533bde3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548646804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2548646804
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2741443804
Short name T133
Test name
Test status
Simulation time 195846789 ps
CPU time 1 seconds
Started Aug 08 05:12:28 PM PDT 24
Finished Aug 08 05:12:29 PM PDT 24
Peak memory 196164 kb
Host smart-5267f401-50d8-4d0a-ae35-470d18a974a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741443804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2741443804
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1752461418
Short name T704
Test name
Test status
Simulation time 113286553 ps
CPU time 1.17 seconds
Started Aug 08 05:12:33 PM PDT 24
Finished Aug 08 05:12:34 PM PDT 24
Peak memory 197388 kb
Host smart-9d1f6c75-5a7d-4b04-9f1d-92707eb9c58d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752461418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1752461418
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1458703823
Short name T7
Test name
Test status
Simulation time 28247556941 ps
CPU time 80.66 seconds
Started Aug 08 05:12:34 PM PDT 24
Finished Aug 08 05:13:55 PM PDT 24
Peak memory 198692 kb
Host smart-558c0567-2320-48e3-b667-0a15e1d7b9bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458703823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1458703823
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.1005517756
Short name T61
Test name
Test status
Simulation time 151953994185 ps
CPU time 323.66 seconds
Started Aug 08 05:12:29 PM PDT 24
Finished Aug 08 05:17:53 PM PDT 24
Peak memory 198892 kb
Host smart-5e400f1d-3deb-4de4-ab7f-8d512ae4da35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1005517756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.1005517756
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2340838441
Short name T34
Test name
Test status
Simulation time 37832870 ps
CPU time 0.58 seconds
Started Aug 08 05:12:20 PM PDT 24
Finished Aug 08 05:12:21 PM PDT 24
Peak memory 194508 kb
Host smart-1576b4b3-066d-47ac-aa70-35f6b757a3cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340838441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2340838441
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.4198398748
Short name T52
Test name
Test status
Simulation time 32131832 ps
CPU time 0.66 seconds
Started Aug 08 05:12:30 PM PDT 24
Finished Aug 08 05:12:30 PM PDT 24
Peak memory 194448 kb
Host smart-b3d3cde9-54cf-4cf1-bda7-e4379cc4b4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198398748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.4198398748
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1628581925
Short name T355
Test name
Test status
Simulation time 334258587 ps
CPU time 10.58 seconds
Started Aug 08 05:12:34 PM PDT 24
Finished Aug 08 05:12:45 PM PDT 24
Peak memory 198464 kb
Host smart-f4c70225-861f-43fa-b065-8e4b1aee5bc6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628581925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1628581925
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3318166193
Short name T469
Test name
Test status
Simulation time 59227854 ps
CPU time 0.91 seconds
Started Aug 08 05:12:29 PM PDT 24
Finished Aug 08 05:12:30 PM PDT 24
Peak memory 196532 kb
Host smart-18fa66c3-5dc2-456f-b32d-a0119c587462
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318166193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3318166193
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.3395929118
Short name T132
Test name
Test status
Simulation time 94814898 ps
CPU time 0.98 seconds
Started Aug 08 05:12:30 PM PDT 24
Finished Aug 08 05:12:31 PM PDT 24
Peak memory 197344 kb
Host smart-c00994ff-0768-4250-ab5d-13938219923a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395929118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3395929118
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.521854906
Short name T441
Test name
Test status
Simulation time 211767500 ps
CPU time 2.09 seconds
Started Aug 08 05:12:23 PM PDT 24
Finished Aug 08 05:12:25 PM PDT 24
Peak memory 197088 kb
Host smart-b9bd9fbe-13c1-4d23-92d3-4b0fe84259b2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521854906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.521854906
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3768275870
Short name T181
Test name
Test status
Simulation time 89723276 ps
CPU time 2.65 seconds
Started Aug 08 05:12:26 PM PDT 24
Finished Aug 08 05:12:29 PM PDT 24
Peak memory 197148 kb
Host smart-755d2ea1-454d-40b4-a1fd-a5499cc58403
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768275870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3768275870
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.1778389534
Short name T274
Test name
Test status
Simulation time 53934871 ps
CPU time 1.13 seconds
Started Aug 08 05:12:30 PM PDT 24
Finished Aug 08 05:12:31 PM PDT 24
Peak memory 196312 kb
Host smart-7bacd306-cb83-4513-aad9-8f29124fb44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778389534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.1778389534
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1995241217
Short name T101
Test name
Test status
Simulation time 503358280 ps
CPU time 0.86 seconds
Started Aug 08 05:12:21 PM PDT 24
Finished Aug 08 05:12:22 PM PDT 24
Peak memory 197636 kb
Host smart-ec56f112-9ddb-4ef8-9792-daae88abd6ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995241217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1995241217
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.132784408
Short name T11
Test name
Test status
Simulation time 1536374558 ps
CPU time 6.03 seconds
Started Aug 08 05:12:25 PM PDT 24
Finished Aug 08 05:12:31 PM PDT 24
Peak memory 197652 kb
Host smart-0c035f70-7f38-48b1-93c8-8efe485d19b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132784408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.132784408
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1533143487
Short name T280
Test name
Test status
Simulation time 350373850 ps
CPU time 1.21 seconds
Started Aug 08 05:12:22 PM PDT 24
Finished Aug 08 05:12:24 PM PDT 24
Peak memory 197036 kb
Host smart-e055ba83-ec13-4eb5-b35e-faac55d8d014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533143487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1533143487
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1659596257
Short name T507
Test name
Test status
Simulation time 235194442 ps
CPU time 1.06 seconds
Started Aug 08 05:12:21 PM PDT 24
Finished Aug 08 05:12:22 PM PDT 24
Peak memory 197000 kb
Host smart-2f7316a6-d686-4692-a967-3068237be24c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659596257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1659596257
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2746948637
Short name T225
Test name
Test status
Simulation time 5841637557 ps
CPU time 156.66 seconds
Started Aug 08 05:12:27 PM PDT 24
Finished Aug 08 05:15:04 PM PDT 24
Peak memory 198720 kb
Host smart-7c196864-1869-441c-965a-9368a70ca7c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746948637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2746948637
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.1218377107
Short name T537
Test name
Test status
Simulation time 31985411287 ps
CPU time 738.09 seconds
Started Aug 08 05:12:32 PM PDT 24
Finished Aug 08 05:24:50 PM PDT 24
Peak memory 198860 kb
Host smart-a2974097-ac38-4e01-a4bc-aed56f5545a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1218377107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.1218377107
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.1572327909
Short name T156
Test name
Test status
Simulation time 11039083 ps
CPU time 0.58 seconds
Started Aug 08 05:12:32 PM PDT 24
Finished Aug 08 05:12:33 PM PDT 24
Peak memory 195060 kb
Host smart-2561db6d-620f-45b7-b1ec-a6c1ea9004d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572327909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.1572327909
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2496040669
Short name T237
Test name
Test status
Simulation time 78798448 ps
CPU time 0.69 seconds
Started Aug 08 05:12:23 PM PDT 24
Finished Aug 08 05:12:23 PM PDT 24
Peak memory 195572 kb
Host smart-76a59633-9d99-42d1-99e6-b54d61f6cec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496040669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2496040669
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2270253813
Short name T461
Test name
Test status
Simulation time 858654330 ps
CPU time 24.48 seconds
Started Aug 08 05:12:25 PM PDT 24
Finished Aug 08 05:12:50 PM PDT 24
Peak memory 196048 kb
Host smart-40795ca3-25f5-4c8c-a6ae-c67addc8428c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270253813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2270253813
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2529217586
Short name T626
Test name
Test status
Simulation time 48494595 ps
CPU time 0.64 seconds
Started Aug 08 05:12:43 PM PDT 24
Finished Aug 08 05:12:44 PM PDT 24
Peak memory 195996 kb
Host smart-eb87f5cc-b357-4cb2-bc93-7f024cbd3329
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529217586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2529217586
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3693055284
Short name T466
Test name
Test status
Simulation time 122074100 ps
CPU time 0.64 seconds
Started Aug 08 05:12:26 PM PDT 24
Finished Aug 08 05:12:26 PM PDT 24
Peak memory 195464 kb
Host smart-e9982f45-b359-4a4d-9f8e-a00af38459fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693055284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3693055284
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3167859303
Short name T710
Test name
Test status
Simulation time 185247396 ps
CPU time 2.01 seconds
Started Aug 08 05:12:21 PM PDT 24
Finished Aug 08 05:12:23 PM PDT 24
Peak memory 197304 kb
Host smart-d9f03850-6ac1-46fc-a3e7-ec28c444107a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167859303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3167859303
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.575388449
Short name T195
Test name
Test status
Simulation time 100835804 ps
CPU time 1.82 seconds
Started Aug 08 05:12:23 PM PDT 24
Finished Aug 08 05:12:25 PM PDT 24
Peak memory 197160 kb
Host smart-c1f532f9-1680-484a-bc94-908d9cee68fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575388449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.575388449
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1281703597
Short name T22
Test name
Test status
Simulation time 26370501 ps
CPU time 1.06 seconds
Started Aug 08 05:12:30 PM PDT 24
Finished Aug 08 05:12:32 PM PDT 24
Peak memory 196516 kb
Host smart-3205a136-8ba7-4d95-be0a-49d9a13da9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281703597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1281703597
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1246514672
Short name T571
Test name
Test status
Simulation time 31098194 ps
CPU time 0.92 seconds
Started Aug 08 05:12:29 PM PDT 24
Finished Aug 08 05:12:30 PM PDT 24
Peak memory 196268 kb
Host smart-758d4611-24a1-439a-bdcd-438f377460da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246514672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1246514672
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3997223180
Short name T697
Test name
Test status
Simulation time 350468635 ps
CPU time 4.12 seconds
Started Aug 08 05:12:26 PM PDT 24
Finished Aug 08 05:12:30 PM PDT 24
Peak memory 198476 kb
Host smart-16d9f908-4439-4887-8a24-617ca909fdb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997223180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3997223180
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1224047309
Short name T634
Test name
Test status
Simulation time 264152892 ps
CPU time 1.13 seconds
Started Aug 08 05:12:28 PM PDT 24
Finished Aug 08 05:12:29 PM PDT 24
Peak memory 196092 kb
Host smart-92d7f174-67d9-4593-a396-2cde325fa736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224047309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1224047309
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3499484175
Short name T332
Test name
Test status
Simulation time 118462403 ps
CPU time 1.23 seconds
Started Aug 08 05:12:30 PM PDT 24
Finished Aug 08 05:12:32 PM PDT 24
Peak memory 196352 kb
Host smart-4906a2f1-c23d-4f67-b3eb-e5f793f8056d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499484175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3499484175
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.5435180
Short name T498
Test name
Test status
Simulation time 55448487402 ps
CPU time 195.56 seconds
Started Aug 08 05:12:24 PM PDT 24
Finished Aug 08 05:15:39 PM PDT 24
Peak memory 198980 kb
Host smart-2542b35c-831f-4d3d-8fe8-a9eb4e4719d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5435180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TES
T_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio
_stress_all.5435180
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.1110243730
Short name T655
Test name
Test status
Simulation time 302982404137 ps
CPU time 1633.2 seconds
Started Aug 08 05:12:28 PM PDT 24
Finished Aug 08 05:39:41 PM PDT 24
Peak memory 198680 kb
Host smart-3e3b7f32-3a78-4169-ac31-aeb8bf7f8d7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1110243730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.1110243730
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3765716259
Short name T906
Test name
Test status
Simulation time 93054600 ps
CPU time 0.99 seconds
Started Aug 08 05:11:46 PM PDT 24
Finished Aug 08 05:11:47 PM PDT 24
Peak memory 196464 kb
Host smart-6a46908d-09b4-497a-9290-5a6d22b9bfd0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3765716259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3765716259
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2194158536
Short name T909
Test name
Test status
Simulation time 95980381 ps
CPU time 1.51 seconds
Started Aug 08 05:11:49 PM PDT 24
Finished Aug 08 05:11:50 PM PDT 24
Peak memory 195596 kb
Host smart-5905dfe9-31dc-4ca2-9931-641bce23cbc6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194158536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2194158536
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.173974112
Short name T853
Test name
Test status
Simulation time 209405798 ps
CPU time 1.04 seconds
Started Aug 08 05:11:47 PM PDT 24
Finished Aug 08 05:11:48 PM PDT 24
Peak memory 196364 kb
Host smart-07372a5d-dc87-4e7a-8fe0-59976ef0d46d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=173974112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.173974112
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.998829881
Short name T938
Test name
Test status
Simulation time 59703939 ps
CPU time 1.01 seconds
Started Aug 08 05:11:50 PM PDT 24
Finished Aug 08 05:11:52 PM PDT 24
Peak memory 196560 kb
Host smart-1225ba51-9e94-467c-a554-89a3053300c1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998829881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.998829881
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3730740657
Short name T922
Test name
Test status
Simulation time 93551350 ps
CPU time 0.75 seconds
Started Aug 08 05:11:51 PM PDT 24
Finished Aug 08 05:11:52 PM PDT 24
Peak memory 195228 kb
Host smart-63cfe545-dffe-4203-a406-1a8558db5d8a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3730740657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3730740657
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1459915526
Short name T857
Test name
Test status
Simulation time 193660701 ps
CPU time 1.08 seconds
Started Aug 08 05:11:49 PM PDT 24
Finished Aug 08 05:11:50 PM PDT 24
Peak memory 196476 kb
Host smart-587541ce-aea4-4f25-82c7-1b1cac7156aa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459915526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1459915526
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.593529654
Short name T854
Test name
Test status
Simulation time 707107246 ps
CPU time 1.18 seconds
Started Aug 08 05:11:52 PM PDT 24
Finished Aug 08 05:11:53 PM PDT 24
Peak memory 196968 kb
Host smart-410b3f67-09e3-4688-a7ac-5ea9b09840c4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=593529654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.593529654
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1604486315
Short name T927
Test name
Test status
Simulation time 21966566 ps
CPU time 0.79 seconds
Started Aug 08 05:11:52 PM PDT 24
Finished Aug 08 05:11:53 PM PDT 24
Peak memory 195932 kb
Host smart-92358cf7-2726-472a-a402-18e361320338
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604486315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1604486315
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1662235758
Short name T842
Test name
Test status
Simulation time 109678861 ps
CPU time 1.02 seconds
Started Aug 08 05:11:46 PM PDT 24
Finished Aug 08 05:11:57 PM PDT 24
Peak memory 196416 kb
Host smart-f964d158-efdd-4b11-9a32-20e10f63b8ad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1662235758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1662235758
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3945488619
Short name T895
Test name
Test status
Simulation time 87411465 ps
CPU time 1.17 seconds
Started Aug 08 05:11:48 PM PDT 24
Finished Aug 08 05:11:49 PM PDT 24
Peak memory 195532 kb
Host smart-adb2480c-9196-4058-aa63-337b68fe5d77
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945488619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3945488619
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.600263815
Short name T929
Test name
Test status
Simulation time 124879993 ps
CPU time 0.83 seconds
Started Aug 08 05:11:50 PM PDT 24
Finished Aug 08 05:11:51 PM PDT 24
Peak memory 195204 kb
Host smart-5b114ac7-6376-46b4-b366-b96b72a5965c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=600263815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.600263815
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.82249497
Short name T931
Test name
Test status
Simulation time 243596269 ps
CPU time 1.31 seconds
Started Aug 08 05:12:03 PM PDT 24
Finished Aug 08 05:12:04 PM PDT 24
Peak memory 197980 kb
Host smart-2e12a7f0-97a2-4b6c-a493-3c37da612abf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82249497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.82249497
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2953369781
Short name T899
Test name
Test status
Simulation time 838995797 ps
CPU time 1.3 seconds
Started Aug 08 05:12:08 PM PDT 24
Finished Aug 08 05:12:09 PM PDT 24
Peak memory 197932 kb
Host smart-c41b0d99-0b2a-473f-b9e4-ff8ef33bb680
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2953369781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2953369781
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.780830030
Short name T917
Test name
Test status
Simulation time 198300946 ps
CPU time 1.55 seconds
Started Aug 08 05:11:48 PM PDT 24
Finished Aug 08 05:11:50 PM PDT 24
Peak memory 196640 kb
Host smart-23b1460f-1840-45a2-b4bf-55b3a11694ac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780830030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.780830030
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.893613669
Short name T885
Test name
Test status
Simulation time 50002790 ps
CPU time 1.15 seconds
Started Aug 08 05:11:50 PM PDT 24
Finished Aug 08 05:11:51 PM PDT 24
Peak memory 196456 kb
Host smart-b493296a-a299-4bfc-91c4-2bc1c55f3ae6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=893613669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.893613669
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.340626056
Short name T845
Test name
Test status
Simulation time 129585003 ps
CPU time 1.05 seconds
Started Aug 08 05:11:46 PM PDT 24
Finished Aug 08 05:11:47 PM PDT 24
Peak memory 196168 kb
Host smart-dbde9633-d8fc-44c6-abe4-45231cac983f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340626056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.340626056
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3627998702
Short name T914
Test name
Test status
Simulation time 30462525 ps
CPU time 1.06 seconds
Started Aug 08 05:11:54 PM PDT 24
Finished Aug 08 05:11:55 PM PDT 24
Peak memory 196504 kb
Host smart-1912b538-4ceb-419f-9c26-c1c13ba4888a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3627998702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3627998702
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2136205776
Short name T840
Test name
Test status
Simulation time 89629221 ps
CPU time 0.96 seconds
Started Aug 08 05:11:48 PM PDT 24
Finished Aug 08 05:11:49 PM PDT 24
Peak memory 196180 kb
Host smart-92581a72-9162-46ca-82cb-4d470c972039
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136205776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2136205776
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2963622402
Short name T849
Test name
Test status
Simulation time 212992392 ps
CPU time 1.42 seconds
Started Aug 08 05:11:54 PM PDT 24
Finished Aug 08 05:11:55 PM PDT 24
Peak memory 196656 kb
Host smart-a540aa3b-7486-4c46-8cec-cb4c1959d3f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2963622402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2963622402
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2337851300
Short name T915
Test name
Test status
Simulation time 41212793 ps
CPU time 0.93 seconds
Started Aug 08 05:11:58 PM PDT 24
Finished Aug 08 05:11:59 PM PDT 24
Peak memory 195484 kb
Host smart-dbff99d9-2dae-4d02-890d-fddc5e1dc572
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337851300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2337851300
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3210011611
Short name T879
Test name
Test status
Simulation time 80699651 ps
CPU time 0.88 seconds
Started Aug 08 05:11:47 PM PDT 24
Finished Aug 08 05:11:48 PM PDT 24
Peak memory 196460 kb
Host smart-33e050e9-de37-4337-ac81-7a6df261adda
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3210011611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3210011611
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1907405387
Short name T894
Test name
Test status
Simulation time 39693783 ps
CPU time 1.02 seconds
Started Aug 08 05:11:51 PM PDT 24
Finished Aug 08 05:11:52 PM PDT 24
Peak memory 196552 kb
Host smart-22e9b462-0d4d-4370-8de3-824dc25eb474
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907405387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1907405387
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1045576388
Short name T892
Test name
Test status
Simulation time 224063925 ps
CPU time 1.17 seconds
Started Aug 08 05:12:00 PM PDT 24
Finished Aug 08 05:12:02 PM PDT 24
Peak memory 198336 kb
Host smart-ce487b11-b02c-4c0b-98c3-40e631e2854c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1045576388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1045576388
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1771304321
Short name T850
Test name
Test status
Simulation time 49302858 ps
CPU time 0.94 seconds
Started Aug 08 05:12:02 PM PDT 24
Finished Aug 08 05:12:03 PM PDT 24
Peak memory 196636 kb
Host smart-727a28db-abd2-42c8-83dd-0ea1c84c27c7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771304321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1771304321
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3293503106
Short name T925
Test name
Test status
Simulation time 28067141 ps
CPU time 0.74 seconds
Started Aug 08 05:11:47 PM PDT 24
Finished Aug 08 05:11:48 PM PDT 24
Peak memory 195924 kb
Host smart-7324710f-ac9f-49b1-83ed-41ec3715eb2c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3293503106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3293503106
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1113674675
Short name T878
Test name
Test status
Simulation time 19828646 ps
CPU time 0.79 seconds
Started Aug 08 05:11:55 PM PDT 24
Finished Aug 08 05:11:56 PM PDT 24
Peak memory 195224 kb
Host smart-5fd2de1f-4d55-4216-b174-5d6b9e5b8c5e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113674675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1113674675
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1069227053
Short name T930
Test name
Test status
Simulation time 67944145 ps
CPU time 1.24 seconds
Started Aug 08 05:11:52 PM PDT 24
Finished Aug 08 05:11:54 PM PDT 24
Peak memory 197616 kb
Host smart-295e2189-6acb-4fbc-9075-c8c1fd09bac1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1069227053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1069227053
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3481747451
Short name T868
Test name
Test status
Simulation time 129557623 ps
CPU time 0.92 seconds
Started Aug 08 05:11:48 PM PDT 24
Finished Aug 08 05:11:49 PM PDT 24
Peak memory 196580 kb
Host smart-c2524b16-b64c-4e2f-84e9-b1517274909f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481747451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3481747451
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3933681217
Short name T893
Test name
Test status
Simulation time 52502490 ps
CPU time 1.4 seconds
Started Aug 08 05:11:49 PM PDT 24
Finished Aug 08 05:11:50 PM PDT 24
Peak memory 196644 kb
Host smart-dacd87fd-0c51-4614-bda5-52e431083c04
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3933681217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.3933681217
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3552509199
Short name T935
Test name
Test status
Simulation time 95766293 ps
CPU time 1.37 seconds
Started Aug 08 05:12:00 PM PDT 24
Finished Aug 08 05:12:02 PM PDT 24
Peak memory 196756 kb
Host smart-c288c36b-65f4-4d36-965c-e259185f15b1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552509199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3552509199
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1331394240
Short name T918
Test name
Test status
Simulation time 58863727 ps
CPU time 1.1 seconds
Started Aug 08 05:11:47 PM PDT 24
Finished Aug 08 05:11:48 PM PDT 24
Peak memory 196468 kb
Host smart-a6475460-38ae-4d13-9fe3-d245dc95cde0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1331394240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1331394240
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3514353218
Short name T921
Test name
Test status
Simulation time 21148378 ps
CPU time 0.81 seconds
Started Aug 08 05:12:01 PM PDT 24
Finished Aug 08 05:12:02 PM PDT 24
Peak memory 195296 kb
Host smart-e57f0c7d-bfe5-45f7-b160-4564d62aec80
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514353218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3514353218
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.4038127635
Short name T881
Test name
Test status
Simulation time 688821262 ps
CPU time 1.32 seconds
Started Aug 08 05:11:52 PM PDT 24
Finished Aug 08 05:11:53 PM PDT 24
Peak memory 196772 kb
Host smart-e89c0320-17ab-463b-95c5-845226e0338c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4038127635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.4038127635
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1974513071
Short name T907
Test name
Test status
Simulation time 192642682 ps
CPU time 1.28 seconds
Started Aug 08 05:11:51 PM PDT 24
Finished Aug 08 05:11:53 PM PDT 24
Peak memory 196796 kb
Host smart-124de8db-0eeb-45a0-8a87-0cc3658bb4c7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974513071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1974513071
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.498377001
Short name T855
Test name
Test status
Simulation time 309156127 ps
CPU time 1.29 seconds
Started Aug 08 05:11:57 PM PDT 24
Finished Aug 08 05:11:58 PM PDT 24
Peak memory 197948 kb
Host smart-6793af4f-6d9f-4f48-831f-adf2e5ba481a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=498377001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.498377001
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2131449615
Short name T891
Test name
Test status
Simulation time 37518558 ps
CPU time 1.17 seconds
Started Aug 08 05:12:00 PM PDT 24
Finished Aug 08 05:12:01 PM PDT 24
Peak memory 196440 kb
Host smart-7f173690-1ab4-41ec-a3b5-c605f2582fbc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131449615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2131449615
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3924278684
Short name T889
Test name
Test status
Simulation time 27917070 ps
CPU time 1 seconds
Started Aug 08 05:11:51 PM PDT 24
Finished Aug 08 05:11:52 PM PDT 24
Peak memory 197356 kb
Host smart-1f46e040-7ac7-4074-a673-a47c86aaf1ac
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3924278684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3924278684
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4161932373
Short name T886
Test name
Test status
Simulation time 31632784 ps
CPU time 0.92 seconds
Started Aug 08 05:12:03 PM PDT 24
Finished Aug 08 05:12:04 PM PDT 24
Peak memory 196548 kb
Host smart-39028c2e-c144-4ef9-b621-138ab86efc8a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161932373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4161932373
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.9211008
Short name T923
Test name
Test status
Simulation time 82106859 ps
CPU time 1.32 seconds
Started Aug 08 05:12:04 PM PDT 24
Finished Aug 08 05:12:05 PM PDT 24
Peak memory 196444 kb
Host smart-fb5218c5-2ab9-4764-b8d7-1eaa4f14267f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=9211008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.9211008
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3471957227
Short name T928
Test name
Test status
Simulation time 76699436 ps
CPU time 1.23 seconds
Started Aug 08 05:11:51 PM PDT 24
Finished Aug 08 05:11:53 PM PDT 24
Peak memory 196588 kb
Host smart-b063c87e-d0b2-47ba-9844-54d9c04101d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471957227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3471957227
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3749847769
Short name T859
Test name
Test status
Simulation time 38309863 ps
CPU time 1.32 seconds
Started Aug 08 05:12:04 PM PDT 24
Finished Aug 08 05:12:05 PM PDT 24
Peak memory 197972 kb
Host smart-16b9bd7b-2c65-4050-829d-3abb77c63558
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3749847769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3749847769
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1323693185
Short name T926
Test name
Test status
Simulation time 95999733 ps
CPU time 0.84 seconds
Started Aug 08 05:11:49 PM PDT 24
Finished Aug 08 05:11:50 PM PDT 24
Peak memory 195168 kb
Host smart-81fdbbba-03cc-4e45-8678-b32aefbf9110
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323693185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1323693185
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1321147789
Short name T875
Test name
Test status
Simulation time 67418569 ps
CPU time 1.22 seconds
Started Aug 08 05:12:01 PM PDT 24
Finished Aug 08 05:12:03 PM PDT 24
Peak memory 196452 kb
Host smart-218ad907-c24d-4ee1-8e49-319806a5c4e1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1321147789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1321147789
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.836262091
Short name T900
Test name
Test status
Simulation time 169553821 ps
CPU time 1.29 seconds
Started Aug 08 05:12:05 PM PDT 24
Finished Aug 08 05:12:07 PM PDT 24
Peak memory 196804 kb
Host smart-1a4e372a-12a2-47c4-8f47-54b0372145f4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836262091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.836262091
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2220658023
Short name T908
Test name
Test status
Simulation time 461008351 ps
CPU time 1.2 seconds
Started Aug 08 05:12:00 PM PDT 24
Finished Aug 08 05:12:01 PM PDT 24
Peak memory 195900 kb
Host smart-677e59a6-12c0-44fc-b0a9-2b9cb3e7b197
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2220658023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2220658023
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3460980151
Short name T843
Test name
Test status
Simulation time 31041248 ps
CPU time 0.95 seconds
Started Aug 08 05:12:07 PM PDT 24
Finished Aug 08 05:12:08 PM PDT 24
Peak memory 195224 kb
Host smart-1272f154-473f-4667-b65a-9477a6ffc0f6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460980151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3460980151
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1447357612
Short name T933
Test name
Test status
Simulation time 48497990 ps
CPU time 0.73 seconds
Started Aug 08 05:11:51 PM PDT 24
Finished Aug 08 05:11:52 PM PDT 24
Peak memory 195256 kb
Host smart-41e82557-b970-4d4a-ad99-ea593faa3736
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1447357612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1447357612
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3748428487
Short name T861
Test name
Test status
Simulation time 107185651 ps
CPU time 1.07 seconds
Started Aug 08 05:11:48 PM PDT 24
Finished Aug 08 05:11:49 PM PDT 24
Peak memory 195576 kb
Host smart-46a5294e-5cd5-4798-a974-6f63e9ae0264
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748428487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3748428487
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3067276807
Short name T873
Test name
Test status
Simulation time 99195816 ps
CPU time 0.95 seconds
Started Aug 08 05:12:26 PM PDT 24
Finished Aug 08 05:12:27 PM PDT 24
Peak memory 197216 kb
Host smart-f2ab9be0-f55c-4ef2-867f-036bd687e32d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3067276807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3067276807
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3580696721
Short name T896
Test name
Test status
Simulation time 121332173 ps
CPU time 1.35 seconds
Started Aug 08 05:12:05 PM PDT 24
Finished Aug 08 05:12:11 PM PDT 24
Peak memory 197912 kb
Host smart-5e22d84e-fdb0-40fe-a62b-416ef9f2dea3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580696721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3580696721
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.722022956
Short name T847
Test name
Test status
Simulation time 63391419 ps
CPU time 0.85 seconds
Started Aug 08 05:12:05 PM PDT 24
Finished Aug 08 05:12:06 PM PDT 24
Peak memory 195056 kb
Host smart-96648117-1ddb-4dc5-b8df-e59fd5a26c8a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=722022956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.722022956
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.604545823
Short name T876
Test name
Test status
Simulation time 116870698 ps
CPU time 0.89 seconds
Started Aug 08 05:12:01 PM PDT 24
Finished Aug 08 05:12:02 PM PDT 24
Peak memory 195388 kb
Host smart-16021145-fe19-4bb0-a602-f39193d738f7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604545823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.604545823
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1970207096
Short name T919
Test name
Test status
Simulation time 695526185 ps
CPU time 1.1 seconds
Started Aug 08 05:12:12 PM PDT 24
Finished Aug 08 05:12:13 PM PDT 24
Peak memory 198032 kb
Host smart-f8c121dc-5ab7-46e2-a99d-c530cd04f007
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1970207096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1970207096
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3729112899
Short name T911
Test name
Test status
Simulation time 82887931 ps
CPU time 1.14 seconds
Started Aug 08 05:12:10 PM PDT 24
Finished Aug 08 05:12:11 PM PDT 24
Peak memory 196628 kb
Host smart-61e1fab8-3a64-4b43-9ef9-5f111e544ea8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729112899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3729112899
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2981536122
Short name T898
Test name
Test status
Simulation time 101264687 ps
CPU time 1.06 seconds
Started Aug 08 05:11:56 PM PDT 24
Finished Aug 08 05:11:58 PM PDT 24
Peak memory 198084 kb
Host smart-a24d2022-b465-4ce2-a84c-b453e2220d75
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2981536122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2981536122
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1034951834
Short name T920
Test name
Test status
Simulation time 54009111 ps
CPU time 0.79 seconds
Started Aug 08 05:12:19 PM PDT 24
Finished Aug 08 05:12:20 PM PDT 24
Peak memory 195372 kb
Host smart-d622fdf9-6bd4-4e56-a5dd-f1645e580369
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034951834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1034951834
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2663002969
Short name T902
Test name
Test status
Simulation time 362235888 ps
CPU time 1.61 seconds
Started Aug 08 05:12:05 PM PDT 24
Finished Aug 08 05:12:06 PM PDT 24
Peak memory 198024 kb
Host smart-c975173c-71e8-4485-acd1-de12f0f1ed95
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2663002969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2663002969
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.420842193
Short name T841
Test name
Test status
Simulation time 61915768 ps
CPU time 1.25 seconds
Started Aug 08 05:12:10 PM PDT 24
Finished Aug 08 05:12:12 PM PDT 24
Peak memory 195580 kb
Host smart-327a7cf0-1940-4e71-8015-1822d9b95f99
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420842193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.420842193
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.4217365406
Short name T905
Test name
Test status
Simulation time 301552398 ps
CPU time 1.35 seconds
Started Aug 08 05:11:55 PM PDT 24
Finished Aug 08 05:11:56 PM PDT 24
Peak memory 198032 kb
Host smart-f7051cda-6e16-41da-8dac-96f475e14372
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4217365406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.4217365406
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3840614340
Short name T887
Test name
Test status
Simulation time 37153805 ps
CPU time 1.06 seconds
Started Aug 08 05:12:07 PM PDT 24
Finished Aug 08 05:12:08 PM PDT 24
Peak memory 196732 kb
Host smart-85b4cc92-9164-4011-9abe-170841fe9837
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840614340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3840614340
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3928560099
Short name T883
Test name
Test status
Simulation time 266891716 ps
CPU time 1.25 seconds
Started Aug 08 05:12:07 PM PDT 24
Finished Aug 08 05:12:08 PM PDT 24
Peak memory 196620 kb
Host smart-4217e178-38d1-4b86-85b7-dc34b0e44a8b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3928560099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3928560099
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.586143462
Short name T890
Test name
Test status
Simulation time 43450883 ps
CPU time 1.11 seconds
Started Aug 08 05:12:12 PM PDT 24
Finished Aug 08 05:12:13 PM PDT 24
Peak memory 196584 kb
Host smart-06e9d850-b407-4ceb-a2c6-427243fb6030
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586143462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.586143462
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3554049766
Short name T856
Test name
Test status
Simulation time 54215399 ps
CPU time 1.02 seconds
Started Aug 08 05:12:06 PM PDT 24
Finished Aug 08 05:12:07 PM PDT 24
Peak memory 196412 kb
Host smart-e9a0c601-0b56-4439-9a60-221e28e5e8e9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3554049766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3554049766
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.860892617
Short name T867
Test name
Test status
Simulation time 208881957 ps
CPU time 0.97 seconds
Started Aug 08 05:12:13 PM PDT 24
Finished Aug 08 05:12:14 PM PDT 24
Peak memory 196560 kb
Host smart-5ef912fd-e40a-4e31-b2a0-df9bdebffc85
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860892617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.860892617
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2260319068
Short name T913
Test name
Test status
Simulation time 196046893 ps
CPU time 1.22 seconds
Started Aug 08 05:12:09 PM PDT 24
Finished Aug 08 05:12:11 PM PDT 24
Peak memory 197916 kb
Host smart-0da4f93a-a548-46da-a70c-2ee79461344c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2260319068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2260319068
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.792485252
Short name T880
Test name
Test status
Simulation time 167686733 ps
CPU time 1.54 seconds
Started Aug 08 05:11:58 PM PDT 24
Finished Aug 08 05:12:00 PM PDT 24
Peak memory 196820 kb
Host smart-941be71e-6b59-4cd1-8493-324ded55b0a5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792485252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.792485252
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1629555147
Short name T903
Test name
Test status
Simulation time 121997683 ps
CPU time 1.21 seconds
Started Aug 08 05:12:11 PM PDT 24
Finished Aug 08 05:12:13 PM PDT 24
Peak memory 197832 kb
Host smart-b2fa20f9-faad-4811-b17c-642531a026b1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1629555147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1629555147
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.197113948
Short name T934
Test name
Test status
Simulation time 147923253 ps
CPU time 1.13 seconds
Started Aug 08 05:12:01 PM PDT 24
Finished Aug 08 05:12:02 PM PDT 24
Peak memory 196628 kb
Host smart-e111f421-ccbc-4ecf-8195-27ddcb1ff3fd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197113948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.197113948
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3167461279
Short name T874
Test name
Test status
Simulation time 369763971 ps
CPU time 0.9 seconds
Started Aug 08 05:11:50 PM PDT 24
Finished Aug 08 05:11:51 PM PDT 24
Peak memory 196936 kb
Host smart-26253b91-51aa-48e8-aa94-48d0d734b1ca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3167461279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.3167461279
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3356287967
Short name T858
Test name
Test status
Simulation time 156043388 ps
CPU time 1.09 seconds
Started Aug 08 05:11:49 PM PDT 24
Finished Aug 08 05:11:50 PM PDT 24
Peak memory 196600 kb
Host smart-02aecb6a-a2a0-43d6-971b-407d22fafc60
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356287967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3356287967
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3231612673
Short name T872
Test name
Test status
Simulation time 150483135 ps
CPU time 0.85 seconds
Started Aug 08 05:11:58 PM PDT 24
Finished Aug 08 05:11:59 PM PDT 24
Peak memory 196120 kb
Host smart-abdb8023-3ab1-4c2c-8b84-7e5062b07d17
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3231612673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3231612673
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.940811420
Short name T937
Test name
Test status
Simulation time 220962045 ps
CPU time 0.97 seconds
Started Aug 08 05:12:00 PM PDT 24
Finished Aug 08 05:12:01 PM PDT 24
Peak memory 196692 kb
Host smart-bbebe775-ec29-4c0a-9ce2-e37be0a7357b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940811420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.940811420
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3316602150
Short name T901
Test name
Test status
Simulation time 90226569 ps
CPU time 1.4 seconds
Started Aug 08 05:12:13 PM PDT 24
Finished Aug 08 05:12:14 PM PDT 24
Peak memory 196876 kb
Host smart-38bcfb05-63b2-40a5-be6a-962bef2be089
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3316602150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3316602150
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.217493056
Short name T936
Test name
Test status
Simulation time 234675106 ps
CPU time 0.99 seconds
Started Aug 08 05:12:14 PM PDT 24
Finished Aug 08 05:12:15 PM PDT 24
Peak memory 197800 kb
Host smart-2dc2828c-8047-4856-a665-ca328d107e2f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217493056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.217493056
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2173083469
Short name T863
Test name
Test status
Simulation time 359648759 ps
CPU time 1.51 seconds
Started Aug 08 05:12:17 PM PDT 24
Finished Aug 08 05:12:18 PM PDT 24
Peak memory 196664 kb
Host smart-0a227385-fe69-4495-8bad-08bfdca8cd28
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2173083469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.2173083469
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3746315362
Short name T904
Test name
Test status
Simulation time 101923566 ps
CPU time 1.09 seconds
Started Aug 08 05:12:04 PM PDT 24
Finished Aug 08 05:12:05 PM PDT 24
Peak memory 197964 kb
Host smart-8d9ee785-c4c3-483c-97bc-6f6b32e65dc3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746315362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3746315362
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2983560051
Short name T851
Test name
Test status
Simulation time 60221094 ps
CPU time 1.05 seconds
Started Aug 08 05:12:01 PM PDT 24
Finished Aug 08 05:12:02 PM PDT 24
Peak memory 195620 kb
Host smart-55c72e64-bfb9-419d-af70-aa1cf15185ca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2983560051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2983560051
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2368229383
Short name T848
Test name
Test status
Simulation time 50766443 ps
CPU time 0.88 seconds
Started Aug 08 05:12:17 PM PDT 24
Finished Aug 08 05:12:18 PM PDT 24
Peak memory 196444 kb
Host smart-86697230-b6d3-409e-a8f5-517a2b1f0476
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368229383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2368229383
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.311804690
Short name T862
Test name
Test status
Simulation time 152926592 ps
CPU time 1.16 seconds
Started Aug 08 05:12:05 PM PDT 24
Finished Aug 08 05:12:06 PM PDT 24
Peak memory 196792 kb
Host smart-18fb05d3-97f8-4d3f-940b-18ec7309cfdc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=311804690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.311804690
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3178180491
Short name T844
Test name
Test status
Simulation time 100148795 ps
CPU time 1.42 seconds
Started Aug 08 05:12:04 PM PDT 24
Finished Aug 08 05:12:05 PM PDT 24
Peak memory 196572 kb
Host smart-eaa007df-4046-4033-81cc-9b4e6d68143d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178180491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3178180491
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1163521971
Short name T846
Test name
Test status
Simulation time 162174417 ps
CPU time 0.94 seconds
Started Aug 08 05:12:16 PM PDT 24
Finished Aug 08 05:12:17 PM PDT 24
Peak memory 196188 kb
Host smart-8e816261-7550-4643-8f28-788d6b6c2fc9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1163521971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1163521971
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1642599081
Short name T866
Test name
Test status
Simulation time 47684160 ps
CPU time 0.79 seconds
Started Aug 08 05:12:21 PM PDT 24
Finished Aug 08 05:12:22 PM PDT 24
Peak memory 195356 kb
Host smart-931e86dd-b809-4d78-8e4b-f1ddf1d5b1f4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642599081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1642599081
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1575060432
Short name T884
Test name
Test status
Simulation time 38782299 ps
CPU time 1.26 seconds
Started Aug 08 05:12:07 PM PDT 24
Finished Aug 08 05:12:08 PM PDT 24
Peak memory 196488 kb
Host smart-46415de2-4240-4320-a673-ce6aa1b34b14
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1575060432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1575060432
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4184751897
Short name T897
Test name
Test status
Simulation time 35902518 ps
CPU time 1.02 seconds
Started Aug 08 05:12:13 PM PDT 24
Finished Aug 08 05:12:14 PM PDT 24
Peak memory 197704 kb
Host smart-683a8fcc-8eed-4a22-87fa-a1385d58848e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184751897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4184751897
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.4206438356
Short name T912
Test name
Test status
Simulation time 49113214 ps
CPU time 1.3 seconds
Started Aug 08 05:12:17 PM PDT 24
Finished Aug 08 05:12:19 PM PDT 24
Peak memory 197996 kb
Host smart-f432c3c4-2df6-402b-8657-fe360c4cd360
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4206438356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.4206438356
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1017310256
Short name T924
Test name
Test status
Simulation time 172620627 ps
CPU time 1.39 seconds
Started Aug 08 05:12:10 PM PDT 24
Finished Aug 08 05:12:11 PM PDT 24
Peak memory 196844 kb
Host smart-ada33be5-a10b-4f62-9f95-0543136e7e34
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017310256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1017310256
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1507463150
Short name T864
Test name
Test status
Simulation time 59272861 ps
CPU time 0.9 seconds
Started Aug 08 05:12:02 PM PDT 24
Finished Aug 08 05:12:03 PM PDT 24
Peak memory 196036 kb
Host smart-282d8d93-79e1-4555-bfac-79ab23d549ea
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1507463150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1507463150
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.925285761
Short name T870
Test name
Test status
Simulation time 389326389 ps
CPU time 1.54 seconds
Started Aug 08 05:12:08 PM PDT 24
Finished Aug 08 05:12:09 PM PDT 24
Peak memory 196708 kb
Host smart-544a6d92-7aea-4d06-8fb7-2a2b75a81e1c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925285761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.925285761
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3527646893
Short name T877
Test name
Test status
Simulation time 223548948 ps
CPU time 1.28 seconds
Started Aug 08 05:12:12 PM PDT 24
Finished Aug 08 05:12:14 PM PDT 24
Peak memory 195888 kb
Host smart-1991f2bf-5af2-493b-bc59-493006bf5b9a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3527646893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3527646893
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2314688934
Short name T869
Test name
Test status
Simulation time 131260117 ps
CPU time 1.14 seconds
Started Aug 08 05:12:14 PM PDT 24
Finished Aug 08 05:12:15 PM PDT 24
Peak memory 196552 kb
Host smart-2a67ba3a-5fc5-4843-94d5-bc3d4b740fee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314688934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2314688934
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.731303491
Short name T888
Test name
Test status
Simulation time 52162483 ps
CPU time 0.86 seconds
Started Aug 08 05:11:46 PM PDT 24
Finished Aug 08 05:11:47 PM PDT 24
Peak memory 195460 kb
Host smart-b58b115b-8cbb-4add-aa73-4944a25df46f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=731303491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.731303491
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3874110818
Short name T860
Test name
Test status
Simulation time 32367517 ps
CPU time 0.98 seconds
Started Aug 08 05:11:51 PM PDT 24
Finished Aug 08 05:11:52 PM PDT 24
Peak memory 196360 kb
Host smart-c5016894-2bed-4c07-8490-cdf449195626
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874110818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3874110818
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.471292523
Short name T910
Test name
Test status
Simulation time 31789673 ps
CPU time 0.79 seconds
Started Aug 08 05:11:50 PM PDT 24
Finished Aug 08 05:11:51 PM PDT 24
Peak memory 195216 kb
Host smart-0a8794c5-4b00-4aee-ab33-f855d7442220
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=471292523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.471292523
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.168809053
Short name T865
Test name
Test status
Simulation time 407912776 ps
CPU time 1.08 seconds
Started Aug 08 05:11:50 PM PDT 24
Finished Aug 08 05:11:51 PM PDT 24
Peak memory 197448 kb
Host smart-e0f693d8-cd02-4cb9-98d3-29c76957d809
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168809053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.168809053
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2826699354
Short name T939
Test name
Test status
Simulation time 42287614 ps
CPU time 1.16 seconds
Started Aug 08 05:11:50 PM PDT 24
Finished Aug 08 05:11:51 PM PDT 24
Peak memory 195768 kb
Host smart-b5456f1e-4ba8-484f-bd02-65f6f94c7af6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2826699354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2826699354
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4159514052
Short name T932
Test name
Test status
Simulation time 204773988 ps
CPU time 1.1 seconds
Started Aug 08 05:11:47 PM PDT 24
Finished Aug 08 05:11:48 PM PDT 24
Peak memory 195740 kb
Host smart-3d8d4b43-c952-43fe-9b4f-f08ff953e24b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159514052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4159514052
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3371605638
Short name T916
Test name
Test status
Simulation time 53060147 ps
CPU time 0.95 seconds
Started Aug 08 05:11:47 PM PDT 24
Finished Aug 08 05:11:48 PM PDT 24
Peak memory 196420 kb
Host smart-876aee38-5287-48ed-a2df-735720456a67
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3371605638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3371605638
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3193112247
Short name T871
Test name
Test status
Simulation time 290578288 ps
CPU time 0.82 seconds
Started Aug 08 05:11:49 PM PDT 24
Finished Aug 08 05:11:50 PM PDT 24
Peak memory 191380 kb
Host smart-aae00802-82c7-4f67-986d-80699a90caea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193112247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3193112247
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.448857719
Short name T852
Test name
Test status
Simulation time 112532842 ps
CPU time 0.79 seconds
Started Aug 08 05:11:50 PM PDT 24
Finished Aug 08 05:11:51 PM PDT 24
Peak memory 195340 kb
Host smart-193558c1-857e-45e7-9955-685d3651e1fc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=448857719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.448857719
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3447943561
Short name T882
Test name
Test status
Simulation time 109489459 ps
CPU time 1.14 seconds
Started Aug 08 05:11:48 PM PDT 24
Finished Aug 08 05:11:49 PM PDT 24
Peak memory 196432 kb
Host smart-ab750955-7d5a-406b-b5f5-2e57959cb272
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447943561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3447943561
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%