Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4293916	1			T24	59		T25	1		T26	202
all_pins[1]	4293916	1			T24	59		T25	1		T26	202
all_pins[2]	4293916	1			T24	59		T25	1		T26	202
all_pins[3]	4293916	1			T24	59		T25	1		T26	202
all_pins[4]	4293916	1			T24	59		T25	1		T26	202
all_pins[5]	4293916	1			T24	59		T25	1		T26	202
all_pins[6]	4293916	1			T24	59		T25	1		T26	202
all_pins[7]	4293916	1			T24	59		T25	1		T26	202
all_pins[8]	4293916	1			T24	59		T25	1		T26	202
all_pins[9]	4293916	1			T24	59		T25	1		T26	202
all_pins[10]	4293916	1			T24	59		T25	1		T26	202
all_pins[11]	4293916	1			T24	59		T25	1		T26	202
all_pins[12]	4293916	1			T24	59		T25	1		T26	202
all_pins[13]	4293916	1			T24	59		T25	1		T26	202
all_pins[14]	4293916	1			T24	59		T25	1		T26	202
all_pins[15]	4293916	1			T24	59		T25	1		T26	202
all_pins[16]	4293916	1			T24	59		T25	1		T26	202
all_pins[17]	4293916	1			T24	59		T25	1		T26	202
all_pins[18]	4293916	1			T24	59		T25	1		T26	202
all_pins[19]	4293916	1			T24	59		T25	1		T26	202
all_pins[20]	4293916	1			T24	59		T25	1		T26	202
all_pins[21]	4293916	1			T24	59		T25	1		T26	202
all_pins[22]	4293916	1			T24	59		T25	1		T26	202
all_pins[23]	4293916	1			T24	59		T25	1		T26	202
all_pins[24]	4293916	1			T24	59		T25	1		T26	202
all_pins[25]	4293916	1			T24	59		T25	1		T26	202
all_pins[26]	4293916	1			T24	59		T25	1		T26	202
all_pins[27]	4293916	1			T24	59		T25	1		T26	202
all_pins[28]	4293916	1			T24	59		T25	1		T26	202
all_pins[29]	4293916	1			T24	59		T25	1		T26	202
all_pins[30]	4293916	1			T24	59		T25	1		T26	202
all_pins[31]	4293916	1			T24	59		T25	1		T26	202

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	85379029	1			T24	1089		T25	32		T26	3959
values[0x1]	52026283	1			T24	799		T26	2505		T1	7642
transitions[0x0=>0x1]	31189312	1			T24	449		T26	1475		T1	4643
transitions[0x1=>0x0]	31189147	1			T24	449		T26	1475		T1	4642

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2669776	1			T24	32		T25	1		T26	145
all_pins[0]	values[0x1]	1624140	1			T24	27		T26	57		T1	265
all_pins[0]	transitions[0x0=>0x1]	1007138	1			T24	14		T26	37		T1	191
all_pins[0]	transitions[0x1=>0x0]	1001040	1			T24	17		T26	66		T1	141
all_pins[1]	values[0x0]	2665006	1			T24	32		T25	1		T26	127
all_pins[1]	values[0x1]	1628910	1			T24	27		T26	75		T1	221
all_pins[1]	transitions[0x0=>0x1]	975878	1			T24	15		T26	52		T1	143
all_pins[1]	transitions[0x1=>0x0]	971108	1			T24	15		T26	34		T1	187
all_pins[2]	values[0x0]	2669542	1			T24	34		T25	1		T26	127
all_pins[2]	values[0x1]	1624374	1			T24	25		T26	75		T1	215
all_pins[2]	transitions[0x0=>0x1]	971468	1			T24	11		T26	43		T1	142
all_pins[2]	transitions[0x1=>0x0]	976004	1			T24	13		T26	43		T1	148
all_pins[3]	values[0x0]	2665556	1			T24	31		T25	1		T26	138
all_pins[3]	values[0x1]	1628360	1			T24	28		T26	64		T1	235
all_pins[3]	transitions[0x0=>0x1]	975562	1			T24	13		T26	40		T1	162
all_pins[3]	transitions[0x1=>0x0]	971576	1			T24	10		T26	51		T1	142
all_pins[4]	values[0x0]	2666264	1			T24	30		T25	1		T26	92
all_pins[4]	values[0x1]	1627652	1			T24	29		T26	110		T1	213
all_pins[4]	transitions[0x0=>0x1]	973919	1			T24	12		T26	75		T1	114
all_pins[4]	transitions[0x1=>0x0]	974627	1			T24	11		T26	29		T1	136
all_pins[5]	values[0x0]	2668873	1			T24	37		T25	1		T26	93
all_pins[5]	values[0x1]	1625043	1			T24	22		T26	109		T1	250
all_pins[5]	transitions[0x0=>0x1]	971150	1			T24	11		T26	40		T1	150
all_pins[5]	transitions[0x1=>0x0]	973759	1			T24	18		T26	41		T1	113
all_pins[6]	values[0x0]	2670564	1			T24	34		T25	1		T26	109
all_pins[6]	values[0x1]	1623352	1			T24	25		T26	93		T1	250
all_pins[6]	transitions[0x0=>0x1]	973467	1			T24	15		T26	41		T1	171
all_pins[6]	transitions[0x1=>0x0]	975158	1			T24	12		T26	57		T1	171
all_pins[7]	values[0x0]	2667194	1			T24	16		T25	1		T26	129
all_pins[7]	values[0x1]	1626722	1			T24	43		T26	73		T1	268
all_pins[7]	transitions[0x0=>0x1]	974800	1			T24	24		T26	29		T1	146
all_pins[7]	transitions[0x1=>0x0]	971430	1			T24	6		T26	49		T1	128
all_pins[8]	values[0x0]	2671839	1			T24	35		T25	1		T26	104
all_pins[8]	values[0x1]	1622077	1			T24	24		T26	98		T1	209
all_pins[8]	transitions[0x0=>0x1]	970934	1			T24	3		T26	61		T1	111
all_pins[8]	transitions[0x1=>0x0]	975579	1			T24	22		T26	36		T1	170
all_pins[9]	values[0x0]	2671087	1			T24	40		T25	1		T26	169
all_pins[9]	values[0x1]	1622829	1			T24	19		T26	33		T1	184
all_pins[9]	transitions[0x0=>0x1]	971774	1			T24	10		T26	11		T1	116
all_pins[9]	transitions[0x1=>0x0]	971022	1			T24	15		T26	76		T1	141
all_pins[10]	values[0x0]	2667503	1			T24	34		T25	1		T26	143
all_pins[10]	values[0x1]	1626413	1			T24	25		T26	59		T1	206
all_pins[10]	transitions[0x0=>0x1]	975231	1			T24	14		T26	49		T1	147
all_pins[10]	transitions[0x1=>0x0]	971647	1			T24	8		T26	23		T1	125
all_pins[11]	values[0x0]	2668912	1			T24	39		T25	1		T26	166
all_pins[11]	values[0x1]	1625004	1			T24	20		T26	36		T1	254
all_pins[11]	transitions[0x0=>0x1]	972438	1			T24	13		T26	28		T1	167
all_pins[11]	transitions[0x1=>0x0]	973847	1			T24	18		T26	51		T1	119
all_pins[12]	values[0x0]	2666857	1			T24	32		T25	1		T26	131
all_pins[12]	values[0x1]	1627059	1			T24	27		T26	71		T1	250
all_pins[12]	transitions[0x0=>0x1]	974099	1			T24	16		T26	56		T1	154
all_pins[12]	transitions[0x1=>0x0]	972044	1			T24	9		T26	21		T1	158
all_pins[13]	values[0x0]	2667323	1			T24	34		T25	1		T26	87
all_pins[13]	values[0x1]	1626593	1			T24	25		T26	115		T1	256
all_pins[13]	transitions[0x0=>0x1]	973711	1			T24	15		T26	69		T1	124
all_pins[13]	transitions[0x1=>0x0]	974177	1			T24	17		T26	25		T1	118
all_pins[14]	values[0x0]	2668695	1			T24	36		T25	1		T26	147
all_pins[14]	values[0x1]	1625221	1			T24	23		T26	55		T1	297
all_pins[14]	transitions[0x0=>0x1]	976655	1			T24	12		T26	21		T1	171
all_pins[14]	transitions[0x1=>0x0]	978027	1			T24	14		T26	81		T1	130
all_pins[15]	values[0x0]	2672888	1			T24	40		T25	1		T26	106
all_pins[15]	values[0x1]	1621028	1			T24	19		T26	96		T1	299
all_pins[15]	transitions[0x0=>0x1]	968575	1			T24	12		T26	61		T1	162
all_pins[15]	transitions[0x1=>0x0]	972768	1			T24	16		T26	20		T1	160
all_pins[16]	values[0x0]	2665246	1			T24	40		T25	1		T26	124
all_pins[16]	values[0x1]	1628670	1			T24	19		T26	78		T1	272
all_pins[16]	transitions[0x0=>0x1]	978002	1			T24	12		T26	47		T1	135
all_pins[16]	transitions[0x1=>0x0]	970360	1			T24	12		T26	65		T1	162
all_pins[17]	values[0x0]	2672102	1			T24	33		T25	1		T26	86
all_pins[17]	values[0x1]	1621814	1			T24	26		T26	116		T1	231
all_pins[17]	transitions[0x0=>0x1]	972348	1			T24	18		T26	66		T1	151
all_pins[17]	transitions[0x1=>0x0]	979204	1			T24	11		T26	28		T1	192
all_pins[18]	values[0x0]	2669136	1			T24	36		T25	1		T26	104
all_pins[18]	values[0x1]	1624780	1			T24	23		T26	98		T1	270
all_pins[18]	transitions[0x0=>0x1]	973967	1			T24	16		T26	32		T1	146
all_pins[18]	transitions[0x1=>0x0]	971001	1			T24	19		T26	50		T1	107
all_pins[19]	values[0x0]	2665491	1			T24	26		T25	1		T26	140
all_pins[19]	values[0x1]	1628425	1			T24	33		T26	62		T1	173
all_pins[19]	transitions[0x0=>0x1]	974347	1			T24	22		T26	19		T1	77
all_pins[19]	transitions[0x1=>0x0]	970702	1			T24	12		T26	55		T1	174
all_pins[20]	values[0x0]	2667715	1			T24	40		T25	1		T26	146
all_pins[20]	values[0x1]	1626201	1			T24	19		T26	56		T1	243
all_pins[20]	transitions[0x0=>0x1]	969493	1			T24	6		T26	43		T1	177
all_pins[20]	transitions[0x1=>0x0]	971717	1			T24	20		T26	49		T1	107
all_pins[21]	values[0x0]	2670203	1			T24	31		T25	1		T26	118
all_pins[21]	values[0x1]	1623713	1			T24	28		T26	84		T1	198
all_pins[21]	transitions[0x0=>0x1]	974177	1			T24	21		T26	58		T1	111
all_pins[21]	transitions[0x1=>0x0]	976665	1			T24	12		T26	30		T1	156
all_pins[22]	values[0x0]	2662985	1			T24	32		T25	1		T26	156
all_pins[22]	values[0x1]	1630931	1			T24	27		T26	46		T1	279
all_pins[22]	transitions[0x0=>0x1]	979950	1			T24	14		T26	23		T1	188
all_pins[22]	transitions[0x1=>0x0]	972732	1			T24	15		T26	61		T1	107
all_pins[23]	values[0x0]	2671381	1			T24	26		T25	1		T26	127
all_pins[23]	values[0x1]	1622535	1			T24	33		T26	75		T1	206
all_pins[23]	transitions[0x0=>0x1]	970787	1			T24	21		T26	60		T1	136
all_pins[23]	transitions[0x1=>0x0]	979183	1			T24	15		T26	31		T1	209
all_pins[24]	values[0x0]	2671122	1			T24	40		T25	1		T26	120
all_pins[24]	values[0x1]	1622794	1			T24	19		T26	82		T1	208
all_pins[24]	transitions[0x0=>0x1]	974322	1			T24	9		T26	57		T1	125
all_pins[24]	transitions[0x1=>0x0]	974063	1			T24	23		T26	50		T1	123
all_pins[25]	values[0x0]	2664383	1			T24	38		T25	1		T26	91
all_pins[25]	values[0x1]	1629533	1			T24	21		T26	111		T1	243
all_pins[25]	transitions[0x0=>0x1]	976946	1			T24	15		T26	76		T1	162
all_pins[25]	transitions[0x1=>0x0]	970207	1			T24	13		T26	47		T1	127
all_pins[26]	values[0x0]	2668941	1			T24	36		T25	1		T26	134
all_pins[26]	values[0x1]	1624975	1			T24	23		T26	68		T1	258
all_pins[26]	transitions[0x0=>0x1]	972065	1			T24	16		T26	26		T1	161
all_pins[26]	transitions[0x1=>0x0]	976623	1			T24	14		T26	69		T1	146
all_pins[27]	values[0x0]	2668813	1			T24	39		T25	1		T26	113
all_pins[27]	values[0x1]	1625103	1			T24	20		T26	89		T1	225
all_pins[27]	transitions[0x0=>0x1]	974844	1			T24	8		T26	52		T1	125
all_pins[27]	transitions[0x1=>0x0]	974716	1			T24	11		T26	31		T1	158
all_pins[28]	values[0x0]	2656824	1			T24	35		T25	1		T26	148
all_pins[28]	values[0x1]	1637092	1			T24	24		T26	54		T1	234
all_pins[28]	transitions[0x0=>0x1]	980773	1			T24	13		T26	24		T1	158
all_pins[28]	transitions[0x1=>0x0]	968784	1			T24	9		T26	59		T1	149
all_pins[29]	values[0x0]	2664057	1			T24	38		T25	1		T26	95
all_pins[29]	values[0x1]	1629859	1			T24	21		T26	107		T1	280
all_pins[29]	transitions[0x0=>0x1]	972192	1			T24	11		T26	93		T1	176
all_pins[29]	transitions[0x1=>0x0]	979425	1			T24	14		T26	40		T1	130
all_pins[30]	values[0x0]	2667042	1			T24	34		T25	1		T26	128
all_pins[30]	values[0x1]	1626874	1			T24	25		T26	74		T1	234
all_pins[30]	transitions[0x0=>0x1]	972399	1			T24	17		T26	36		T1	125
all_pins[30]	transitions[0x1=>0x0]	975384	1			T24	13		T26	69		T1	171
all_pins[31]	values[0x0]	2675709	1			T24	29		T25	1		T26	116
all_pins[31]	values[0x1]	1618207	1			T24	30		T26	86		T1	216
all_pins[31]	transitions[0x0=>0x1]	965901	1			T24	20		T26	50		T1	119
all_pins[31]	transitions[0x1=>0x0]	974568	1			T24	15		T26	38		T1	137