Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14311054	1			T24	774		T25	88		T26	664
all_values[1]	14311054	1			T24	774		T25	88		T26	664
all_values[2]	14311054	1			T24	774		T25	88		T26	664
all_values[3]	14311054	1			T24	774		T25	88		T26	664
all_values[4]	14311054	1			T24	774		T25	88		T26	664
all_values[5]	14311054	1			T24	774		T25	88		T26	664
all_values[6]	14311054	1			T24	774		T25	88		T26	664
all_values[7]	14311054	1			T24	774		T25	88		T26	664
all_values[8]	14311054	1			T24	774		T25	88		T26	664
all_values[9]	14311054	1			T24	774		T25	88		T26	664
all_values[10]	14311054	1			T24	774		T25	88		T26	664
all_values[11]	14311054	1			T24	774		T25	88		T26	664
all_values[12]	14311054	1			T24	774		T25	88		T26	664
all_values[13]	14311054	1			T24	774		T25	88		T26	664
all_values[14]	14311054	1			T24	774		T25	88		T26	664
all_values[15]	14311054	1			T24	774		T25	88		T26	664
all_values[16]	14311054	1			T24	774		T25	88		T26	664
all_values[17]	14311054	1			T24	774		T25	88		T26	664
all_values[18]	14311054	1			T24	774		T25	88		T26	664
all_values[19]	14311054	1			T24	774		T25	88		T26	664
all_values[20]	14311054	1			T24	774		T25	88		T26	664
all_values[21]	14311054	1			T24	774		T25	88		T26	664
all_values[22]	14311054	1			T24	774		T25	88		T26	664
all_values[23]	14311054	1			T24	774		T25	88		T26	664
all_values[24]	14311054	1			T24	774		T25	88		T26	664
all_values[25]	14311054	1			T24	774		T25	88		T26	664
all_values[26]	14311054	1			T24	774		T25	88		T26	664
all_values[27]	14311054	1			T24	774		T25	88		T26	664
all_values[28]	14311054	1			T24	774		T25	88		T26	664
all_values[29]	14311054	1			T24	774		T25	88		T26	664
all_values[30]	14311054	1			T24	774		T25	88		T26	664
all_values[31]	14311054	1			T24	774		T25	88		T26	664

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

263220066

1

T24

24768

T25

2816

T26

11369

auto[1]

194733662

1

T26

9879

T1

24807

T11

7317

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105698940

1

T24

24768

T25

2816

T26

2448

auto[1]

352254788

1

T26

18800

T1

42597

T11

13337

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

452874181

1

T24

24768

T25

2816

T26

20402

auto[1]

5079547

1

T26

846

T1

1986

T27

98577

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2710441	1			T24	774		T25	88		T26	58
all_values[0]	auto[0]	auto[0]	auto[1]	5433644	1			T26	313		T1	589		T11	216
all_values[0]	auto[0]	auto[1]	auto[0]	588993	1			T26	37		T1	99		T11	6
all_values[0]	auto[0]	auto[1]	auto[1]	5418828	1			T26	234		T1	714		T11	200
all_values[0]	auto[1]	auto[0]	auto[1]	79567	1			T26	11		T1	31		T27	1541
all_values[0]	auto[1]	auto[1]	auto[1]	79581	1			T26	11		T1	29		T27	1564
all_values[1]	auto[0]	auto[0]	auto[0]	2716042	1			T24	774		T25	88		T26	61
all_values[1]	auto[0]	auto[0]	auto[1]	5414158	1			T26	304		T1	612		T11	162
all_values[1]	auto[0]	auto[1]	auto[0]	591521	1			T26	25		T1	69		T11	25
all_values[1]	auto[0]	auto[1]	auto[1]	5430595	1			T26	253		T1	625		T11	231
all_values[1]	auto[1]	auto[0]	auto[1]	79569	1			T26	9		T1	43		T27	1623
all_values[1]	auto[1]	auto[1]	auto[1]	79169	1			T26	12		T1	23		T27	1522
all_values[2]	auto[0]	auto[0]	auto[0]	2715117	1			T24	774		T25	88		T26	56
all_values[2]	auto[0]	auto[0]	auto[1]	5457263	1			T26	359		T1	804		T11	65
all_values[2]	auto[0]	auto[1]	auto[0]	591375	1			T26	15		T1	101		T11	73
all_values[2]	auto[0]	auto[1]	auto[1]	5388471	1			T26	212		T1	477		T11	317
all_values[2]	auto[1]	auto[0]	auto[1]	80004	1			T26	16		T1	36		T27	1514
all_values[2]	auto[1]	auto[1]	auto[1]	78824	1			T26	6		T1	26		T27	1527
all_values[3]	auto[0]	auto[0]	auto[0]	2715077	1			T24	774		T25	88		T26	60
all_values[3]	auto[0]	auto[0]	auto[1]	5410946	1			T26	285		T1	734		T11	234
all_values[3]	auto[0]	auto[1]	auto[0]	591375	1			T26	46		T1	54		T11	13
all_values[3]	auto[0]	auto[1]	auto[1]	5434685	1			T26	248		T1	624		T11	180
all_values[3]	auto[1]	auto[0]	auto[1]	79528	1			T26	15		T1	34		T27	1586
all_values[3]	auto[1]	auto[1]	auto[1]	79443	1			T26	10		T1	36		T27	1545
all_values[4]	auto[0]	auto[0]	auto[0]	2719481	1			T24	774		T25	88		T26	33
all_values[4]	auto[0]	auto[0]	auto[1]	5429582	1			T26	222		T1	540		T11	220
all_values[4]	auto[0]	auto[1]	auto[0]	589819	1			T26	37		T1	160		T11	18
all_values[4]	auto[0]	auto[1]	auto[1]	5413508	1			T26	342		T1	647		T11	213
all_values[4]	auto[1]	auto[0]	auto[1]	79352	1			T26	11		T1	28		T27	1554
all_values[4]	auto[1]	auto[1]	auto[1]	79312	1			T26	19		T1	46		T27	1524
all_values[5]	auto[0]	auto[0]	auto[0]	2717201	1			T24	774		T25	88		T26	36
all_values[5]	auto[0]	auto[0]	auto[1]	5424720	1			T26	215		T1	680		T11	223
all_values[5]	auto[0]	auto[1]	auto[0]	589799	1			T26	33		T1	79		T11	7
all_values[5]	auto[0]	auto[1]	auto[1]	5421003	1			T26	358		T1	633		T11	224
all_values[5]	auto[1]	auto[0]	auto[1]	79508	1			T26	8		T1	32		T27	1631
all_values[5]	auto[1]	auto[1]	auto[1]	78823	1			T26	14		T1	27		T27	1496
all_values[6]	auto[0]	auto[0]	auto[0]	2723356	1			T24	774		T25	88		T26	33
all_values[6]	auto[0]	auto[0]	auto[1]	5445486	1			T26	314		T1	713		T11	323
all_values[6]	auto[0]	auto[1]	auto[0]	574292	1			T26	23		T1	61		T11	3
all_values[6]	auto[0]	auto[1]	auto[1]	5409123	1			T26	263		T1	650		T11	100
all_values[6]	auto[1]	auto[0]	auto[1]	80237	1			T26	11		T1	28		T27	1531
all_values[6]	auto[1]	auto[1]	auto[1]	78560	1			T26	20		T1	28		T27	1549
all_values[7]	auto[0]	auto[0]	auto[0]	2709447	1			T24	774		T25	88		T26	40
all_values[7]	auto[0]	auto[0]	auto[1]	5442777	1			T26	367		T1	529		T11	258
all_values[7]	auto[0]	auto[1]	auto[0]	588079	1			T26	10		T1	153		T11	8
all_values[7]	auto[0]	auto[1]	auto[1]	5412484	1			T26	215		T1	720		T11	172
all_values[7]	auto[1]	auto[0]	auto[1]	79294	1			T26	20		T1	30		T27	1466
all_values[7]	auto[1]	auto[1]	auto[1]	78973	1			T26	12		T1	32		T27	1609
all_values[8]	auto[0]	auto[0]	auto[0]	2718405	1			T24	774		T25	88		T26	51
all_values[8]	auto[0]	auto[0]	auto[1]	5433875	1			T26	247		T1	712		T11	317
all_values[8]	auto[0]	auto[1]	auto[0]	596936	1			T26	23		T1	49		T11	6
all_values[8]	auto[0]	auto[1]	auto[1]	5403066	1			T26	312		T1	571		T11	123
all_values[8]	auto[1]	auto[0]	auto[1]	79759	1			T26	16		T1	30		T27	1544
all_values[8]	auto[1]	auto[1]	auto[1]	79013	1			T26	15		T1	29		T27	1480
all_values[9]	auto[0]	auto[0]	auto[0]	2712394	1			T24	774		T25	88		T26	53
all_values[9]	auto[0]	auto[0]	auto[1]	5453762	1			T26	444		T1	647		T11	128
all_values[9]	auto[0]	auto[1]	auto[0]	595891	1			T26	30		T1	150		T11	67
all_values[9]	auto[0]	auto[1]	auto[1]	5390652	1			T26	113		T1	464		T11	246
all_values[9]	auto[1]	auto[0]	auto[1]	79077	1			T26	19		T1	35		T27	1557
all_values[9]	auto[1]	auto[1]	auto[1]	79278	1			T26	5		T1	21		T27	1549
all_values[10]	auto[0]	auto[0]	auto[0]	2717030	1			T24	774		T25	88		T26	30
all_values[10]	auto[0]	auto[0]	auto[1]	5411492	1			T26	328		T1	725		T11	231
all_values[10]	auto[0]	auto[1]	auto[0]	591072	1			T26	29		T1	106		T11	18
all_values[10]	auto[0]	auto[1]	auto[1]	5432102	1			T26	246		T1	540		T11	200
all_values[10]	auto[1]	auto[0]	auto[1]	80381	1			T26	19		T1	30		T27	1541
all_values[10]	auto[1]	auto[1]	auto[1]	78977	1			T26	12		T1	31		T27	1502
all_values[11]	auto[0]	auto[0]	auto[0]	2710925	1			T24	774		T25	88		T26	66
all_values[11]	auto[0]	auto[0]	auto[1]	5435827	1			T26	435		T1	505		T11	189
all_values[11]	auto[0]	auto[1]	auto[0]	587530	1			T26	4		T1	175		T11	8
all_values[11]	auto[0]	auto[1]	auto[1]	5417880	1			T26	135		T1	724		T11	188
all_values[11]	auto[1]	auto[0]	auto[1]	79866	1			T26	16		T1	24		T27	1509
all_values[11]	auto[1]	auto[1]	auto[1]	79026	1			T26	8		T1	36		T27	1588
all_values[12]	auto[0]	auto[0]	auto[0]	2709085	1			T24	774		T25	88		T26	46
all_values[12]	auto[0]	auto[0]	auto[1]	5456383	1			T26	257		T1	623		T11	226
all_values[12]	auto[0]	auto[1]	auto[0]	588365	1			T26	66		T1	88		T11	47
all_values[12]	auto[0]	auto[1]	auto[1]	5398626	1			T26	268		T1	668		T11	131
all_values[12]	auto[1]	auto[0]	auto[1]	79925	1			T26	12		T1	37		T27	1562
all_values[12]	auto[1]	auto[1]	auto[1]	78670	1			T26	15		T1	27		T27	1495
all_values[13]	auto[0]	auto[0]	auto[0]	2710867	1			T24	774		T25	88		T26	6
all_values[13]	auto[0]	auto[0]	auto[1]	5427061	1			T26	190		T1	584		T11	174
all_values[13]	auto[0]	auto[1]	auto[0]	584224	1			T26	71		T1	113		T11	8
all_values[13]	auto[0]	auto[1]	auto[1]	5430069	1			T26	368		T1	698		T11	267
all_values[13]	auto[1]	auto[0]	auto[1]	80421	1			T26	14		T1	30		T27	1611
all_values[13]	auto[1]	auto[1]	auto[1]	78412	1			T26	15		T1	32		T27	1466
all_values[14]	auto[0]	auto[0]	auto[0]	2715210	1			T24	774		T25	88		T26	69
all_values[14]	auto[0]	auto[0]	auto[1]	5444932	1			T26	339		T1	642		T11	263
all_values[14]	auto[0]	auto[1]	auto[0]	587609	1			T26	4		T1	65		T11	21
all_values[14]	auto[0]	auto[1]	auto[1]	5404670	1			T26	224		T1	714		T11	140
all_values[14]	auto[1]	auto[0]	auto[1]	79679	1			T26	20		T1	36		T27	1547
all_values[14]	auto[1]	auto[1]	auto[1]	78954	1			T26	8		T1	28		T27	1590
all_values[15]	auto[0]	auto[0]	auto[0]	2719699	1			T24	774		T25	88		T26	21
all_values[15]	auto[0]	auto[0]	auto[1]	5464853	1			T26	256		T1	521		T11	189
all_values[15]	auto[0]	auto[1]	auto[0]	584359	1			T26	22		T1	105		T11	26
all_values[15]	auto[0]	auto[1]	auto[1]	5383417	1			T26	339		T1	789		T11	234
all_values[15]	auto[1]	auto[0]	auto[1]	79522	1			T26	14		T1	28		T27	1557
all_values[15]	auto[1]	auto[1]	auto[1]	79204	1			T26	12		T1	41		T27	1482
all_values[16]	auto[0]	auto[0]	auto[0]	2709132	1			T24	774		T25	88		T26	40
all_values[16]	auto[0]	auto[0]	auto[1]	5406514	1			T26	248		T1	660		T11	67
all_values[16]	auto[0]	auto[1]	auto[0]	593919	1			T26	23		T1	58		T11	32
all_values[16]	auto[0]	auto[1]	auto[1]	5442751	1			T26	323		T1	664		T11	348
all_values[16]	auto[1]	auto[0]	auto[1]	79554	1			T26	16		T1	34		T27	1488
all_values[16]	auto[1]	auto[1]	auto[1]	79184	1			T26	14		T1	31		T27	1536
all_values[17]	auto[0]	auto[0]	auto[0]	2712224	1			T24	774		T25	88		T26	17
all_values[17]	auto[0]	auto[0]	auto[1]	5424272	1			T26	225		T1	653		T11	131
all_values[17]	auto[0]	auto[1]	auto[0]	588533	1			T26	29		T1	112		T11	12
all_values[17]	auto[0]	auto[1]	auto[1]	5427324	1			T26	360		T1	619		T11	317
all_values[17]	auto[1]	auto[0]	auto[1]	79579	1			T26	20		T1	30		T27	1521
all_values[17]	auto[1]	auto[1]	auto[1]	79122	1			T26	13		T1	32		T27	1605
all_values[18]	auto[0]	auto[0]	auto[0]	2716063	1			T24	774		T25	88		T26	55
all_values[18]	auto[0]	auto[0]	auto[1]	5421855	1			T26	218		T1	545		T11	251
all_values[18]	auto[0]	auto[1]	auto[0]	588817	1			T26	34		T1	117		T11	4
all_values[18]	auto[0]	auto[1]	auto[1]	5425686	1			T26	333		T1	710		T11	159
all_values[18]	auto[1]	auto[0]	auto[1]	79251	1			T26	9		T1	28		T27	1522
all_values[18]	auto[1]	auto[1]	auto[1]	79382	1			T26	15		T1	36		T27	1578
all_values[19]	auto[0]	auto[0]	auto[0]	2723590	1			T24	774		T25	88		T26	70
all_values[19]	auto[0]	auto[0]	auto[1]	5413887	1			T26	279		T1	751		T11	227
all_values[19]	auto[0]	auto[1]	auto[0]	588543	1			T26	37		T1	110		T11	7
all_values[19]	auto[0]	auto[1]	auto[1]	5426488	1			T26	254		T1	531		T11	183
all_values[19]	auto[1]	auto[0]	auto[1]	79120	1			T26	17		T1	43		T27	1567
all_values[19]	auto[1]	auto[1]	auto[1]	79426	1			T26	7		T1	23		T27	1541
all_values[20]	auto[0]	auto[0]	auto[0]	2727299	1			T24	774		T25	88		T26	81
all_values[20]	auto[0]	auto[0]	auto[1]	5413934	1			T26	301		T1	658		T11	288
all_values[20]	auto[0]	auto[1]	auto[0]	583987	1			T26	72		T1	116		T11	7
all_values[20]	auto[0]	auto[1]	auto[1]	5427030	1			T26	188		T1	613		T11	151
all_values[20]	auto[1]	auto[0]	auto[1]	79251	1			T26	16		T1	29		T27	1496
all_values[20]	auto[1]	auto[1]	auto[1]	79553	1			T26	6		T1	29		T27	1541
all_values[21]	auto[0]	auto[0]	auto[0]	2717290	1			T24	774		T25	88		T26	41
all_values[21]	auto[0]	auto[0]	auto[1]	5445034	1			T26	241		T1	677		T11	165
all_values[21]	auto[0]	auto[1]	auto[0]	590504	1			T26	37		T1	117		T11	50
all_values[21]	auto[0]	auto[1]	auto[1]	5399428	1			T26	319		T1	564		T11	233
all_values[21]	auto[1]	auto[0]	auto[1]	80108	1			T26	14		T1	34		T27	1552
all_values[21]	auto[1]	auto[1]	auto[1]	78690	1			T26	12		T1	23		T27	1483
all_values[22]	auto[0]	auto[0]	auto[0]	2721224	1			T24	774		T25	88		T26	57
all_values[22]	auto[0]	auto[0]	auto[1]	5417421	1			T26	362		T1	517		T11	206
all_values[22]	auto[0]	auto[1]	auto[0]	592024	1			T26	31		T1	149		T11	18
all_values[22]	auto[0]	auto[1]	auto[1]	5421636	1			T26	182		T1	746		T11	198
all_values[22]	auto[1]	auto[0]	auto[1]	79170	1			T26	25		T1	21		T27	1519
all_values[22]	auto[1]	auto[1]	auto[1]	79579	1			T26	7		T1	40		T27	1555
all_values[23]	auto[0]	auto[0]	auto[0]	2714284	1			T24	774		T25	88		T26	47
all_values[23]	auto[0]	auto[0]	auto[1]	5481747	1			T26	263		T1	550		T11	178
all_values[23]	auto[0]	auto[1]	auto[0]	579490	1			T26	28		T1	157		T11	31
all_values[23]	auto[0]	auto[1]	auto[1]	5377168	1			T26	299		T1	669		T11	225
all_values[23]	auto[1]	auto[0]	auto[1]	79504	1			T26	17		T1	24		T27	1447
all_values[23]	auto[1]	auto[1]	auto[1]	78861	1			T26	10		T1	38		T27	1612
all_values[24]	auto[0]	auto[0]	auto[0]	2711381	1			T24	774		T25	88		T26	37
all_values[24]	auto[0]	auto[0]	auto[1]	5423724	1			T26	295		T1	636		T11	136
all_values[24]	auto[0]	auto[1]	auto[0]	588793	1			T26	39		T1	146		T11	25
all_values[24]	auto[0]	auto[1]	auto[1]	5428490	1			T26	269		T1	571		T11	247
all_values[24]	auto[1]	auto[0]	auto[1]	79517	1			T26	14		T1	26		T27	1554
all_values[24]	auto[1]	auto[1]	auto[1]	79149	1			T26	10		T1	31		T27	1454
all_values[25]	auto[0]	auto[0]	auto[0]	2717005	1			T24	774		T25	88		T26	39
all_values[25]	auto[0]	auto[0]	auto[1]	5377437	1			T26	205		T1	657		T11	254
all_values[25]	auto[0]	auto[1]	auto[0]	592216	1			T26	15		T1	111		T11	23
all_values[25]	auto[0]	auto[1]	auto[1]	5465624	1			T26	383		T1	596		T11	172
all_values[25]	auto[1]	auto[0]	auto[1]	80043	1			T26	6		T1	37		T27	1535
all_values[25]	auto[1]	auto[1]	auto[1]	78729	1			T26	16		T1	21		T27	1531
all_values[26]	auto[0]	auto[0]	auto[0]	2712667	1			T24	774		T25	88		T26	54
all_values[26]	auto[0]	auto[0]	auto[1]	5416983	1			T26	352		T1	641		T11	273
all_values[26]	auto[0]	auto[1]	auto[0]	590179	1			T26	25		T1	116		T11	26
all_values[26]	auto[0]	auto[1]	auto[1]	5432707	1			T26	204		T1	645		T11	146
all_values[26]	auto[1]	auto[0]	auto[1]	79921	1			T26	19		T1	29		T27	1544
all_values[26]	auto[1]	auto[1]	auto[1]	78597	1			T26	10		T1	31		T27	1486
all_values[27]	auto[0]	auto[0]	auto[0]	2713314	1			T24	774		T25	88		T26	16
all_values[27]	auto[0]	auto[0]	auto[1]	5446487	1			T26	290		T1	701		T11	251
all_values[27]	auto[0]	auto[1]	auto[0]	584875	1			T26	47		T1	75		T11	27
all_values[27]	auto[0]	auto[1]	auto[1]	5407559	1			T26	288		T1	578		T11	176
all_values[27]	auto[1]	auto[0]	auto[1]	79907	1			T26	13		T1	31		T27	1589
all_values[27]	auto[1]	auto[1]	auto[1]	78912	1			T26	10		T1	31		T27	1501
all_values[28]	auto[0]	auto[0]	auto[0]	2706299	1			T24	774		T25	88		T26	43
all_values[28]	auto[0]	auto[0]	auto[1]	5399252	1			T26	401		T1	628		T11	229
all_values[28]	auto[0]	auto[1]	auto[0]	579988	1			T26	27		T1	113		T11	4
all_values[28]	auto[0]	auto[1]	auto[1]	5466882	1			T26	170		T1	617		T11	224
all_values[28]	auto[1]	auto[0]	auto[1]	79091	1			T26	15		T1	26		T27	1513
all_values[28]	auto[1]	auto[1]	auto[1]	79542	1			T26	8		T1	32		T27	1630
all_values[29]	auto[0]	auto[0]	auto[0]	2707050	1			T24	774		T25	88		T26	36
all_values[29]	auto[0]	auto[0]	auto[1]	5435425	1			T26	222		T1	497		T11	229
all_values[29]	auto[0]	auto[1]	auto[0]	587670	1			T26	36		T1	67		T11	9
all_values[29]	auto[0]	auto[1]	auto[1]	5422229	1			T26	339		T1	854		T11	222
all_values[29]	auto[1]	auto[0]	auto[1]	79399	1			T26	17		T1	16		T27	1509
all_values[29]	auto[1]	auto[1]	auto[1]	79281	1			T26	14		T1	45		T27	1575
all_values[30]	auto[0]	auto[0]	auto[0]	2709908	1			T24	774		T25	88		T26	24
all_values[30]	auto[0]	auto[0]	auto[1]	5435969	1			T26	333		T1	673		T11	260
all_values[30]	auto[0]	auto[1]	auto[0]	586665	1			T26	61		T1	73		T11	44
all_values[30]	auto[0]	auto[1]	auto[1]	5419686	1			T26	222		T1	614		T11	153
all_values[30]	auto[1]	auto[0]	auto[1]	79975	1			T26	13		T1	36		T27	1566
all_values[30]	auto[1]	auto[1]	auto[1]	78851	1			T26	11		T1	24		T27	1505
all_values[31]	auto[0]	auto[0]	auto[0]	2715347	1			T24	774		T25	88		T26	48
all_values[31]	auto[0]	auto[0]	auto[1]	5450537	1			T26	356		T1	590		T11	134
all_values[31]	auto[0]	auto[1]	auto[0]	587644	1			T26	8		T1	135		T11	4
all_values[31]	auto[0]	auto[1]	auto[1]	5398135	1			T26	225		T1	568		T11	320
all_values[31]	auto[1]	auto[0]	auto[1]	79894	1			T26	17		T1	39		T27	1614
all_values[31]	auto[1]	auto[1]	auto[1]	79497	1			T26	10		T1	32		T27	1546

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal