Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[1]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[2]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[3]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[4]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[5]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[6]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[7]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[8]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[9]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[10]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[11]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[12]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[13]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[14]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[15]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[16]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[17]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[18]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[19]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[20]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[21]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[22]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[23]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[24]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[25]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[26]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[27]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[28]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[29]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[30]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[31]	14057055	1			T24	774		T25	156		T26	619

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

267829651

1

T24

12356

T25

3971

T26

14838

auto[1]

181996109

1

T24

12412

T25

1021

T26

4970

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

361144553

1

T24

24768

T25

4395

T26

11053

auto[1]

88681207

1

T25

597

T26

8755

T1

20140

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

335042701

1

T24

24768

T25

2663

T26

10011

auto[1]

114783059

1

T25

2329

T26

9797

T1

22610

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5209845	1			T24	358		T25	25		T26	123
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3868791	1			T24	416		T25	4		T26	6
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1396007	1			T25	8		T26	144		T1	319
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1756601	1			T25	88		T26	134		T1	437
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	446045	1			T25	10		T26	13		T1	12
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1379766	1			T25	21		T26	199		T1	271
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5209835	1			T24	353		T25	34		T26	156
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3862042	1			T24	421		T25	7		T26	6
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1395826	1			T25	4		T26	159		T1	405
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1761703	1			T25	68		T26	143		T1	351
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	444298	1			T25	20		T26	8		T1	14
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1383351	1			T25	23		T26	147		T1	329
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5212007	1			T24	384		T25	76		T26	114
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3855357	1			T24	390		T25	22		T26	6
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1391690	1			T25	4		T26	157		T1	316
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1766796	1			T25	45		T26	143		T1	418
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	450546	1			T25	6		T26	12		T1	15
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1380659	1			T25	3		T26	187		T1	279
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5211835	1			T24	387		T25	93		T26	94
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3858214	1			T24	387		T25	27		T1	9
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1395062	1			T25	18		T26	163		T1	365
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1761557	1			T25	17		T26	194		T1	320
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	444433	1			T25	1		T26	8		T1	9
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1385954	1			T26	160		T1	337		T13	96
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5221651	1			T24	370		T25	94		T26	146
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3854812	1			T24	404		T25	18		T26	6
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1392669	1			T25	5		T26	118		T1	370
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1760972	1			T25	32		T26	201		T1	323
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	448327	1			T25	1		T26	6		T1	6
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1378624	1			T25	6		T26	142		T1	209
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5215289	1			T24	456		T25	99		T26	138
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3855234	1			T24	318		T25	26		T26	13
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1393849	1			T25	24		T26	184		T1	326
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1766970	1			T25	2		T26	139		T1	356
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	447956	1			T26	3		T1	8		T13	25
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1377757	1			T25	5		T26	142		T1	334
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5200429	1			T24	378		T25	52		T26	101
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3871366	1			T24	396		T25	9		T26	4
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1393794	1			T25	3		T26	73		T1	280
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1762356	1			T25	70		T26	222		T1	355
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	448297	1			T25	10		T26	10		T1	11
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1380813	1			T25	12		T26	209		T1	384
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5210640	1			T24	300		T25	33		T26	145
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3864782	1			T24	474		T25	4		T26	3
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1394718	1			T25	11		T26	159		T1	309
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1761266	1			T25	83		T26	143		T1	377
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	444739	1			T25	17		T26	14		T1	9
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1380910	1			T25	8		T26	155		T1	364
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5207091	1			T24	427		T25	56		T26	166
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3869845	1			T24	347		T25	15		T26	13
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1392875	1			T25	11		T26	170		T1	437
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1763866	1			T25	54		T26	136		T1	345
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	442869	1			T25	14		T26	4		T1	6
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1380509	1			T25	6		T26	130		T1	253
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5212247	1			T24	432		T25	60		T26	188
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3860356	1			T24	342		T25	8		T26	11
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1391405	1			T25	6		T26	169		T1	203
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1762096	1			T25	55		T26	159		T1	528
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	447615	1			T25	12		T26	8		T1	12
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1383336	1			T25	15		T26	84		T1	277
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5202935	1			T24	388		T25	74		T26	166
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3862635	1			T24	386		T25	7		T26	4
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1396077	1			T25	7		T26	112		T1	339
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1760492	1			T25	50		T26	189		T1	359
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	449487	1			T25	10		T26	12		T1	10
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1385429	1			T25	8		T26	136		T1	293
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5217148	1			T24	415		T25	63		T26	235
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3864596	1			T24	359		T25	10		T26	15
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1398543	1			T25	3		T26	159		T1	313
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1750063	1			T25	60		T26	89		T1	323
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	447314	1			T25	7		T26	2		T1	6
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1379391	1			T25	13		T26	119		T1	368
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5212959	1			T24	443		T25	32		T26	199
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3863598	1			T24	331		T25	11		T26	10
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1398333	1			T26	108		T1	300		T13	72
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1757393	1			T25	83		T26	169		T1	393
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	445365	1			T25	17		T26	1		T1	7
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1379407	1			T25	13		T26	132		T1	317
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5225340	1			T24	412		T25	37		T26	245
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3853099	1			T24	362		T25	2		T26	7
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1391346	1			T25	6		T26	59		T1	296
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1758540	1			T25	75		T26	221		T1	377
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	445000	1			T25	15		T26	10		T1	4
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1383730	1			T25	21		T26	77		T1	325
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5220665	1			T24	411		T25	45		T26	171
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3858609	1			T24	363		T25	6		T26	6
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1395145	1			T25	8		T26	87		T1	387
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1757223	1			T25	58		T26	162		T1	432
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	447065	1			T25	15		T26	12		T1	18
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1378348	1			T25	24		T26	181		T1	275
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5215336	1			T24	406		T25	77		T26	172
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3869759	1			T24	368		T25	8		T26	11
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1396801	1			T25	2		T26	139		T1	238
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1754664	1			T25	37		T26	167		T1	338
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	444458	1			T25	9		T26	7		T1	16
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1376037	1			T25	23		T26	123		T1	250
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5217098	1			T24	384		T25	44		T26	239
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3863839	1			T24	390		T25	9		T26	15
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1386828	1			T25	15		T26	132		T1	340
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1762338	1			T25	64		T26	121		T1	410
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	447654	1			T25	17		T1	8		T13	31
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1379298	1			T25	7		T26	112		T1	303
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5218602	1			T24	375		T25	138		T26	160
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3862758	1			T24	399		T25	14		T1	11
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1389882	1			T25	4		T26	79		T1	287
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1761286	1			T26	201		T1	473		T13	202
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	448337	1			T26	15		T1	5		T13	39
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1376190	1			T26	164		T1	346		T13	98
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5211926	1			T24	371		T25	39		T26	141
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3867813	1			T24	403		T25	14		T26	12
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1391990	1			T25	8		T26	193		T1	452
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1760280	1			T25	66		T26	145		T1	322
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	448869	1			T25	17		T26	9		T1	16
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1376177	1			T25	12		T26	119		T1	264
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5209413	1			T24	376		T25	101		T26	165
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3865544	1			T24	398		T25	19		T26	10
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1387694	1			T25	16		T26	150		T1	303
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1767483	1			T25	16		T26	182		T1	407
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	447852	1			T25	1		T26	9		T1	16
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1379069	1			T25	3		T26	103		T1	314
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5223295	1			T24	408		T25	109		T26	224
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3861775	1			T24	366		T25	19		T26	5
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1391775	1			T25	17		T26	135		T1	327
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1759167	1			T25	6		T26	158		T1	352
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	444809	1			T25	1		T26	21		T1	6
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1376234	1			T25	4		T26	76		T1	273
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5222704	1			T24	409		T25	16		T26	217
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3854414	1			T24	365		T25	2		T26	14
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1394356	1			T25	2		T26	140		T1	320
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1763648	1			T25	106		T26	90		T1	418
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	445882	1			T25	17		T26	1		T1	5
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1376051	1			T25	13		T26	157		T1	306
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5218559	1			T24	337		T25	89		T26	188
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3858397	1			T24	437		T25	20		T26	12
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1390208	1			T25	19		T26	162		T1	283
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1761973	1			T25	26		T26	138		T1	433
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	448697	1			T26	3		T1	15		T13	34
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1379221	1			T25	2		T26	116		T1	263
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5214034	1			T24	377		T25	26		T26	129
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3865492	1			T24	397		T25	2		T26	15
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1384973	1			T25	5		T26	158		T1	270
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1765478	1			T25	95		T26	114		T1	395
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	446885	1			T25	22		T26	6		T1	14
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1380193	1			T25	6		T26	197		T1	300
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5215076	1			T24	404		T25	118		T26	213
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3862670	1			T24	370		T25	22		T26	10
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1390249	1			T25	8		T26	106		T1	421
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1763984	1			T25	8		T26	181		T1	323
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	445645	1			T26	1		T1	4		T13	29
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1379431	1			T26	108		T1	251		T13	113
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5228985	1			T24	313		T25	73		T26	73
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3853824	1			T24	461		T25	10		T1	10
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1387182	1			T25	11		T26	94		T1	275
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1762762	1			T25	35		T26	229		T1	380
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	448658	1			T25	11		T26	14		T1	13
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1375644	1			T25	16		T26	209		T1	339
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5224221	1			T24	365		T25	77		T26	256
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3857779	1			T24	409		T25	4		T26	9
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1392396	1			T26	134		T1	288		T13	52
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1761796	1			T25	48		T26	128		T1	388
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	447642	1			T25	9		T26	7		T1	14
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1373221	1			T25	18		T26	85		T1	383
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5218655	1			T24	416		T25	104		T26	130
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3864460	1			T24	358		T25	22		T26	13
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1394394	1			T25	13		T26	167		T1	280
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1757954	1			T25	14		T26	164		T1	364
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	445459	1			T25	2		T26	4		T1	5
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1376133	1			T25	1		T26	141		T1	388
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5232209	1			T24	360		T25	6		T26	136
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3849678	1			T24	414		T25	1		T26	2
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1389713	1			T25	1		T26	111		T1	270
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1759291	1			T25	104		T26	222		T1	474
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	447161	1			T25	32		T26	16		T1	10
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1379003	1			T25	12		T26	132		T1	343
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5219199	1			T24	412		T25	110		T26	185
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3862242	1			T24	362		T25	20		T26	11
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1392525	1			T25	26		T26	107		T1	317
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1759973	1			T26	152		T1	422		T13	170
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	447842	1			T26	9		T1	13		T13	29
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1375274	1			T26	155		T1	268		T13	45
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5212290	1			T24	347		T25	3		T26	239
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3870753	1			T24	427		T26	10		T1	12
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1392878	1			T26	102		T1	268		T13	58
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1757237	1			T25	121		T26	162		T1	354
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	447771	1			T25	18		T26	6		T1	5
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1376126	1			T25	14		T26	100		T1	427
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5223580	1			T24	382		T25	21		T26	166
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3855192	1			T24	392		T25	4		T26	15
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1386695	1			T25	8		T26	187		T1	311
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1769467	1			T25	88		T26	103		T1	420
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	450078	1			T25	20		T26	7		T1	6
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1372043	1			T25	15		T26	141		T1	292

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal