Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[1]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[2]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[3]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[4]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[5]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[6]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[7]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[8]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[9]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[10]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[11]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[12]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[13]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[14]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[15]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[16]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[17]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[18]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[19]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[20]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[21]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[22]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[23]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[24]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[25]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[26]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[27]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[28]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[29]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[30]	14057055	1			T24	774		T25	156		T26	619
bins_for_gpio_bits[31]	14057055	1			T24	774		T25	156		T26	619

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

267829651

1

T24

12356

T25

3971

T26

14838

auto[1]

181996109

1

T24

12412

T25

1021

T26

4970

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

267823098

1

T24

12356

T25

3960

T26

14829

auto[1]

182002662

1

T24

12412

T25

1032

T26

4979

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8115289	1			T24	358		T25	116		T26	375
bins_for_gpio_bits[0]	auto[0]	auto[1]	246945	1			T25	5		T26	26		T1	42
bins_for_gpio_bits[0]	auto[1]	auto[0]	247164	1			T25	5		T26	26		T1	42
bins_for_gpio_bits[0]	auto[1]	auto[1]	5447657	1			T24	416		T25	30		T26	192
bins_for_gpio_bits[1]	auto[0]	auto[0]	8120628	1			T24	353		T25	101		T26	443
bins_for_gpio_bits[1]	auto[0]	auto[1]	246524	1			T25	5		T26	15		T1	47
bins_for_gpio_bits[1]	auto[1]	auto[0]	246736	1			T25	5		T26	15		T1	47
bins_for_gpio_bits[1]	auto[1]	auto[1]	5443167	1			T24	421		T25	45		T26	146
bins_for_gpio_bits[2]	auto[0]	auto[0]	8124067	1			T24	384		T25	123		T26	390
bins_for_gpio_bits[2]	auto[0]	auto[1]	246257	1			T25	1		T26	24		T1	40
bins_for_gpio_bits[2]	auto[1]	auto[0]	246426	1			T25	2		T26	24		T1	40
bins_for_gpio_bits[2]	auto[1]	auto[1]	5440305	1			T24	390		T25	30		T26	181
bins_for_gpio_bits[3]	auto[0]	auto[0]	8121389	1			T24	387		T25	128		T26	434
bins_for_gpio_bits[3]	auto[0]	auto[1]	246871	1			T26	17		T1	42		T13	16
bins_for_gpio_bits[3]	auto[1]	auto[0]	247065	1			T26	17		T1	42		T13	17
bins_for_gpio_bits[3]	auto[1]	auto[1]	5441730	1			T24	387		T25	28		T26	151
bins_for_gpio_bits[4]	auto[0]	auto[0]	8128793	1			T24	370		T25	129		T26	445
bins_for_gpio_bits[4]	auto[0]	auto[1]	246295	1			T25	2		T26	20		T1	37
bins_for_gpio_bits[4]	auto[1]	auto[0]	246499	1			T25	2		T26	20		T1	37
bins_for_gpio_bits[4]	auto[1]	auto[1]	5435468	1			T24	404		T25	23		T26	134
bins_for_gpio_bits[5]	auto[0]	auto[0]	8129278	1			T24	456		T25	124		T26	444
bins_for_gpio_bits[5]	auto[0]	auto[1]	246598	1			T25	1		T26	17		T1	41
bins_for_gpio_bits[5]	auto[1]	auto[0]	246830	1			T25	1		T26	17		T1	41
bins_for_gpio_bits[5]	auto[1]	auto[1]	5434349	1			T24	318		T25	30		T26	141
bins_for_gpio_bits[6]	auto[0]	auto[0]	8110319	1			T24	378		T25	121		T26	380
bins_for_gpio_bits[6]	auto[0]	auto[1]	246080	1			T25	4		T26	16		T1	43
bins_for_gpio_bits[6]	auto[1]	auto[0]	246260	1			T25	4		T26	16		T1	43
bins_for_gpio_bits[6]	auto[1]	auto[1]	5454396	1			T24	396		T25	27		T26	207
bins_for_gpio_bits[7]	auto[0]	auto[0]	8119570	1			T24	300		T25	124		T26	426
bins_for_gpio_bits[7]	auto[0]	auto[1]	246852	1			T25	3		T26	20		T1	47
bins_for_gpio_bits[7]	auto[1]	auto[0]	247054	1			T25	3		T26	21		T1	47
bins_for_gpio_bits[7]	auto[1]	auto[1]	5443579	1			T24	474		T25	26		T26	152
bins_for_gpio_bits[8]	auto[0]	auto[0]	8116434	1			T24	427		T25	119		T26	452
bins_for_gpio_bits[8]	auto[0]	auto[1]	247238	1			T25	2		T26	20		T1	44
bins_for_gpio_bits[8]	auto[1]	auto[0]	247398	1			T25	2		T26	20		T1	44
bins_for_gpio_bits[8]	auto[1]	auto[1]	5445985	1			T24	347		T25	33		T26	127
bins_for_gpio_bits[9]	auto[0]	auto[0]	8118677	1			T24	432		T25	117		T26	500
bins_for_gpio_bits[9]	auto[0]	auto[1]	246852	1			T25	4		T26	15		T1	41
bins_for_gpio_bits[9]	auto[1]	auto[0]	247071	1			T25	4		T26	16		T1	41
bins_for_gpio_bits[9]	auto[1]	auto[1]	5444455	1			T24	342		T25	31		T26	88
bins_for_gpio_bits[10]	auto[0]	auto[0]	8112599	1			T24	388		T25	128		T26	449
bins_for_gpio_bits[10]	auto[0]	auto[1]	246733	1			T25	3		T26	17		T1	37
bins_for_gpio_bits[10]	auto[1]	auto[0]	246905	1			T25	3		T26	18		T1	37
bins_for_gpio_bits[10]	auto[1]	auto[1]	5450818	1			T24	386		T25	22		T26	135
bins_for_gpio_bits[11]	auto[0]	auto[0]	8119577	1			T24	415		T25	121		T26	466
bins_for_gpio_bits[11]	auto[0]	auto[1]	245973	1			T25	4		T26	17		T1	48
bins_for_gpio_bits[11]	auto[1]	auto[0]	246177	1			T25	5		T26	17		T1	48
bins_for_gpio_bits[11]	auto[1]	auto[1]	5445328	1			T24	359		T25	26		T26	119
bins_for_gpio_bits[12]	auto[0]	auto[0]	8122125	1			T24	443		T25	111		T26	454
bins_for_gpio_bits[12]	auto[0]	auto[1]	246350	1			T25	3		T26	22		T1	48
bins_for_gpio_bits[12]	auto[1]	auto[0]	246560	1			T25	4		T26	22		T1	48
bins_for_gpio_bits[12]	auto[1]	auto[1]	5442020	1			T24	331		T25	38		T26	121
bins_for_gpio_bits[13]	auto[0]	auto[0]	8128658	1			T24	412		T25	112		T26	515
bins_for_gpio_bits[13]	auto[0]	auto[1]	246353	1			T25	6		T26	10		T1	40
bins_for_gpio_bits[13]	auto[1]	auto[0]	246568	1			T25	6		T26	10		T1	40
bins_for_gpio_bits[13]	auto[1]	auto[1]	5435476	1			T24	362		T25	32		T26	84
bins_for_gpio_bits[14]	auto[0]	auto[0]	8127161	1			T24	411		T25	106		T26	396
bins_for_gpio_bits[14]	auto[0]	auto[1]	245686	1			T25	4		T26	24		T1	51
bins_for_gpio_bits[14]	auto[1]	auto[0]	245872	1			T25	5		T26	24		T1	51
bins_for_gpio_bits[14]	auto[1]	auto[1]	5438336	1			T24	363		T25	41		T26	175
bins_for_gpio_bits[15]	auto[0]	auto[0]	8120505	1			T24	406		T25	112		T26	454
bins_for_gpio_bits[15]	auto[0]	auto[1]	246060	1			T25	4		T26	23		T1	37
bins_for_gpio_bits[15]	auto[1]	auto[0]	246296	1			T25	4		T26	24		T1	37
bins_for_gpio_bits[15]	auto[1]	auto[1]	5444194	1			T24	368		T25	36		T26	118
bins_for_gpio_bits[16]	auto[0]	auto[0]	8119779	1			T24	384		T25	120		T26	477
bins_for_gpio_bits[16]	auto[0]	auto[1]	246278	1			T25	2		T26	14		T1	47
bins_for_gpio_bits[16]	auto[1]	auto[0]	246485	1			T25	3		T26	15		T1	47
bins_for_gpio_bits[16]	auto[1]	auto[1]	5444513	1			T24	390		T25	31		T26	113
bins_for_gpio_bits[17]	auto[0]	auto[0]	8122988	1			T24	375		T25	142		T26	423
bins_for_gpio_bits[17]	auto[0]	auto[1]	246594	1			T26	17		T1	50		T13	12
bins_for_gpio_bits[17]	auto[1]	auto[0]	246782	1			T26	17		T1	50		T13	12
bins_for_gpio_bits[17]	auto[1]	auto[1]	5440691	1			T24	399		T25	14		T26	162
bins_for_gpio_bits[18]	auto[0]	auto[0]	8117206	1			T24	371		T25	108		T26	458
bins_for_gpio_bits[18]	auto[0]	auto[1]	246770	1			T25	4		T26	20		T1	41
bins_for_gpio_bits[18]	auto[1]	auto[0]	246990	1			T25	5		T26	21		T1	41
bins_for_gpio_bits[18]	auto[1]	auto[1]	5446089	1			T24	403		T25	39		T26	120
bins_for_gpio_bits[19]	auto[0]	auto[0]	8117519	1			T24	376		T25	131		T26	481
bins_for_gpio_bits[19]	auto[0]	auto[1]	246851	1			T25	1		T26	16		T1	38
bins_for_gpio_bits[19]	auto[1]	auto[0]	247071	1			T25	2		T26	16		T1	38
bins_for_gpio_bits[19]	auto[1]	auto[1]	5445614	1			T24	398		T25	22		T26	106
bins_for_gpio_bits[20]	auto[0]	auto[0]	8127336	1			T24	408		T25	131		T26	506
bins_for_gpio_bits[20]	auto[0]	auto[1]	246723	1			T25	1		T26	11		T1	43
bins_for_gpio_bits[20]	auto[1]	auto[0]	246901	1			T25	1		T26	11		T1	43
bins_for_gpio_bits[20]	auto[1]	auto[1]	5436095	1			T24	366		T25	23		T26	91
bins_for_gpio_bits[21]	auto[0]	auto[0]	8133534	1			T24	409		T25	121		T26	428
bins_for_gpio_bits[21]	auto[0]	auto[1]	246953	1			T25	3		T26	19		T1	47
bins_for_gpio_bits[21]	auto[1]	auto[0]	247174	1			T25	3		T26	19		T1	47
bins_for_gpio_bits[21]	auto[1]	auto[1]	5429394	1			T24	365		T25	29		T26	153
bins_for_gpio_bits[22]	auto[0]	auto[0]	8123650	1			T24	337		T25	133		T26	471
bins_for_gpio_bits[22]	auto[0]	auto[1]	246899	1			T25	1		T26	17		T1	45
bins_for_gpio_bits[22]	auto[1]	auto[0]	247090	1			T25	1		T26	17		T1	45
bins_for_gpio_bits[22]	auto[1]	auto[1]	5439416	1			T24	437		T25	21		T26	114
bins_for_gpio_bits[23]	auto[0]	auto[0]	8117315	1			T24	377		T25	124		T26	380
bins_for_gpio_bits[23]	auto[0]	auto[1]	246978	1			T25	2		T26	20		T1	45
bins_for_gpio_bits[23]	auto[1]	auto[0]	247170	1			T25	2		T26	21		T1	45
bins_for_gpio_bits[23]	auto[1]	auto[1]	5445592	1			T24	397		T25	28		T26	198
bins_for_gpio_bits[24]	auto[0]	auto[0]	8122256	1			T24	404		T25	134		T26	481
bins_for_gpio_bits[24]	auto[0]	auto[1]	246799	1			T26	18		T1	38		T13	17
bins_for_gpio_bits[24]	auto[1]	auto[0]	247053	1			T26	19		T1	38		T13	18
bins_for_gpio_bits[24]	auto[1]	auto[1]	5440947	1			T24	370		T25	22		T26	101
bins_for_gpio_bits[25]	auto[0]	auto[0]	8132636	1			T24	313		T25	116		T26	373
bins_for_gpio_bits[25]	auto[0]	auto[1]	246040	1			T25	2		T26	22		T1	46
bins_for_gpio_bits[25]	auto[1]	auto[0]	246293	1			T25	3		T26	23		T1	46
bins_for_gpio_bits[25]	auto[1]	auto[1]	5432086	1			T24	461		T25	35		T26	201
bins_for_gpio_bits[26]	auto[0]	auto[0]	8131312	1			T24	365		T25	119		T26	505
bins_for_gpio_bits[26]	auto[0]	auto[1]	246930	1			T25	5		T26	13		T1	55
bins_for_gpio_bits[26]	auto[1]	auto[0]	247101	1			T25	6		T26	13		T1	55
bins_for_gpio_bits[26]	auto[1]	auto[1]	5431712	1			T24	409		T25	26		T26	88
bins_for_gpio_bits[27]	auto[0]	auto[0]	8124516	1			T24	416		T25	130		T26	441
bins_for_gpio_bits[27]	auto[0]	auto[1]	246312	1			T26	20		T1	52		T13	12
bins_for_gpio_bits[27]	auto[1]	auto[0]	246487	1			T25	1		T26	20		T1	52
bins_for_gpio_bits[27]	auto[1]	auto[1]	5439740	1			T24	358		T25	25		T26	138
bins_for_gpio_bits[28]	auto[0]	auto[0]	8133702	1			T24	360		T25	106		T26	451
bins_for_gpio_bits[28]	auto[0]	auto[1]	247264	1			T25	5		T26	18		T1	49
bins_for_gpio_bits[28]	auto[1]	auto[0]	247511	1			T25	5		T26	18		T1	49
bins_for_gpio_bits[28]	auto[1]	auto[1]	5428578	1			T24	414		T25	40		T26	132
bins_for_gpio_bits[29]	auto[0]	auto[0]	8124841	1			T24	412		T25	136		T26	421
bins_for_gpio_bits[29]	auto[0]	auto[1]	246597	1			T26	23		T1	47		T13	8
bins_for_gpio_bits[29]	auto[1]	auto[0]	246856	1			T26	23		T1	47		T13	8
bins_for_gpio_bits[29]	auto[1]	auto[1]	5438761	1			T24	362		T25	20		T26	152
bins_for_gpio_bits[30]	auto[0]	auto[0]	8115721	1			T24	347		T25	117		T26	491
bins_for_gpio_bits[30]	auto[0]	auto[1]	246499	1			T25	6		T26	12		T1	48
bins_for_gpio_bits[30]	auto[1]	auto[0]	246684	1			T25	7		T26	12		T1	48
bins_for_gpio_bits[30]	auto[1]	auto[1]	5448151	1			T24	427		T25	26		T26	104
bins_for_gpio_bits[31]	auto[0]	auto[0]	8133402	1			T24	382		T25	112		T26	437
bins_for_gpio_bits[31]	auto[0]	auto[1]	246162	1			T25	5		T26	19		T1	47
bins_for_gpio_bits[31]	auto[1]	auto[0]	246340	1			T25	5		T26	19		T1	47
bins_for_gpio_bits[31]	auto[1]	auto[1]	5431151	1			T24	392		T25	34		T26	144