Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8223652 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
382 |
| auto[1] |
6087402 |
1 |
|
|
T26 |
282 |
|
T1 |
842 |
|
T11 |
206 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13525912 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
646 |
| auto[1] |
785142 |
1 |
|
|
T26 |
18 |
|
T1 |
32 |
|
T11 |
50 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8191833 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
333 |
| auto[1] |
6119221 |
1 |
|
|
T26 |
331 |
|
T1 |
879 |
|
T11 |
282 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2685526 |
1 |
|
|
T26 |
189 |
|
T1 |
360 |
|
T11 |
133 |
| auto[1] |
auto[0] |
auto[1] |
396741 |
1 |
|
|
T26 |
10 |
|
T1 |
16 |
|
T11 |
27 |
| auto[1] |
auto[1] |
auto[0] |
2648553 |
1 |
|
|
T26 |
124 |
|
T1 |
487 |
|
T11 |
99 |
| auto[1] |
auto[1] |
auto[1] |
388401 |
1 |
|
|
T26 |
8 |
|
T1 |
16 |
|
T11 |
23 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8209769 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
374 |
| auto[1] |
6101285 |
1 |
|
|
T26 |
290 |
|
T1 |
717 |
|
T11 |
256 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13538746 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
652 |
| auto[1] |
772308 |
1 |
|
|
T26 |
12 |
|
T1 |
27 |
|
T11 |
36 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8256276 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
307 |
| auto[1] |
6054778 |
1 |
|
|
T26 |
357 |
|
T1 |
819 |
|
T11 |
166 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2629025 |
1 |
|
|
T26 |
188 |
|
T1 |
421 |
|
T11 |
32 |
| auto[1] |
auto[0] |
auto[1] |
385114 |
1 |
|
|
T26 |
7 |
|
T1 |
13 |
|
T11 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2653445 |
1 |
|
|
T26 |
157 |
|
T1 |
371 |
|
T11 |
98 |
| auto[1] |
auto[1] |
auto[1] |
387194 |
1 |
|
|
T26 |
5 |
|
T1 |
14 |
|
T11 |
29 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8208903 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
377 |
| auto[1] |
6102151 |
1 |
|
|
T26 |
287 |
|
T1 |
677 |
|
T11 |
218 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13529823 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
651 |
| auto[1] |
781231 |
1 |
|
|
T26 |
13 |
|
T1 |
27 |
|
T11 |
58 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8206848 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
336 |
| auto[1] |
6104206 |
1 |
|
|
T26 |
328 |
|
T1 |
908 |
|
T11 |
329 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2666502 |
1 |
|
|
T26 |
179 |
|
T1 |
485 |
|
T11 |
126 |
| auto[1] |
auto[0] |
auto[1] |
390332 |
1 |
|
|
T26 |
5 |
|
T1 |
19 |
|
T11 |
30 |
| auto[1] |
auto[1] |
auto[0] |
2656473 |
1 |
|
|
T26 |
136 |
|
T1 |
396 |
|
T11 |
145 |
| auto[1] |
auto[1] |
auto[1] |
390899 |
1 |
|
|
T26 |
8 |
|
T1 |
8 |
|
T11 |
28 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8226618 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
517 |
| auto[1] |
6084436 |
1 |
|
|
T26 |
147 |
|
T1 |
935 |
|
T11 |
196 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13533474 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
647 |
| auto[1] |
777580 |
1 |
|
|
T26 |
17 |
|
T1 |
23 |
|
T11 |
25 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8229898 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
290 |
| auto[1] |
6081156 |
1 |
|
|
T26 |
374 |
|
T1 |
743 |
|
T11 |
134 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2643818 |
1 |
|
|
T26 |
257 |
|
T1 |
257 |
|
T11 |
54 |
| auto[1] |
auto[0] |
auto[1] |
386409 |
1 |
|
|
T26 |
13 |
|
T1 |
7 |
|
T11 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2659758 |
1 |
|
|
T26 |
100 |
|
T1 |
463 |
|
T11 |
55 |
| auto[1] |
auto[1] |
auto[1] |
391171 |
1 |
|
|
T26 |
4 |
|
T1 |
16 |
|
T11 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8245393 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
315 |
| auto[1] |
6065661 |
1 |
|
|
T26 |
349 |
|
T1 |
783 |
|
T11 |
178 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13535535 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
651 |
| auto[1] |
775519 |
1 |
|
|
T26 |
13 |
|
T1 |
36 |
|
T11 |
46 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8241243 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
303 |
| auto[1] |
6069811 |
1 |
|
|
T26 |
361 |
|
T1 |
871 |
|
T11 |
243 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2646792 |
1 |
|
|
T26 |
126 |
|
T1 |
364 |
|
T11 |
106 |
| auto[1] |
auto[0] |
auto[1] |
387689 |
1 |
|
|
T26 |
5 |
|
T1 |
12 |
|
T11 |
25 |
| auto[1] |
auto[1] |
auto[0] |
2647500 |
1 |
|
|
T26 |
222 |
|
T1 |
471 |
|
T11 |
91 |
| auto[1] |
auto[1] |
auto[1] |
387830 |
1 |
|
|
T26 |
8 |
|
T1 |
24 |
|
T11 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8218349 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
210 |
| auto[1] |
6092705 |
1 |
|
|
T26 |
454 |
|
T1 |
843 |
|
T11 |
275 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13535901 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
655 |
| auto[1] |
775153 |
1 |
|
|
T26 |
9 |
|
T1 |
15 |
|
T11 |
61 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8243735 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
392 |
| auto[1] |
6067319 |
1 |
|
|
T26 |
272 |
|
T1 |
653 |
|
T11 |
285 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2660453 |
1 |
|
|
T26 |
86 |
|
T1 |
311 |
|
T11 |
65 |
| auto[1] |
auto[0] |
auto[1] |
388985 |
1 |
|
|
T26 |
3 |
|
T1 |
8 |
|
T11 |
14 |
| auto[1] |
auto[1] |
auto[0] |
2631713 |
1 |
|
|
T26 |
177 |
|
T1 |
327 |
|
T11 |
159 |
| auto[1] |
auto[1] |
auto[1] |
386168 |
1 |
|
|
T26 |
6 |
|
T1 |
7 |
|
T11 |
47 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8239821 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
428 |
| auto[1] |
6071233 |
1 |
|
|
T26 |
236 |
|
T1 |
807 |
|
T11 |
161 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13532025 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
650 |
| auto[1] |
779029 |
1 |
|
|
T26 |
14 |
|
T1 |
29 |
|
T11 |
30 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8228657 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
369 |
| auto[1] |
6082397 |
1 |
|
|
T26 |
295 |
|
T1 |
800 |
|
T11 |
173 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2661130 |
1 |
|
|
T26 |
130 |
|
T1 |
343 |
|
T11 |
93 |
| auto[1] |
auto[0] |
auto[1] |
390510 |
1 |
|
|
T26 |
5 |
|
T1 |
19 |
|
T11 |
19 |
| auto[1] |
auto[1] |
auto[0] |
2642238 |
1 |
|
|
T26 |
151 |
|
T1 |
428 |
|
T11 |
50 |
| auto[1] |
auto[1] |
auto[1] |
388519 |
1 |
|
|
T26 |
9 |
|
T1 |
10 |
|
T11 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8264074 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
291 |
| auto[1] |
6046980 |
1 |
|
|
T26 |
373 |
|
T1 |
935 |
|
T11 |
260 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13532356 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
644 |
| auto[1] |
778698 |
1 |
|
|
T26 |
20 |
|
T1 |
23 |
|
T11 |
39 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8223350 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
233 |
| auto[1] |
6087704 |
1 |
|
|
T26 |
431 |
|
T1 |
794 |
|
T11 |
188 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2675341 |
1 |
|
|
T26 |
133 |
|
T1 |
325 |
|
T11 |
86 |
| auto[1] |
auto[0] |
auto[1] |
393333 |
1 |
|
|
T26 |
3 |
|
T1 |
7 |
|
T11 |
24 |
| auto[1] |
auto[1] |
auto[0] |
2633665 |
1 |
|
|
T26 |
278 |
|
T1 |
446 |
|
T11 |
63 |
| auto[1] |
auto[1] |
auto[1] |
385365 |
1 |
|
|
T26 |
17 |
|
T1 |
16 |
|
T11 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8195200 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
304 |
| auto[1] |
6115854 |
1 |
|
|
T26 |
360 |
|
T1 |
753 |
|
T11 |
380 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13530421 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
658 |
| auto[1] |
780633 |
1 |
|
|
T26 |
6 |
|
T1 |
28 |
|
T11 |
45 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8213982 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
402 |
| auto[1] |
6097072 |
1 |
|
|
T26 |
262 |
|
T1 |
794 |
|
T11 |
247 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2647550 |
1 |
|
|
T26 |
117 |
|
T1 |
370 |
|
T11 |
41 |
| auto[1] |
auto[0] |
auto[1] |
387809 |
1 |
|
|
T26 |
2 |
|
T1 |
13 |
|
T11 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2668889 |
1 |
|
|
T26 |
139 |
|
T1 |
396 |
|
T11 |
161 |
| auto[1] |
auto[1] |
auto[1] |
392824 |
1 |
|
|
T26 |
4 |
|
T1 |
15 |
|
T11 |
38 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8216075 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
262 |
| auto[1] |
6094979 |
1 |
|
|
T26 |
402 |
|
T1 |
763 |
|
T11 |
329 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13531520 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
656 |
| auto[1] |
779534 |
1 |
|
|
T26 |
8 |
|
T1 |
39 |
|
T11 |
55 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8207314 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
304 |
| auto[1] |
6103740 |
1 |
|
|
T26 |
360 |
|
T1 |
953 |
|
T11 |
264 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2674320 |
1 |
|
|
T26 |
117 |
|
T1 |
410 |
|
T11 |
31 |
| auto[1] |
auto[0] |
auto[1] |
392430 |
1 |
|
|
T26 |
2 |
|
T1 |
15 |
|
T11 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2649886 |
1 |
|
|
T26 |
235 |
|
T1 |
504 |
|
T11 |
178 |
| auto[1] |
auto[1] |
auto[1] |
387104 |
1 |
|
|
T26 |
6 |
|
T1 |
24 |
|
T11 |
47 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8217169 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
282 |
| auto[1] |
6093885 |
1 |
|
|
T26 |
382 |
|
T1 |
863 |
|
T11 |
163 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13529089 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
654 |
| auto[1] |
781965 |
1 |
|
|
T26 |
10 |
|
T1 |
27 |
|
T11 |
61 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8204217 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
338 |
| auto[1] |
6106837 |
1 |
|
|
T26 |
326 |
|
T1 |
795 |
|
T11 |
291 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2668282 |
1 |
|
|
T26 |
114 |
|
T1 |
359 |
|
T11 |
146 |
| auto[1] |
auto[0] |
auto[1] |
392623 |
1 |
|
|
T26 |
5 |
|
T1 |
10 |
|
T11 |
43 |
| auto[1] |
auto[1] |
auto[0] |
2656590 |
1 |
|
|
T26 |
202 |
|
T1 |
409 |
|
T11 |
84 |
| auto[1] |
auto[1] |
auto[1] |
389342 |
1 |
|
|
T26 |
5 |
|
T1 |
17 |
|
T11 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8216597 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
366 |
| auto[1] |
6094457 |
1 |
|
|
T26 |
298 |
|
T1 |
664 |
|
T11 |
190 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13534131 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
649 |
| auto[1] |
776923 |
1 |
|
|
T26 |
15 |
|
T1 |
23 |
|
T11 |
47 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8224156 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
364 |
| auto[1] |
6086898 |
1 |
|
|
T26 |
300 |
|
T1 |
735 |
|
T11 |
279 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2643750 |
1 |
|
|
T26 |
135 |
|
T1 |
459 |
|
T11 |
121 |
| auto[1] |
auto[0] |
auto[1] |
386139 |
1 |
|
|
T26 |
8 |
|
T1 |
11 |
|
T11 |
28 |
| auto[1] |
auto[1] |
auto[0] |
2666225 |
1 |
|
|
T26 |
150 |
|
T1 |
253 |
|
T11 |
111 |
| auto[1] |
auto[1] |
auto[1] |
390784 |
1 |
|
|
T26 |
7 |
|
T1 |
12 |
|
T11 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8252384 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
431 |
| auto[1] |
6058670 |
1 |
|
|
T26 |
233 |
|
T1 |
604 |
|
T11 |
390 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13532927 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
651 |
| auto[1] |
778127 |
1 |
|
|
T26 |
13 |
|
T1 |
26 |
|
T11 |
37 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8224613 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
330 |
| auto[1] |
6086441 |
1 |
|
|
T26 |
334 |
|
T1 |
707 |
|
T11 |
209 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2676592 |
1 |
|
|
T26 |
228 |
|
T1 |
408 |
|
T11 |
41 |
| auto[1] |
auto[0] |
auto[1] |
392358 |
1 |
|
|
T26 |
11 |
|
T1 |
17 |
|
T11 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2631722 |
1 |
|
|
T26 |
93 |
|
T1 |
273 |
|
T11 |
131 |
| auto[1] |
auto[1] |
auto[1] |
385769 |
1 |
|
|
T26 |
2 |
|
T1 |
9 |
|
T11 |
29 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8220484 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
398 |
| auto[1] |
6090570 |
1 |
|
|
T26 |
266 |
|
T1 |
758 |
|
T11 |
158 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13528171 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
658 |
| auto[1] |
782883 |
1 |
|
|
T26 |
6 |
|
T1 |
29 |
|
T11 |
21 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8201434 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
417 |
| auto[1] |
6109620 |
1 |
|
|
T26 |
247 |
|
T1 |
682 |
|
T11 |
105 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2653356 |
1 |
|
|
T26 |
109 |
|
T1 |
316 |
|
T11 |
68 |
| auto[1] |
auto[0] |
auto[1] |
390845 |
1 |
|
|
T26 |
3 |
|
T1 |
13 |
|
T11 |
17 |
| auto[1] |
auto[1] |
auto[0] |
2673381 |
1 |
|
|
T26 |
132 |
|
T1 |
337 |
|
T11 |
16 |
| auto[1] |
auto[1] |
auto[1] |
392038 |
1 |
|
|
T26 |
3 |
|
T1 |
16 |
|
T11 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8242432 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
296 |
| auto[1] |
6068622 |
1 |
|
|
T26 |
368 |
|
T1 |
704 |
|
T11 |
283 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13530729 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
649 |
| auto[1] |
780325 |
1 |
|
|
T26 |
15 |
|
T1 |
34 |
|
T11 |
69 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8220442 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
318 |
| auto[1] |
6090612 |
1 |
|
|
T26 |
346 |
|
T1 |
782 |
|
T11 |
376 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2677180 |
1 |
|
|
T26 |
157 |
|
T1 |
456 |
|
T11 |
127 |
| auto[1] |
auto[0] |
auto[1] |
394220 |
1 |
|
|
T26 |
8 |
|
T1 |
17 |
|
T11 |
30 |
| auto[1] |
auto[1] |
auto[0] |
2633107 |
1 |
|
|
T26 |
174 |
|
T1 |
292 |
|
T11 |
180 |
| auto[1] |
auto[1] |
auto[1] |
386105 |
1 |
|
|
T26 |
7 |
|
T1 |
17 |
|
T11 |
39 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8217815 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
444 |
| auto[1] |
6093239 |
1 |
|
|
T26 |
220 |
|
T1 |
935 |
|
T11 |
216 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13532875 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
650 |
| auto[1] |
778179 |
1 |
|
|
T26 |
14 |
|
T1 |
29 |
|
T11 |
60 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8232877 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
298 |
| auto[1] |
6078177 |
1 |
|
|
T26 |
366 |
|
T1 |
869 |
|
T11 |
269 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2645983 |
1 |
|
|
T26 |
181 |
|
T1 |
331 |
|
T11 |
80 |
| auto[1] |
auto[0] |
auto[1] |
389042 |
1 |
|
|
T26 |
5 |
|
T1 |
14 |
|
T11 |
23 |
| auto[1] |
auto[1] |
auto[0] |
2654015 |
1 |
|
|
T26 |
171 |
|
T1 |
509 |
|
T11 |
129 |
| auto[1] |
auto[1] |
auto[1] |
389137 |
1 |
|
|
T26 |
9 |
|
T1 |
15 |
|
T11 |
37 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8275535 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
327 |
| auto[1] |
6035519 |
1 |
|
|
T26 |
337 |
|
T1 |
864 |
|
T11 |
256 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13532784 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
651 |
| auto[1] |
778270 |
1 |
|
|
T26 |
13 |
|
T1 |
33 |
|
T11 |
26 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8230241 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
409 |
| auto[1] |
6080813 |
1 |
|
|
T26 |
255 |
|
T1 |
822 |
|
T11 |
132 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2677501 |
1 |
|
|
T26 |
116 |
|
T1 |
335 |
|
T11 |
62 |
| auto[1] |
auto[0] |
auto[1] |
394681 |
1 |
|
|
T26 |
1 |
|
T1 |
14 |
|
T11 |
13 |
| auto[1] |
auto[1] |
auto[0] |
2625042 |
1 |
|
|
T26 |
126 |
|
T1 |
454 |
|
T11 |
44 |
| auto[1] |
auto[1] |
auto[1] |
383589 |
1 |
|
|
T26 |
12 |
|
T1 |
19 |
|
T11 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8214622 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
346 |
| auto[1] |
6096432 |
1 |
|
|
T26 |
318 |
|
T1 |
748 |
|
T11 |
272 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13532963 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
654 |
| auto[1] |
778091 |
1 |
|
|
T26 |
10 |
|
T1 |
26 |
|
T11 |
38 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8220283 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
282 |
| auto[1] |
6090771 |
1 |
|
|
T26 |
382 |
|
T1 |
802 |
|
T11 |
182 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2658480 |
1 |
|
|
T26 |
179 |
|
T1 |
392 |
|
T11 |
28 |
| auto[1] |
auto[0] |
auto[1] |
388668 |
1 |
|
|
T26 |
7 |
|
T1 |
15 |
|
T11 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2654200 |
1 |
|
|
T26 |
193 |
|
T1 |
384 |
|
T11 |
116 |
| auto[1] |
auto[1] |
auto[1] |
389423 |
1 |
|
|
T26 |
3 |
|
T1 |
11 |
|
T11 |
31 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8174485 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
250 |
| auto[1] |
6136569 |
1 |
|
|
T26 |
414 |
|
T1 |
728 |
|
T11 |
195 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13533298 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
653 |
| auto[1] |
777756 |
1 |
|
|
T26 |
11 |
|
T1 |
31 |
|
T11 |
40 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8221368 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
410 |
| auto[1] |
6089686 |
1 |
|
|
T26 |
254 |
|
T1 |
768 |
|
T11 |
222 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2634252 |
1 |
|
|
T26 |
90 |
|
T1 |
341 |
|
T11 |
107 |
| auto[1] |
auto[0] |
auto[1] |
383416 |
1 |
|
|
T26 |
4 |
|
T1 |
17 |
|
T11 |
21 |
| auto[1] |
auto[1] |
auto[0] |
2677678 |
1 |
|
|
T26 |
153 |
|
T1 |
396 |
|
T11 |
75 |
| auto[1] |
auto[1] |
auto[1] |
394340 |
1 |
|
|
T26 |
7 |
|
T1 |
14 |
|
T11 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |