Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8221429 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
259 |
| auto[1] |
6089625 |
1 |
|
|
T26 |
405 |
|
T1 |
739 |
|
T11 |
231 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13532917 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
655 |
| auto[1] |
778137 |
1 |
|
|
T26 |
9 |
|
T1 |
28 |
|
T11 |
28 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8221980 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
377 |
| auto[1] |
6089074 |
1 |
|
|
T26 |
287 |
|
T1 |
836 |
|
T11 |
130 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2638145 |
1 |
|
|
T26 |
124 |
|
T1 |
376 |
|
T11 |
26 |
| auto[1] |
auto[0] |
auto[1] |
385757 |
1 |
|
|
T26 |
4 |
|
T1 |
13 |
|
T11 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2672792 |
1 |
|
|
T26 |
154 |
|
T1 |
432 |
|
T11 |
76 |
| auto[1] |
auto[1] |
auto[1] |
392380 |
1 |
|
|
T26 |
5 |
|
T1 |
15 |
|
T11 |
22 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |