Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8249079 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
358 |
| auto[1] |
6061975 |
1 |
|
|
T26 |
306 |
|
T1 |
739 |
|
T11 |
103 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13534480 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
653 |
| auto[1] |
776574 |
1 |
|
|
T26 |
11 |
|
T1 |
32 |
|
T11 |
66 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8233775 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
348 |
| auto[1] |
6077279 |
1 |
|
|
T26 |
316 |
|
T1 |
819 |
|
T11 |
338 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2666259 |
1 |
|
|
T26 |
130 |
|
T1 |
418 |
|
T11 |
189 |
| auto[1] |
auto[0] |
auto[1] |
390252 |
1 |
|
|
T26 |
5 |
|
T1 |
15 |
|
T11 |
46 |
| auto[1] |
auto[1] |
auto[0] |
2634446 |
1 |
|
|
T26 |
175 |
|
T1 |
369 |
|
T11 |
83 |
| auto[1] |
auto[1] |
auto[1] |
386322 |
1 |
|
|
T26 |
6 |
|
T1 |
17 |
|
T11 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |