Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8231518 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
427 |
| auto[1] |
6079536 |
1 |
|
|
T26 |
237 |
|
T1 |
905 |
|
T11 |
180 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13532361 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
650 |
| auto[1] |
778693 |
1 |
|
|
T26 |
14 |
|
T1 |
35 |
|
T11 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8221500 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
295 |
| auto[1] |
6089554 |
1 |
|
|
T26 |
369 |
|
T1 |
909 |
|
T11 |
95 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2664502 |
1 |
|
|
T26 |
211 |
|
T1 |
333 |
|
T11 |
81 |
| auto[1] |
auto[0] |
auto[1] |
391392 |
1 |
|
|
T26 |
6 |
|
T1 |
13 |
|
T11 |
14 |
| auto[1] |
auto[1] |
auto[0] |
2646359 |
1 |
|
|
T26 |
144 |
|
T1 |
541 |
|
T12 |
69 |
| auto[1] |
auto[1] |
auto[1] |
387301 |
1 |
|
|
T26 |
8 |
|
T1 |
22 |
|
T12 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |