Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8232039 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
314 |
| auto[1] |
6079015 |
1 |
|
|
T26 |
350 |
|
T1 |
649 |
|
T11 |
129 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13542802 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
654 |
| auto[1] |
768252 |
1 |
|
|
T26 |
10 |
|
T1 |
24 |
|
T11 |
57 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8280239 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
374 |
| auto[1] |
6030815 |
1 |
|
|
T26 |
290 |
|
T1 |
794 |
|
T11 |
296 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2633020 |
1 |
|
|
T26 |
99 |
|
T1 |
443 |
|
T11 |
168 |
| auto[1] |
auto[0] |
auto[1] |
384137 |
1 |
|
|
T26 |
3 |
|
T1 |
10 |
|
T11 |
42 |
| auto[1] |
auto[1] |
auto[0] |
2629543 |
1 |
|
|
T26 |
181 |
|
T1 |
327 |
|
T11 |
71 |
| auto[1] |
auto[1] |
auto[1] |
384115 |
1 |
|
|
T26 |
7 |
|
T1 |
14 |
|
T11 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |