Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8245233 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
516 |
| auto[1] |
6065821 |
1 |
|
|
T26 |
148 |
|
T1 |
635 |
|
T11 |
313 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13534937 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
646 |
| auto[1] |
776117 |
1 |
|
|
T26 |
18 |
|
T1 |
26 |
|
T11 |
50 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8233613 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
245 |
| auto[1] |
6077441 |
1 |
|
|
T26 |
419 |
|
T1 |
839 |
|
T11 |
236 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2673816 |
1 |
|
|
T26 |
304 |
|
T1 |
456 |
|
T11 |
53 |
| auto[1] |
auto[0] |
auto[1] |
392939 |
1 |
|
|
T26 |
17 |
|
T1 |
14 |
|
T11 |
15 |
| auto[1] |
auto[1] |
auto[0] |
2627508 |
1 |
|
|
T26 |
97 |
|
T1 |
357 |
|
T11 |
133 |
| auto[1] |
auto[1] |
auto[1] |
383178 |
1 |
|
|
T26 |
1 |
|
T1 |
12 |
|
T11 |
35 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |