Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8223652 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
382 |
| auto[1] |
6087402 |
1 |
|
|
T26 |
282 |
|
T1 |
842 |
|
T11 |
206 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11793785 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
548 |
| auto[1] |
2517269 |
1 |
|
|
T26 |
116 |
|
T1 |
204 |
|
T11 |
66 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8220652 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
364 |
| auto[1] |
6090402 |
1 |
|
|
T26 |
300 |
|
T1 |
889 |
|
T11 |
115 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1787844 |
1 |
|
|
T26 |
88 |
|
T1 |
316 |
|
T11 |
24 |
| auto[1] |
auto[0] |
auto[1] |
1260426 |
1 |
|
|
T26 |
58 |
|
T1 |
115 |
|
T11 |
35 |
| auto[1] |
auto[1] |
auto[0] |
1785289 |
1 |
|
|
T26 |
96 |
|
T1 |
369 |
|
T11 |
25 |
| auto[1] |
auto[1] |
auto[1] |
1256843 |
1 |
|
|
T26 |
58 |
|
T1 |
89 |
|
T11 |
31 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |