Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8209769 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
374 |
| auto[1] |
6101285 |
1 |
|
|
T26 |
290 |
|
T1 |
717 |
|
T11 |
256 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11809893 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
594 |
| auto[1] |
2501161 |
1 |
|
|
T26 |
70 |
|
T1 |
222 |
|
T11 |
116 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8246138 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
341 |
| auto[1] |
6064916 |
1 |
|
|
T26 |
323 |
|
T1 |
965 |
|
T11 |
236 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1782143 |
1 |
|
|
T26 |
149 |
|
T1 |
436 |
|
T11 |
61 |
| auto[1] |
auto[0] |
auto[1] |
1252323 |
1 |
|
|
T26 |
45 |
|
T1 |
114 |
|
T11 |
72 |
| auto[1] |
auto[1] |
auto[0] |
1781612 |
1 |
|
|
T26 |
104 |
|
T1 |
307 |
|
T11 |
59 |
| auto[1] |
auto[1] |
auto[1] |
1248838 |
1 |
|
|
T26 |
25 |
|
T1 |
108 |
|
T11 |
44 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |