Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8208903 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
377 |
| auto[1] |
6102151 |
1 |
|
|
T26 |
287 |
|
T1 |
677 |
|
T11 |
218 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11792929 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
569 |
| auto[1] |
2518125 |
1 |
|
|
T26 |
95 |
|
T1 |
127 |
|
T11 |
141 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8238372 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
328 |
| auto[1] |
6072682 |
1 |
|
|
T26 |
336 |
|
T1 |
732 |
|
T11 |
278 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1771864 |
1 |
|
|
T26 |
141 |
|
T1 |
317 |
|
T11 |
72 |
| auto[1] |
auto[0] |
auto[1] |
1258344 |
1 |
|
|
T26 |
45 |
|
T1 |
84 |
|
T11 |
77 |
| auto[1] |
auto[1] |
auto[0] |
1782693 |
1 |
|
|
T26 |
100 |
|
T1 |
288 |
|
T11 |
65 |
| auto[1] |
auto[1] |
auto[1] |
1259781 |
1 |
|
|
T26 |
50 |
|
T1 |
43 |
|
T11 |
64 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |