Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8226618 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
517 |
| auto[1] |
6084436 |
1 |
|
|
T26 |
147 |
|
T1 |
935 |
|
T11 |
196 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11793883 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
600 |
| auto[1] |
2517171 |
1 |
|
|
T26 |
64 |
|
T1 |
195 |
|
T11 |
105 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8208111 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
339 |
| auto[1] |
6102943 |
1 |
|
|
T26 |
325 |
|
T1 |
756 |
|
T11 |
235 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1801334 |
1 |
|
|
T26 |
227 |
|
T1 |
197 |
|
T11 |
72 |
| auto[1] |
auto[0] |
auto[1] |
1262123 |
1 |
|
|
T26 |
33 |
|
T1 |
87 |
|
T11 |
58 |
| auto[1] |
auto[1] |
auto[0] |
1784438 |
1 |
|
|
T26 |
34 |
|
T1 |
364 |
|
T11 |
58 |
| auto[1] |
auto[1] |
auto[1] |
1255048 |
1 |
|
|
T26 |
31 |
|
T1 |
108 |
|
T11 |
47 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |