Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8245393 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
315 |
| auto[1] |
6065661 |
1 |
|
|
T26 |
349 |
|
T1 |
783 |
|
T11 |
178 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11780371 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
590 |
| auto[1] |
2530683 |
1 |
|
|
T26 |
74 |
|
T1 |
142 |
|
T11 |
159 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8182292 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
383 |
| auto[1] |
6128762 |
1 |
|
|
T26 |
281 |
|
T1 |
665 |
|
T11 |
315 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1801916 |
1 |
|
|
T26 |
129 |
|
T1 |
287 |
|
T11 |
103 |
| auto[1] |
auto[0] |
auto[1] |
1264918 |
1 |
|
|
T26 |
40 |
|
T1 |
53 |
|
T11 |
93 |
| auto[1] |
auto[1] |
auto[0] |
1796163 |
1 |
|
|
T26 |
78 |
|
T1 |
236 |
|
T11 |
53 |
| auto[1] |
auto[1] |
auto[1] |
1265765 |
1 |
|
|
T26 |
34 |
|
T1 |
89 |
|
T11 |
66 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |