Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8209571 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
425 |
| auto[1] |
6101483 |
1 |
|
|
T26 |
239 |
|
T1 |
792 |
|
T11 |
172 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13536685 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
649 |
| auto[1] |
774369 |
1 |
|
|
T26 |
15 |
|
T1 |
26 |
|
T11 |
49 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8255754 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
310 |
| auto[1] |
6055300 |
1 |
|
|
T26 |
354 |
|
T1 |
715 |
|
T11 |
269 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2640505 |
1 |
|
|
T26 |
219 |
|
T1 |
367 |
|
T11 |
128 |
| auto[1] |
auto[0] |
auto[1] |
386125 |
1 |
|
|
T26 |
6 |
|
T1 |
16 |
|
T11 |
33 |
| auto[1] |
auto[1] |
auto[0] |
2640426 |
1 |
|
|
T26 |
120 |
|
T1 |
322 |
|
T11 |
92 |
| auto[1] |
auto[1] |
auto[1] |
388244 |
1 |
|
|
T26 |
9 |
|
T1 |
10 |
|
T11 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |