Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8218349 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
210 |
| auto[1] |
6092705 |
1 |
|
|
T26 |
454 |
|
T1 |
843 |
|
T11 |
275 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11796972 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
610 |
| auto[1] |
2514082 |
1 |
|
|
T26 |
54 |
|
T1 |
150 |
|
T11 |
146 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8229215 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
331 |
| auto[1] |
6081839 |
1 |
|
|
T26 |
333 |
|
T1 |
700 |
|
T11 |
263 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1792618 |
1 |
|
|
T26 |
60 |
|
T1 |
234 |
|
T11 |
47 |
| auto[1] |
auto[0] |
auto[1] |
1261701 |
1 |
|
|
T26 |
6 |
|
T1 |
69 |
|
T11 |
61 |
| auto[1] |
auto[1] |
auto[0] |
1775139 |
1 |
|
|
T26 |
219 |
|
T1 |
316 |
|
T11 |
70 |
| auto[1] |
auto[1] |
auto[1] |
1252381 |
1 |
|
|
T26 |
48 |
|
T1 |
81 |
|
T11 |
85 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |