Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8239821 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
428 |
| auto[1] |
6071233 |
1 |
|
|
T26 |
236 |
|
T1 |
807 |
|
T11 |
161 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11799705 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
515 |
| auto[1] |
2511349 |
1 |
|
|
T26 |
149 |
|
T1 |
145 |
|
T11 |
108 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8223828 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
239 |
| auto[1] |
6087226 |
1 |
|
|
T26 |
425 |
|
T1 |
828 |
|
T11 |
200 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1801855 |
1 |
|
|
T26 |
176 |
|
T1 |
331 |
|
T11 |
40 |
| auto[1] |
auto[0] |
auto[1] |
1261076 |
1 |
|
|
T26 |
65 |
|
T1 |
62 |
|
T11 |
56 |
| auto[1] |
auto[1] |
auto[0] |
1774022 |
1 |
|
|
T26 |
100 |
|
T1 |
352 |
|
T11 |
52 |
| auto[1] |
auto[1] |
auto[1] |
1250273 |
1 |
|
|
T26 |
84 |
|
T1 |
83 |
|
T11 |
52 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |