Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8264074 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
291 |
| auto[1] |
6046980 |
1 |
|
|
T26 |
373 |
|
T1 |
935 |
|
T11 |
260 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11808795 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
589 |
| auto[1] |
2502259 |
1 |
|
|
T26 |
75 |
|
T1 |
140 |
|
T11 |
144 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8254862 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
379 |
| auto[1] |
6056192 |
1 |
|
|
T26 |
285 |
|
T1 |
784 |
|
T11 |
322 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1792286 |
1 |
|
|
T26 |
98 |
|
T1 |
209 |
|
T11 |
69 |
| auto[1] |
auto[0] |
auto[1] |
1261574 |
1 |
|
|
T26 |
27 |
|
T1 |
58 |
|
T11 |
79 |
| auto[1] |
auto[1] |
auto[0] |
1761647 |
1 |
|
|
T26 |
112 |
|
T1 |
435 |
|
T11 |
109 |
| auto[1] |
auto[1] |
auto[1] |
1240685 |
1 |
|
|
T26 |
48 |
|
T1 |
82 |
|
T11 |
65 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |