Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8195200 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
304 |
| auto[1] |
6115854 |
1 |
|
|
T26 |
360 |
|
T1 |
753 |
|
T11 |
380 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11795862 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
595 |
| auto[1] |
2515192 |
1 |
|
|
T26 |
69 |
|
T1 |
149 |
|
T11 |
80 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8244168 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
353 |
| auto[1] |
6066886 |
1 |
|
|
T26 |
311 |
|
T1 |
748 |
|
T11 |
160 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1776138 |
1 |
|
|
T26 |
93 |
|
T1 |
305 |
|
T11 |
21 |
| auto[1] |
auto[0] |
auto[1] |
1253351 |
1 |
|
|
T26 |
16 |
|
T1 |
59 |
|
T11 |
12 |
| auto[1] |
auto[1] |
auto[0] |
1775556 |
1 |
|
|
T26 |
149 |
|
T1 |
294 |
|
T11 |
59 |
| auto[1] |
auto[1] |
auto[1] |
1261841 |
1 |
|
|
T26 |
53 |
|
T1 |
90 |
|
T11 |
68 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |